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1. 发明授权

US5649170A Interconnect and driver optimization for high performance processors 失效
标题翻译：高性能处理器的互连和驱动优化
公开(公告)号：US5649170A
公开(公告)日：1997-07-15
申请号：US497175
申请日：1995-06-30
申请人： Barbara Alane Chappell , Parsotam Trikam Patel , Phoung Kim Phan , George Anthony Sai Halasz
发明人： Barbara Alane Chappell , Parsotam Trikam Patel , Phoung Kim Phan , George Anthony Sai Halasz
IPC分类号： G06F17/50 , H01L27/02 , H03H11/26
CPC分类号： H01L27/0207 , G06F17/505 , G06F17/5068
摘要： A method for determining an optimal design for wiring interconnect and driver power for a designed target delay begins at the floor planning stages of the chip design and may be repeated during the design process. The designer initially specifies a maximum width that wires are allowed to use and a target delay value. Then the designer gives values to weights used in the calculation of an optimization function G(d,p,w), where d is the delay, p is the power, and w is wire width. An "ideal" slope ##EQU1## is calculated, assuming zero resistance. The designer chooses a slope decrease value from the "ideal" slope value. For each set wire width, the delay (at the proper slope) belonging to that particular wire width is obtained. With these inputs, an optimization program according to the invention is run. This program then calculates values of the function G(d,p,w) for increasing wire pitches, starting with the minimum allowed by the technology. The process continues until (1) the target delay is set by the designer is met, (2) the largest pitch value allowed by the designer is reached, or (3) further calculation will not yield a smaller value for the optimization function.
摘要翻译：用于确定用于设计的目标延迟的布线互连和驱动器功率的最佳设计的方法从芯片设计的平面布置阶段开始，并且可以在设计过程期间重复。设计师最初规定允许使用电线的最大宽度和目标延迟值。然后，设计人员给出了计算优化函数G（d，p，w）时使用的权重值，其中d是延迟，p是功率，w是线宽。一个“理想”的斜坡。设计者从“理想”斜率值中选择斜率减小值。对于每组设置的线宽，获得属于该特定线宽的延迟（以适当的斜率）。利用这些输入，执行根据本发明的优化程序。该程序然后计算用于增加线间距的函数G（d，p，w）的值，从该技术允许的最小值开始。该过程一直持续到（1）设计人员满足目标延迟，（2）达到设计师允许的最大间距值，或者（3）进一步的计算不会产生较小的优化函数值。

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