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1. 发明授权

US07544968B1 Non-volatile memory cell with charge storage element and method of programming 有权
标题翻译：具有电荷存储元件的非易失性存储单元和编程方法
公开(公告)号：US07544968B1
公开(公告)日：2009-06-09
申请号：US11210499
申请日：2005-08-24
申请人： Shahin Toutounchi , James Karp , Jongheon Jeong , Michael G. Ahrens , Michael J. Hart
发明人： Shahin Toutounchi , James Karp , Jongheon Jeong , Michael G. Ahrens , Michael J. Hart
IPC分类号： H01L29/04
CPC分类号： H01L29/42368 , H01L27/1021 , H01L27/112 , H01L27/11206
摘要： An MOS transistor is programmed in a non-volatile memory cell. A storage capacitor in the non-volatile memory cell is used to enhance programming efficiency by providing additional charge to the programming terminal of the MOS transistor during breakdown of the gate dielectric, thus avoiding soft programming faults. In a particular embodiment the storage capacitor is a second MOS transistor having a thicker gate dielectric layer than the dielectric layer of the programmable MOS transistor.
摘要翻译： MOS晶体管被编程在非易失性存储单元中。非易失性存储单元中的存储电容器用于通过在栅极电介质击穿期间向MOS晶体管的编程端提供额外的电荷来提高编程效率，从而避免软编程故障。在特定实施例中，存储电容器是具有比可编程MOS晶体管的介电层更厚的栅介质层的第二MOS晶体管。

2. 发明授权

US07420842B1 Method of programming a three-terminal non-volatile memory element using source-drain bias 有权
标题翻译：使用源极 - 漏极偏置来编程三端非易失性存储元件的方法
公开(公告)号：US07420842B1
公开(公告)日：2008-09-02
申请号：US11210595
申请日：2005-08-24
申请人： Michael G. Ahrens , Shahin Toutounchi , James Karp , Jongheon Jeong
发明人： Michael G. Ahrens , Shahin Toutounchi , James Karp , Jongheon Jeong
IPC分类号： G11C11/34
CPC分类号： G11C17/16 , G11C17/18
摘要： A storage transistor is programmed as a non-volatile memory element by biasing the source and drain while a programming voltage is applied to the gate. The substrate is held at a different potential than the source/drain to insure that the greatest difference in voltage during the programming step occurs between the channel region and the gate, rather than the gate and the source/drain. The programming voltage heats the channel region to form a non-volatile low-resistance connection between the source and drain, which is read to determine the programmed state.
摘要翻译：存储晶体管通过在将编程电压施加到栅极的情况下偏置源极和漏极而被编程为非易失性存储器元件。基板保持在与源极/漏极不同的电位，以确保在编程步骤期间在沟道区域和栅极之间而不是栅极和源极/漏极发生最大的电压差。编程电压加热通道区域，以在源极和漏极之间形成非易失性低电阻连接，读取该电阻以确定编程状态。

3. 发明授权

US07687797B1 Three-terminal non-volatile memory element with hybrid gate dielectric 有权
标题翻译：具有混合栅极电介质的三端非易失性存储元件
公开(公告)号：US07687797B1
公开(公告)日：2010-03-30
申请号：US11210500
申请日：2005-08-24
申请人： James Karp , Daniel Gitlin , Shahin Toutounchi , Michael G. Ahrens , Jongheon Jeong
发明人： James Karp , Daniel Gitlin , Shahin Toutounchi , Michael G. Ahrens , Jongheon Jeong
IPC分类号： H01L29/06 , H01L47/02
CPC分类号： G11C17/16 , G11C17/18 , H01L27/112 , H01L27/11206
摘要： A MOS transistor is used as a programmable three-terminal non-volatile memory element. The gate dielectric layer of the MOS transistor has a first portion with a relatively higher dielectric breakdown strength than a second portion. The location of the second portion is chosen so as to avoid having the gate dielectric layer break down near the edge of the active area or isolation area during programming. In a particular embodiment, the gate dielectric layer is silicon oxide, and the first portion is thicker than the second portion.
摘要翻译： MOS晶体管用作可编程三端非易失性存储元件。 MOS晶体管的栅介质层具有比第二部分具有相对更高的介电击穿强度的第一部分。选择第二部分的位置以避免在编程期间栅极电介质层在有源区域或隔离区域的边缘附近分解。在特定实施例中，栅介质层是氧化硅，第一部分比第二部分厚。

4. 发明授权

US07450431B1 PMOS three-terminal non-volatile memory element and method of programming 有权
标题翻译： PMOS三端非易失性存储元件及编程方法
公开(公告)号：US07450431B1
公开(公告)日：2008-11-11
申请号：US11210496
申请日：2005-08-24
申请人： James Karp , Jongheon Jeong , Michael G. Ahrens , Shahin Toutounchi
发明人： James Karp , Jongheon Jeong , Michael G. Ahrens , Shahin Toutounchi
IPC分类号： G11C16/04
CPC分类号： G11C17/16
摘要： A PMOS transistor is programmed as a non-volatile memory element by operating the PMOS transistor in accumulation mode. This facilitates merging the source and drain regions to form a low-resistance path because most heating occurs on the channel side of the gate dielectric, rather than on the gate terminal side. In a particular embodiment, boron is used as the dopant. Boron has a higher diffusivity than arsenic or phosphorous, which are typical n-type dopants. Boron's higher diffusivity promotes merging the source and drain regions.
摘要翻译：通过在累积模式下操作PMOS晶体管，将PMOS晶体管编程为非易失性存储元件。这有助于将源极和漏极区域合并以形成低电阻路径，因为大多数加热发生在栅极电介质的沟道侧，而不是栅极端子侧。在一个具体实施方案中，使用硼作为掺杂剂。硼具有比砷或磷更高的扩散性，它们是典型的n型掺杂剂。硼的较高扩散性促进了源区和漏区的融合。

5. 发明授权

US06549458B1 Non-volatile memory array using gate breakdown structures 有权
标题翻译：使用门击穿结构的非易失性存储器阵列
公开(公告)号：US06549458B1
公开(公告)日：2003-04-15
申请号：US10040044
申请日：2001-10-25
申请人： Kameswara K. Rao , Martin L. Voogel , James Karp , Shahin Toutounchi , Michael J. Hart , Daniel Gitlin , Kevin T. Look , Jongheon Jeong , Radko G. Bankras
发明人： Kameswara K. Rao , Martin L. Voogel , James Karp , Shahin Toutounchi , Michael J. Hart , Daniel Gitlin , Kevin T. Look , Jongheon Jeong , Radko G. Bankras
IPC分类号： G11C1400
CPC分类号： G11C16/08
摘要： Memory cell structures and related circuitry for use in non-volatile memory devices can be fabricated utilizing standard CMOS processes, for example, 0.18 micron or 0.15 micron processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials, for example, between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming.
摘要翻译：用于非易失性存储器件的存储器单元结构和相关电路可以使用标准CMOS工艺制造，例如0.18微米或0.15微米工艺。有利地，单元结构可以被编程，使得导电路径形成在类型材料之间，例如在p型栅极和p型源极/漏极区域之间或n型栅极和n型源极 /漏区。以这种方式编程单元有利地在编程之后提供具有低线性电阻的编程单元。

6. 发明授权

US06522582B1 Non-volatile memory array using gate breakdown structures 有权
标题翻译：使用门击穿结构的非易失性存储器阵列
公开(公告)号：US06522582B1
公开(公告)日：2003-02-18
申请号：US09553571
申请日：2000-04-19
申请人： Kameswara K. Rao , Martin L. Voogel , James Karp , Shahin Toutounchi , Michael J. Hart , Daniel Gitlin , Kevin T. Look , Jongheon Jeong , Radko G. Bankras
发明人： Kameswara K. Rao , Martin L. Voogel , James Karp , Shahin Toutounchi , Michael J. Hart , Daniel Gitlin , Kevin T. Look , Jongheon Jeong , Radko G. Bankras
IPC分类号： G11C1400
CPC分类号： G11C16/08
摘要： Memory cell structures and related circuitry for use in non-volatile memory devices are described. The cell structures can be fabricated utilizing standard CMOS processes, e.g. sub 0.35 micron or sub 0.25 micron processes. Preferably, the cell structures can be fabricated using 0.18 micron or 0.15 micron standard CMOS processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials. For example, in certain cell structures a cell is programmed by applying a programming voltage in such a way as to form a conductive path between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming. In addition, novel charge pump circuits are provided that, in a preferred embodiment, are located “on chip” with an array of memory cells. These charge pump circuits are preferably fabricated utilizing the same standard CMOS processing techniques that were utilized to form the memory cell structures and related circuitry.
摘要翻译：描述了用于非易失性存储器件的存储单元结构和相关电路。可以使用标准CMOS工艺制造电池结构，例如次0.35微米或次级0.25微米工艺。优选地，可以使用0.18微米或0.15微米标准CMOS工艺制造电池结构。有利地，电池结构可以被编程，使得在相似类型的材料之间形成导电路径。例如，在某些单元结构中，通过施加编程电压来编程单元，以便在p型栅极和p型源极/漏极区域或n型栅极和n型栅极之间形成导电路径型源极/漏极区域。以这种方式编程单元有利地在编程之后提供具有低线性电阻的编程单元。此外，提供了新颖的电荷泵电路，在优选实施例中，它们以“存储器”阵列位于芯片上。这些电荷泵电路优选地利用用于形成存储器单元结构和相关电路的相同的标准CMOS处理技术来制造。

7. 发明授权

US06740936B1 Ballast resistor with reduced area for ESD protection 有权
标题翻译：镇流电阻器具有减小的ESD保护面积
公开(公告)号：US06740936B1
公开(公告)日：2004-05-25
申请号：US10134086
申请日：2002-04-25
申请人： Daniel Gitlin , James Karp , Jongheon Jeong , Jan L. de Jong
发明人： Daniel Gitlin , James Karp , Jongheon Jeong , Jan L. de Jong
IPC分类号： H01L2978
CPC分类号： H01L29/8605
摘要： A transistor with ballast resistor formed between the transistor drain and the drain contact is formed by masking regions of the ballast resistor to increase resistivity and thus reduce required area. The invention achieves this without introducing any additional process or masking steps. Thus the invention allows a reduction in IC die size for the same ESD requirement or allows better ESD protection for a given die size.
摘要翻译：形成在晶体管漏极和漏极接触之间的具有镇流电阻的晶体管由镇流电阻器的掩蔽区域形成，以增加电阻率，从而减少所需面积。本发明实现了这一点，而不引入任何附加的处理或掩蔽步骤。因此，本发明允许针对相同ESD要求降低IC管芯尺寸，或者允许针对给定裸片尺寸的更好的ESD保护。

8. 发明授权

US08212576B1 Method and apparatus for self-regulated burn-in of an integrated circuit 有权
标题翻译：集成电路自调节老化的方法和装置
公开(公告)号：US08212576B1
公开(公告)日：2012-07-03
申请号：US12606101
申请日：2009-10-26
申请人： Jae Cho , Glenn O'Rourke , Michael M. Matera , Jongheon Jeong
发明人： Jae Cho , Glenn O'Rourke , Michael M. Matera , Jongheon Jeong
IPC分类号： G01R31/00
CPC分类号： G01R31/2856
摘要： Method and apparatus for self-regulated burn-in of an integrated circuit (IC) is described. One embodiment of a method of burn-in for the IC includes: configuring programmable resources of the IC device based on a burn-in pattern to implement a load controller, the load controller having a plurality of heat core circuits. The load controller is initialized with a number of enabled heat core circuits of the plurality of heat core circuits. A junction temperature is measured in the IC device after a measurement period has elapsed. The junction temperature is compared with a set-point temperature. The number of the enabled heat core circuits is increased if the junction temperature is less than the set-point temperature, or the number of the enabled heat core circuits is decreased if the junction temperature is greater than the set-point temperature.
摘要翻译：描述了用于集成电路（IC）的自调节老化的方法和装置。 IC的老化方法的一个实施例包括：基于老化模式配置IC器件的可编程资源以实现负载控制器，所述负载控制器具有多个热芯电路。负载控制器通过多个加热芯电路的多个使能的加热芯电路进行初始化。在测量周期过后，在IC器件中测量结温。结温与设定点温度进行比较。如果结温低于设定点温度，则可使加热芯电路的数量增加，或者如果结温高于设定点温度，则可使热芯电路的数量减少。

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