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1. 发明授权

US06549458B1 Non-volatile memory array using gate breakdown structures 有权
标题翻译：使用门击穿结构的非易失性存储器阵列
公开(公告)号：US06549458B1
公开(公告)日：2003-04-15
申请号：US10040044
申请日：2001-10-25
申请人： Kameswara K. Rao , Martin L. Voogel , James Karp , Shahin Toutounchi , Michael J. Hart , Daniel Gitlin , Kevin T. Look , Jongheon Jeong , Radko G. Bankras
发明人： Kameswara K. Rao , Martin L. Voogel , James Karp , Shahin Toutounchi , Michael J. Hart , Daniel Gitlin , Kevin T. Look , Jongheon Jeong , Radko G. Bankras
IPC分类号： G11C1400
CPC分类号： G11C16/08
摘要： Memory cell structures and related circuitry for use in non-volatile memory devices can be fabricated utilizing standard CMOS processes, for example, 0.18 micron or 0.15 micron processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials, for example, between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming.
摘要翻译：用于非易失性存储器件的存储器单元结构和相关电路可以使用标准CMOS工艺制造，例如0.18微米或0.15微米工艺。有利地，单元结构可以被编程，使得导电路径形成在类型材料之间，例如在p型栅极和p型源极/漏极区域之间或n型栅极和n型源极 /漏区。以这种方式编程单元有利地在编程之后提供具有低线性电阻的编程单元。

2. 发明授权

US06522582B1 Non-volatile memory array using gate breakdown structures 有权
标题翻译：使用门击穿结构的非易失性存储器阵列
公开(公告)号：US06522582B1
公开(公告)日：2003-02-18
申请号：US09553571
申请日：2000-04-19
申请人： Kameswara K. Rao , Martin L. Voogel , James Karp , Shahin Toutounchi , Michael J. Hart , Daniel Gitlin , Kevin T. Look , Jongheon Jeong , Radko G. Bankras
发明人： Kameswara K. Rao , Martin L. Voogel , James Karp , Shahin Toutounchi , Michael J. Hart , Daniel Gitlin , Kevin T. Look , Jongheon Jeong , Radko G. Bankras
IPC分类号： G11C1400
CPC分类号： G11C16/08
摘要： Memory cell structures and related circuitry for use in non-volatile memory devices are described. The cell structures can be fabricated utilizing standard CMOS processes, e.g. sub 0.35 micron or sub 0.25 micron processes. Preferably, the cell structures can be fabricated using 0.18 micron or 0.15 micron standard CMOS processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials. For example, in certain cell structures a cell is programmed by applying a programming voltage in such a way as to form a conductive path between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming. In addition, novel charge pump circuits are provided that, in a preferred embodiment, are located “on chip” with an array of memory cells. These charge pump circuits are preferably fabricated utilizing the same standard CMOS processing techniques that were utilized to form the memory cell structures and related circuitry.
摘要翻译：描述了用于非易失性存储器件的存储单元结构和相关电路。可以使用标准CMOS工艺制造电池结构，例如次0.35微米或次级0.25微米工艺。优选地，可以使用0.18微米或0.15微米标准CMOS工艺制造电池结构。有利地，电池结构可以被编程，使得在相似类型的材料之间形成导电路径。例如，在某些单元结构中，通过施加编程电压来编程单元，以便在p型栅极和p型源极/漏极区域或n型栅极和n型栅极之间形成导电路径型源极/漏极区域。以这种方式编程单元有利地在编程之后提供具有低线性电阻的编程单元。此外，提供了新颖的电荷泵电路，在优选实施例中，它们以“存储器”阵列位于芯片上。这些电荷泵电路优选地利用用于形成存储器单元结构和相关电路的相同的标准CMOS处理技术来制造。

3. 发明授权

US07687797B1 Three-terminal non-volatile memory element with hybrid gate dielectric 有权
标题翻译：具有混合栅极电介质的三端非易失性存储元件
公开(公告)号：US07687797B1
公开(公告)日：2010-03-30
申请号：US11210500
申请日：2005-08-24
申请人： James Karp , Daniel Gitlin , Shahin Toutounchi , Michael G. Ahrens , Jongheon Jeong
发明人： James Karp , Daniel Gitlin , Shahin Toutounchi , Michael G. Ahrens , Jongheon Jeong
IPC分类号： H01L29/06 , H01L47/02
CPC分类号： G11C17/16 , G11C17/18 , H01L27/112 , H01L27/11206
摘要： A MOS transistor is used as a programmable three-terminal non-volatile memory element. The gate dielectric layer of the MOS transistor has a first portion with a relatively higher dielectric breakdown strength than a second portion. The location of the second portion is chosen so as to avoid having the gate dielectric layer break down near the edge of the active area or isolation area during programming. In a particular embodiment, the gate dielectric layer is silicon oxide, and the first portion is thicker than the second portion.
摘要翻译： MOS晶体管用作可编程三端非易失性存储元件。 MOS晶体管的栅介质层具有比第二部分具有相对更高的介电击穿强度的第一部分。选择第二部分的位置以避免在编程期间栅极电介质层在有源区域或隔离区域的边缘附近分解。在特定实施例中，栅介质层是氧化硅，第一部分比第二部分厚。

4. 发明授权

US06268639B1 Electrostatic-discharge protection circuit 有权
标题翻译：静电放电保护电路
公开(公告)号：US06268639B1
公开(公告)日：2001-07-31
申请号：US09248547
申请日：1999-02-11
申请人： Sheau-Suey Li , Shahin Toutounchi , Michael J. Hart , Xin X. Wu , Daniel Gitlin
发明人： Sheau-Suey Li , Shahin Toutounchi , Michael J. Hart , Xin X. Wu , Daniel Gitlin
IPC分类号： H01L218222
CPC分类号： H01L27/0251 , Y10S438/983
摘要： An ESD protection circuit includes a bipolar transistor, a resistor, and a zener diode formed on and within a semiconductor substrate. The resistor extends between the base and emitter regions of the transistor so that voltage developed across the resistor can turn on the transistor. The zener diode is formed in series with the resistor and extends between the base and collector regions of the transistor. Thus configured, breakdown current through the zener diode, typically in response to an ESD event, turns on the transistor to provide a nondestructive discharge path for the ESD. The zener diode includes anode and cathode diffusions. The cathode diffusion extends down into the semiconductor substrate in a direction perpendicular to the substrate. The anode diffusion extends down through the cathode diffusion into the semiconductor substrate. The anode diffusion extends down further than the cathode diffusion so that the zener diode is arranged vertically with respect to the substrate. The cathode diffusion can be formed using two separate diffusions, one of which extends deeper into the substrate than other.
摘要翻译： ESD保护电路包括形成在半导体衬底上和半导体衬底内的双极晶体管，电阻器和齐纳二极管。电阻器在晶体管的基极和发射极区域之间延伸，使跨越电阻器的电压可以导通晶体管。齐纳二极管与电阻器串联形成，并在晶体管的基极和集电极区域之间延伸。如此配置，通常通过齐纳二极管的击穿电流（通常响应于ESD事件）导通晶体管，以为ESD提供非破坏性的放电路径。齐纳二极管包括阳极和阴极扩散。阴极扩散沿垂直于衬底的方向向下延伸到半导体衬底中。阳极扩散通过阴极扩散向下延伸到半导体衬底中。阳极扩散比阴极扩散向下延伸，使得齐纳二极管相对于衬底垂直布置。可以使用两个分开的扩散形成阴极扩散，其中一个扩散比其它扩散更深。

5. 发明授权

US06645802B1 Method of forming a zener diode 有权
标题翻译：形成齐纳二极管的方法
公开(公告)号：US06645802B1
公开(公告)日：2003-11-11
申请号：US09877690
申请日：2001-06-08
申请人： Sheau-Suey Li , Shahin Toutounchi , Michael J. Hart , Xin X. Wu , Daniel Gitlin
发明人： Sheau-Suey Li , Shahin Toutounchi , Michael J. Hart , Xin X. Wu , Daniel Gitlin
IPC分类号： H01L218234
CPC分类号： H01L27/0251 , Y10S438/983
摘要： An ESD protection circuit includes a bipolar transistor, a resistor, and a zener diode formed on and within a semiconductor substrate. The resistor extends between the base and emitter regions of the transistor so that voltage developed across the resistor can turn on the transistor. The zener diode is formed in series with the resistor and extends between the base and collector regions of the transistor. Thus configured, breakdown current through the zener diode, typically in response to an ESD event, turns on the transistor to provide a nondestructive discharge path for the ESD. The zener diode includes anode and cathode diffusions. The cathode diffusion extends down into the semiconductor substrate in a direction perpendicular to the substrate. The anode diffusion extends down through the cathode diffusion into the semiconductor substrate. The anode diffusion extends down further than the cathode diffusion so that the zener diode is arranged vertically with respect to the substrate. The cathode diffusion can be formed using two separate diffusions, one of which extends deeper into the substrate than other.
摘要翻译： ESD保护电路包括形成在半导体衬底上和半导体衬底内的双极晶体管，电阻器和齐纳二极管。电阻器在晶体管的基极和发射极区域之间延伸，使跨越电阻器的电压可以导通晶体管。齐纳二极管与电阻器串联形成，并在晶体管的基极和集电极区域之间延伸。如此配置，通常通过齐纳二极管的击穿电流（通常响应于ESD事件）导通晶体管，以为ESD提供非破坏性的放电路径。齐纳二极管包括阳极和阴极扩散。阴极扩散沿垂直于衬底的方向向下延伸到半导体衬底中。阳极扩散通过阴极扩散向下延伸到半导体衬底中。阳极扩散比阴极扩散向下延伸，使得齐纳二极管相对于衬底垂直布置。可以使用两个分开的扩散形成阴极扩散，其中一个扩散比其它扩散更深。

6. 发明授权

US06266269B1 Three terminal non-volatile memory element 有权
标题翻译：三端非易失性存储元件
公开(公告)号：US06266269B1
公开(公告)日：2001-07-24
申请号：US09589337
申请日：2000-06-07
申请人： James Karp , Daniel Gitlin , Shahin Toutounchi
发明人： James Karp , Daniel Gitlin , Shahin Toutounchi
IPC分类号： G11C1124
CPC分类号： G11C16/0466
摘要： A three terminal non-volatile memory element includes a standard (low voltage) CMOS transistor, i.e. a storage transistor, having a drain coupled to a read bit line and a source connected to ground. The storage transistor is programmed by applying a high programming voltage to its gate, thereby rupturing the gate oxide of the storage transistor. Of importance, in submicron technology, the source and drain regions of the storage transistor merge, thereby providing a highly reliable, conductive path. Thus, the state of the memory cell can be advantageously read solely via the read bit line.
摘要翻译：三端非易失性存储元件包括标准（低电压）CMOS晶体管，即存储晶体管，其具有耦合到读位线的漏极和连接到地的源极。存储晶体管通过向其栅极施加高编程电压来编程，从而破坏存储晶体管的栅极氧化物。重要的是，在亚微米技术中，存储晶体管的源极和漏极区域合并，从而提供高度可靠的导电路径。因此，存储单元的状态可以有利地仅通过读位线读取。

7. 发明授权

US06740936B1 Ballast resistor with reduced area for ESD protection 有权
标题翻译：镇流电阻器具有减小的ESD保护面积
公开(公告)号：US06740936B1
公开(公告)日：2004-05-25
申请号：US10134086
申请日：2002-04-25
申请人： Daniel Gitlin , James Karp , Jongheon Jeong , Jan L. de Jong
发明人： Daniel Gitlin , James Karp , Jongheon Jeong , Jan L. de Jong
IPC分类号： H01L2978
CPC分类号： H01L29/8605
摘要： A transistor with ballast resistor formed between the transistor drain and the drain contact is formed by masking regions of the ballast resistor to increase resistivity and thus reduce required area. The invention achieves this without introducing any additional process or masking steps. Thus the invention allows a reduction in IC die size for the same ESD requirement or allows better ESD protection for a given die size.
摘要翻译：形成在晶体管漏极和漏极接触之间的具有镇流电阻的晶体管由镇流电阻器的掩蔽区域形成，以增加电阻率，从而减少所需面积。本发明实现了这一点，而不引入任何附加的处理或掩蔽步骤。因此，本发明允许针对相同ESD要求降低IC管芯尺寸，或者允许针对给定裸片尺寸的更好的ESD保护。

8. 发明授权

US5880620A Pass gate circuit with body bias control 失效
标题翻译：通过门电路与体偏置控制
公开(公告)号：US5880620A
公开(公告)日：1999-03-09
申请号：US840582
申请日：1997-04-22
申请人： Daniel Gitlin , Sheau-Suey Li , Martin L. Voogel , Tiemin Zhao
发明人： Daniel Gitlin , Sheau-Suey Li , Martin L. Voogel , Tiemin Zhao
IPC分类号： G11C5/14 , H03K17/06 , H03K3/01
CPC分类号： G11C5/146 , H03K17/063 , H03K2217/0018
摘要： A pass gate circuit includes a pass transistor and a body bias control circuit for biasing the body of the pass transistor to reduce body effect. The body bias control circuit includes one or more control transistors arranged to selectively connect the substrate (body) of the pass transistor to the drain or gate of the pass transistor when predetermined voltages are applied to the drain and gate of the pass transistor. As a result, the pass transistor exhibits a reduced body effect in the on-state. In one embodiment, the body bias control circuit includes a first control transistor having a drain and gate connected to the gate of the pass transistor, a gate connected to the drain of the pass transistor, and a source. The body bias control circuit also includes a second control transistor having a drain connected to the source of the first control transistor, a source connected to a body of the pass transistor, and a gate connected to the drain of the pass transistor. The bodies of the pass transistor, first control transistor and second control transistor are electrically interconnected. With this arrangement, the body of the pass transistor is biased "high" by the gate of the pass transistor only when both the gate and drain of the pass transistor are at a high voltage level.
摘要翻译：通路电路包括通过晶体管和体偏置控制电路，用于偏置通过晶体管的主体以减小体效应。体偏置控制电路包括一个或多个控制晶体管，其布置成当预定电压施加到传输晶体管的漏极和栅极时，选择性地将传输晶体管的衬底（主体）连接到传输晶体管的漏极或栅极。结果，通过晶体管在导通状态下表现出减小的体效应。在一个实施例中，体偏置控制电路包括第一控制晶体管，其具有连接到传输晶体管的栅极的漏极和栅极，连接到传输晶体管的漏极的栅极和源极。体偏置控制电路还包括第二控制晶体管，其具有连接到第一控制晶体管的源极的漏极，连接到传输晶体管的主体的源极和连接到通过晶体管的漏极的栅极。传输晶体管，第一控制晶体管和第二控制晶体管的主体电互连。通过这种布置，只有当传输晶体管的栅极和漏极都处于高电压电平时，传输晶体管的主体被传输晶体管的栅极偏置“高”。

9. 发明授权

US06621325B2 Structures and methods for selectively applying a well bias to portions of a programmable device 有权
标题翻译：用于选择性地将井偏压施加到可编程设备的部分的结构和方法
公开(公告)号：US06621325B2
公开(公告)日：2003-09-16
申请号：US09956203
申请日：2001-09-18
申请人： Michael J. Hart , Steven P. Young , Daniel Gitlin , Hua Shen , Stephen M. Trimberger
发明人： Michael J. Hart , Steven P. Young , Daniel Gitlin , Hua Shen , Stephen M. Trimberger
IPC分类号： H03K301
CPC分类号： H03K19/17792 , G06F17/5054 , H01L27/0928 , H01L27/11807
摘要： Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integrated circuit includes a plurality of wells, each of which can be independently and programmably biased with the same or a different well bias voltage. In one embodiment, FPGA implementation software automatically determines the critical paths and generates a configuration bitstream that enables positive well biasing only for the transistors participating in the critical paths, or only for programmable logic elements (e.g., CLBs or lookup tables) containing those transistors. In another embodiment, negative well biasing is selectively applied to reduce leakage current.
摘要翻译：用于选择性地将阱偏压施加到PLD的那些需要或期望的偏置的那些部分的结构和方法，例如在用户设计中的关键路径上的晶体管施加正的阱偏置。用于集成电路的衬底包括多个阱，每个阱可以以相同或不同的阱偏置电压独立地且可编程地偏置。在一个实施例中，FPGA实现软件自动地确定关键路径并且生成配置比特流，其使得能够仅对参与关键路径的晶体管施加正阱偏置，或仅对包含那些晶体管的可编程逻辑元件（例如，CLB或查找表）进行偏置。在另一个实施例中，选择性地施加负阱偏置以减少泄漏电流。

10. 发明授权

US5870327A Mixed mode RAM/ROM cell using antifuses 失效
标题翻译：使用反熔丝的混合模式RAM / ROM单元
公开(公告)号：US5870327A
公开(公告)日：1999-02-09
申请号：US963532
申请日：1997-11-03
申请人： Daniel Gitlin , Dennis L. Segers , Michael J. Hart
发明人： Daniel Gitlin , Dennis L. Segers , Michael J. Hart
IPC分类号： G11C7/20 , G11C17/00
CPC分类号： G11C7/20
摘要： A mixed mode RAM/ROM cell includes a volatile memory cell and an antifuse coupled to the cell. In an array of mixed mode memory cells, addressing circuitry is coupled to the volatile memory cells and programming circuitry is coupled to the antifuses. After an antifuse is programmed, the associated memory cell is transformed from a volatile memory to a non-volatile memory. Specifically, during normal operation, a standard supply voltage is provided to all antifuses. Thus, after a power down or power fluctuation, the programmed antifuses ensure subsequent configuration of their respective volatile memory cells.
摘要翻译：混合模式RAM / ROM单元包括易失性存储单元和耦合到单元的反熔丝。在混合模式存储器单元的阵列中，寻址电路耦合到易失性存储器单元，并且编程电路耦合到反熔丝。在反熔丝被编程之后，相关联的存储器单元从易失性存储器转换成非易失性存储器。具体地说，在正常操作期间，向所有反熔丝提供标准电源电压。因此，在断电或功率波动之后，编程的反熔丝确保其各自的易失性存储单元的后续配置。

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