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1. 发明授权

US5872313A Temperature-compensated surface micromachined angular rate sensor 失效
标题翻译：温度补偿表面微加工角速度传感器
公开(公告)号：US5872313A
公开(公告)日：1999-02-16
申请号：US833438
申请日：1997-04-07
申请人： Seyed Ramezan Zarabadi , Jack Daniel Johnson , Michael William Putty
发明人： Seyed Ramezan Zarabadi , Jack Daniel Johnson , Michael William Putty
IPC分类号： G01C19/5684 , G01P3/00
CPC分类号： G01C19/5684
摘要： A motion sensor having a micromachine sensing element and electrodes formed on a silicon chip. The sensing element includes a ring supported above a substrate so as to have an axis of rotation normal to the substrate. Surrounding the ring is at least one pair of diametrically-opposed electrode structures. The sensing ring and electrode structures are configured to include interdigitized members whose relative placement to each other enables at least partial cancellation of the effect of differential thermal expansion of the ring and electrodes. As a result, the performance of the motion sensor is, to first order, insensitive to temperature variation. The sensor further includes circuitry for creating and detecting an electrostatic force between the interdigitized members of the sensing ring and electrode structures. The circuitry operates to sum the electrostatic forces such that, on the occurrence of a temperature change, a corresponding decrease in the electrostatic force between one pair of interdigitized members will at least partially cancel a corresponding increase in electrostatic force between a second pair of interdigitized members. Accordingly, the net effect is that a temperature change will have a reduced effect on the sensing performance of the sensor, because the effects of thermal expansion will be at least partially canceled.
摘要翻译：一种运动传感器，其具有微机械感测元件和形成在硅芯片上的电极。感测元件包括支撑在基板上方的环，以便具有垂直于基板的旋转轴。环绕环是至少一对直径相对的电极结构。感测环和电极结构被配置为包括互相指向的构件，其相对放置彼此能够至少部分地消除环和电极的差动热膨胀的影响。结果，运动传感器的性能一度对温度变化不敏感。传感器还包括用于产生和检测感测环和电极结构的叉指构件之间的静电力的电路。电路用于对静电力求和，使得在温度变化的发生时，一对叉指构件之间的静电力的相应减小将至少部分地抵消第二对叉指构件之间的静电力的相应增加。因此，净效果是温度变化对传感器的感测性能的影响将会降低，因为热膨胀的影响将至少部分被消除。

2. 发明授权

US5910745A Process parameters and temperature insensitive analog divider/multiplier/ratiometry circuit 失效
标题翻译：过程参数和温度不敏感的模拟分频器/乘法器/比率电路
公开(公告)号：US5910745A
公开(公告)日：1999-06-08
申请号：US846455
申请日：1997-05-01
申请人： Seyed Ramezan Zarabadi
发明人： Seyed Ramezan Zarabadi
IPC分类号： G06G7/164 , H03K17/92
CPC分类号： G06G7/164
摘要： A CMOS analog divider/multiplier/ratiometry circuit that provides a ratiometric output of two or more inputs, where the output is insensitive to process parameters and temperature variations effecting the circuit. The analog divider/multiplier/ratiometry circuit includes a multiplier portion made up of six FET devices. The six FET devices are electrically connected together so that first and second current outputs from the multiplier portion are insensitive to process parameter and temperature variations effecting the circuit. A first input current is applied to a gate terminal of one of the FET devices and a second input current is applied to a gate terminal of the FET devices in the multiplier portion of the circuit. The first and second input currents are based on currents generated by first and second linear voltage-to-current converter input circuits that are responsive to first and second input voltage, respectively, whose ratio or product is to be determined at the output of the circuit. The output currents from the multiplier portion are applied to a difference amplifier that generates the ratio/product output.
摘要翻译： CMOS模拟分频器/倍增器/比例计电路，提供两个或多个输入的比例输出，其中输出对影响电路的过程参数和温度变化不敏感。模拟分频器/倍增器/比例计电路包括由六个FET器件组成的乘法器部分。六个FET器件电连接在一起，使得来自乘法器部分的第一和第二电流输出对影响电路的工艺参数和温度变化不敏感。第一输入电流被施加到FET器件中的一个的栅极端子，并且第二输入电流被施加到电路的乘法器部分中的FET器件的栅极端子。第一和第二输入电流基于分别响应于第一和第二输入电压的第一和第二线性电压 - 电流转换器输入电路产生的电流，其比例或乘积将在电路的输出端确定。来自乘法器部分的输出电流被施加到产生比率/乘积输出的差分放大器。

3. 发明授权

US06198350B1 Signal amplifier with fast recovery time response, efficient output driver and DC offset cancellation capability 有权
标题翻译：具有快速恢复时间响应的信号放大器，高效的输出驱动器和DC偏移消除功能
公开(公告)号：US06198350B1
公开(公告)日：2001-03-06
申请号：US09290835
申请日：1999-04-13
申请人： Seyed Ramezan Zarabadi
发明人： Seyed Ramezan Zarabadi
IPC分类号： H03F326
CPC分类号： H03F3/45179 , H03F3/45717 , H03F2203/45068 , H03F2203/45074 , H03F2203/45076 , H03F2203/45078 , H03F2203/45081 , H03F2203/45188 , H03F2203/45212 , H03F2203/45508
摘要： A signal amplifying circuit (24) includes level shifting input circuits (D1-D4) permitting input common-mode voltages (VIN1 and VIN2) of an amplifier and fault detection circuit (50) to vary between preset limits. The sense amplifier circuit (24) includes a DC offset buffer circuit (52) operable to receive an analog DC offset compensation signal and provide this signal to an input of the amplifier and fault detection circuit (50). The buffered DC offset compensation signal provided to the amplifier and fault detection circuit (50) is operable to reduce an aggregate DC offset voltage attributable to signal amplifying circuit (24) to a desired DC offset level. The amplifier and fault detection circuit (50) also includes a fault detection function whereby an output (VSENSE) of the amplifier circuit (50) is forced to a predetermined output state if either, or both, of the inputs (VIN1 and VIN2) of the sense amplifier circuit (24) are unconnected; i.e., floating. The output (VSENSE) of the amplifier and fault detection circuit (50) is provided to an output buffer circuit (54) operable to modulate the load current supplied to an output (VOUT1, VOUT2) thereof as a function of a difference between the amplifier output signal (VSENSE) and the output buffer output signal (VOUT1).
摘要翻译：信号放大电路（24）包括允许放大器和故障检测电路（50）的输入共模电压（VIN1和VIN2）在预设极限之间变化的电平移位输入电路（D1-D4）。读出放大器电路（24）包括DC偏移缓冲电路（52），可操作以接收模拟DC偏移补偿信号，并将该信号提供给放大器和故障检测电路（50）的输入端。提供给放大器和故障检测电路（50）的缓冲DC偏移补偿信号可操作以将归因于信号放大电路（24）的总的DC偏移电压减小到期望的DC偏移电平。放大器和故障检测电路（50）还包括故障检测功能，由此如果放大器电路（50）的输入（VIN1和VIN2）的输入（VIN1和VIN2）之一或两者被强制为预定的输出状态读出放大器电路（24）不连接; 即浮动。放大器和故障检测电路（50）的输出（VSENSE）被提供给输出缓冲器电路（54），该输出缓冲器电路（54）可用于调制提供给其输出（VOUT1，VOUT2）的负载电流作为放大器输出信号（VSENSE）和输出缓冲器输出信号（VOUT1）。

4. 发明授权

US06305222B1 Road vibration compensated angular rate sensor 有权
标题翻译：道路振动补偿角速率传感器
公开(公告)号：US06305222B1
公开(公告)日：2001-10-23
申请号：US09321449
申请日：1999-05-27
申请人： Jack Daniel Johnson , Seyed Ramezan Zarabadi
发明人： Jack Daniel Johnson , Seyed Ramezan Zarabadi
IPC分类号： G01P300
CPC分类号： G01C19/5684
摘要： A motion sensor (10) includes a micromachined sensing structure and a number of capacitive electrodes (20) disposed about a periphery thereof. The sensing structure includes a ring (14) supported above a substrate (12) so as to have an axis of rotation normal to the substrate (12), and a number of springs (16) attached to a post (18) positioned at the center of the ring (14). Certain diametrically opposed ones of the capacitive electrodes (20) are configured as drive electrodes (20a), and other diametrically opposed ones of the capacitive electrodes (20), positioned 90 degrees relative to the corresponding drive electrodes (20a) are configured as sense electrodes (20b). Signals produced at the opposed sense electrodes (20b) are conditioned and coupled to a common input of an amplifier circuit (64,70). With the configuration of the drive (20a) and sense (20b) electrodes and supporting circuitry (60-70), the resulting sensor (10) is operable to reject the effects of linear forces thereupon due to road vibrational effects.
摘要翻译：运动传感器（10）包括微机械感测结构和围绕其周边设置的多个电容电极（20）。感测结构包括支撑在基板（12）上方以具有垂直于基板（12）的旋转轴线的环（14），以及附接到位于该基板（12）上的柱（18）的多个弹簧环的中心（14）。电容电极（20）中的某些直径相对的电极被构造为驱动电极（20a），并且相对于相应的驱动电极（20a）定位成90度的其它直径相对的电容电极（20）被配置为感测电极（20b）。在相对的感测电极（20b）处产生的信号被调节并耦合到放大器电路（64,70）的公共输入端。通过驱动器（20a）和感测（20b）电极和支撑电路（60-70）的配置，所得到的传感器（10）可操作以抵消由于道路振动效应而产生的线性力的影响。

5. 发明授权

US06194941B1 DC offset compensation circuit for a signal amplifier 有权
标题翻译：用于信号放大器的直流偏移补偿电路
公开(公告)号：US06194941B1
公开(公告)日：2001-02-27
申请号：US09290929
申请日：1999-04-13
申请人： Seyed Ramezan Zarabadi , Mark Russell Keyse , Pedro Enrique Castillo-Borelly , William Joseph Hulka
发明人： Seyed Ramezan Zarabadi , Mark Russell Keyse , Pedro Enrique Castillo-Borelly , William Joseph Hulka
IPC分类号： H03L500
CPC分类号： H03F3/45605 , H03F3/45475
摘要： A DC offset compensation circuit (34) for compensating for a DC offset voltage of a signal amplifier (24) includes a first sample and hold circuit (40) having an input receiving an amplifier output signal (VOUT2) and an output supplying the sampled and held output signal (VOUT2) to a non-inverting input of a comparator 42. A first digital-to-analog (D/A) circuit (46) is responsive to a number of digital input signals to produce an analog DC target signal at an output (VD) thereof. The analog DC target signal is provided to an input of a second sample and hold circuit (50) having an output supplying the sampled and held analog DC target signal to an inverting input of the comparator 42. The output of the comparator 42 is provided to an offset cancellation control circuit (56) including a state machine (66) and a counter circuit (68) operable to modify a count value (OFFDAC) thereof depending upon statuses of a number of input control signals (CLK1, CLK2, STRT, STP) and the comparator output signal (CO). A second D/A circuit has a number of digital inputs receiving the count value (OFFDAC) and producing at an output (VDCO) thereof an analog DC compensation signal corresponding thereto. The analog DC compensation signal is provided to a input (VDCO) of the signal amplifier (24) to thereby force the DC component of the amplifier output signal (VOUT2) near the analog DC target signal, thereby minimizing an aggregate DC offset voltage attributable to the signal amplifier (24).
摘要翻译：用于补偿信号放大器（24）的DC偏移电压的DC偏移补偿电路（34）包括具有接收放大器输出信号（VOUT2）的输入的第一采样保持电路（40）和提供采样和保持输出信号（VOUT2）到比较器42的非反相输入端。第一数模（D / A）电路（46）响应多个数字输入信号以产生模拟DC目标信号其输出（VD）。模拟DC目标信号被提供给具有将采样和保持的模拟DC目标信号提供给比较器42的反相输入的输出的第二采样和保持电路（50）的输入。比较器42的输出被提供给偏移消除控制电路（56），包括状态机（66）和计数器电路（68），可根据输入控制信号（CLK1，CLK2，STRT，STP）的状态修改其计数值（OFFDAC））和比较器输出信号（CO）。第二D / A电路具有接收计数值（OFFDAC）的多个数字输入，并在其输出（VDCO）处产生与其对应的模拟DC补偿信号。模拟DC补偿信号被提供给信号放大器（24）的输入端（VDCO），从而将放大器输出信号（VOUT2）的DC分量逼近模拟DC目标信号附近，从而最小化归因于信号放大器（24）。

6. 发明授权

US5856941A One-time programmable latch which allows volatile writes prior to permanent programming 失效
标题翻译：一次性可编程锁存器，允许永久编程之前的易失性写入
公开(公告)号：US5856941A
公开(公告)日：1999-01-05
申请号：US929457
申请日：1997-09-15
申请人： Mark Russell Keyse , Gregory Jon Manlove , Pedro E. Castillo-Borelly , Seyed Ramezan Zarabadi
发明人： Mark Russell Keyse , Gregory Jon Manlove , Pedro E. Castillo-Borelly , Seyed Ramezan Zarabadi
IPC分类号： G11C16/04 , G11C11/00
CPC分类号： G11C16/0441
摘要： A cross-coupled latch circuit that is a one-time programmable latch that allows volatile temporary writes to the latch prior to permanent programming of the latch. The latch circuit includes first and second programmable FET devices that include poly-poly capacitators in series with the gate terminal of each device. A pair of PMOS FET devices combine with the programmable devices to make up the latch. The latch circuit includes other FET devices that are switched on and off depending on whether the latch is being permanently programmed, temporarily written to, or reset. A NAND gate is provided such that a logical high output on the NAND gate allows the first programmable device to be temporarily programmed with a logical one and permanently programmed with a logical zero. A NOR gate is provided such that a logical high on the NOR gate allows the second programmable device to be temporarily programmed with a logical zero and permanently programmed with a logical one.
摘要翻译：交叉耦合锁存电路，其是在锁存器的永久编程之前允许对锁存器的易失性临时写入的一次性可编程锁存器。锁存电路包括第一和第二可编程FET器件，其包括与每个器件的栅极端子串联的多晶硅电容器。一对PMOS FET器件与可编程器件组合构成锁存器。锁存电路包括根据锁存器是被永久编程，临时写入还是复位而导通和关断的其他FET器件。提供NAND门，使得NAND门上的逻辑高输出允许第一可编程器件以逻辑1临时编程并且用逻辑零永久编程。 NOR门被提供，使得NOR门上的逻辑高电平允许第二可编程器件被临时编程为逻辑0并且用逻辑0永久编程。

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