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1. 发明申请

US20110316092A1 Mask Rom 有权
标题翻译：面具Rom
公开(公告)号：US20110316092A1
公开(公告)日：2011-12-29
申请号：US13050241
申请日：2011-03-17
申请人： Seung-Jin Yang , Yong-Tae Kim , Hyuck-Soo Yang , Jung-Ho Moon
发明人： Seung-Jin Yang , Yong-Tae Kim , Hyuck-Soo Yang , Jung-Ho Moon
IPC分类号： H01L27/112
CPC分类号： H01L27/0203 , H01L27/112 , H01L27/11253
摘要： A mask read-only memory (ROM) includes parallel doping lines of a second conductivity type formed in a substrate of a first conductivity type, a first insulation film formed on the doping lines and the substrate, conductive pads fainted on the first insulation film, a second insulation film formed on the first insulation film and the conductive pads, parallel wires formed on the second insulation film extending perpendicular to the doping lines, contact plugs formed in the first insulation film that connect the doping lines to the conductive pads, and vias formed in the second insulation film that connect the conductive pads to the wires, wherein crossings of the doping lines and the wires define memory cells, contact plugs and vias are formed in memory cells of a first type, and at least one of the contact plug and via are missing from memory cells of a second type.
摘要翻译：掩模只读存储器（ROM）包括形成在第一导电类型的衬底中的第二导电类型的并行掺杂线，形成在掺杂线和衬底上的第一绝缘膜，位于第一绝缘膜上的导电焊盘，形成在所述第一绝缘膜和所述导电焊盘上的第二绝缘膜，形成在垂直于所述掺杂线延伸的所述第二绝缘膜上的平行布线，形成在将所述掺杂线连接到所述导电焊盘的所述第一绝缘膜中的接触插塞，以及通孔形成在所述第二绝缘膜中，所述第二绝缘膜将所述导电焊盘连接到所述导线，其中所述掺杂线和所述布线的交叉限定存储器单元，接触插塞和通孔形成在第一类型的存储器单元中，并且所述接触插塞并且第二类型的存储器单元中缺少通孔。

2. 发明授权

US08507997B2 Mask read-only memory having a fake select transistor 有权
标题翻译：具有假选择晶体管的掩模只读存储器
公开(公告)号：US08507997B2
公开(公告)日：2013-08-13
申请号：US13050241
申请日：2011-03-17
申请人： Seung-Jin Yang , Yong-Tae Kim , Hyuck-Soo Yang , Jung-Ho Moon
发明人： Seung-Jin Yang , Yong-Tae Kim , Hyuck-Soo Yang , Jung-Ho Moon
IPC分类号： H01L21/70
CPC分类号： H01L27/0203 , H01L27/112 , H01L27/11253
摘要： A mask read-only memory (ROM) includes parallel doping lines of a second conductivity type formed in a substrate of a first conductivity type, a first insulation film formed on the doping lines and the substrate, conductive pads fainted on the first insulation film, a second insulation film formed on the first insulation film and the conductive pads, parallel wires formed on the second insulation film extending perpendicular to the doping lines, contact plugs formed in the first insulation film that connect the doping lines to the conductive pads, and vias formed in the second insulation film that connect the conductive pads to the wires, wherein crossings of the doping lines and the wires define memory cells, contact plugs and vias are formed in memory cells of a first type, and at least one of the contact plug and via are missing from memory cells of a second type.
摘要翻译：掩模只读存储器（ROM）包括形成在第一导电类型的衬底中的第二导电类型的并行掺杂线，形成在掺杂线和衬底上的第一绝缘膜，位于第一绝缘膜上的导电焊盘，形成在所述第一绝缘膜和所述导电焊盘上的第二绝缘膜，形成在垂直于所述掺杂线延伸的所述第二绝缘膜上的平行布线，形成在将所述掺杂线连接到所述导电焊盘的所述第一绝缘膜中的接触插塞，以及通孔形成在所述第二绝缘膜中，所述第二绝缘膜将所述导电焊盘连接到所述导线，其中所述掺杂线和所述布线的交叉限定存储器单元，接触插塞和通孔形成在第一类型的存储器单元中，并且所述接触插塞并且第二类型的存储器单元中缺少通孔。

3. 发明授权

US08203981B2 Wireless sensor network with linear structure being capable of bidirectional communication and method thereof 有权
标题翻译：具有线性结构的无线传感器网络能够进行双向通信及其方法
公开(公告)号：US08203981B2
公开(公告)日：2012-06-19
申请号：US12449103
申请日：2008-01-09
申请人： Tae-Yun Chung , Han-Su Chung , Jung-Ho Moon
发明人： Tae-Yun Chung , Han-Su Chung , Jung-Ho Moon
IPC分类号： H04L5/14
CPC分类号： H04W72/1257 , H04W56/0015 , H04W84/18
摘要： Disclosed is a wireless sensor network with a linear structure capable of bidirectional communication. The wireless sensor network includes a plurality of nodes linearly connected from a sink node to a terminal node by connecting each node to a single upper-level node and a single lower-level node, each node has an active period for transmitting/receiving data to/from its upper-level node and lower-level node, the active period includes a downstream duration for transmitting data/commands from the sink node to the terminal node and an upstream duration for transmitting data/commands from the terminal node to the sink node, and each of the upstream and downstream durations sequentially includes RX, TX, and ACK intervals, so that bidirectional communication between the sink node and the terminal node can be performed within a single active period.
摘要翻译：公开了具有能够双向通信的线性结构的无线传感器网络。无线传感器网络包括通过将每个节点连接到单个上层节点和单个下级节点而从宿节点线路连接到终端节点的多个节点，每个节点具有用于发送/接收数据的活动周期 /从其上级节点和下级节点，活动时段包括用于从汇聚节点向终端节点发送数据/命令的下游持续时间，以及从终端节点向汇聚节点发送数据/命令的上行持续时间，并且上游和下游持续时间中的每一个顺序地包括RX，TX和ACK间隔，使得宿节点和终端节点之间的双向通信可以在单个活动时段内执行。

4. 发明授权

US06974748B2 Semiconductor device with split gate electrode structure and method for manufacturing the semiconductor device 失效
公开(公告)号：US06974748B2
公开(公告)日：2005-12-13
申请号：US10920158
申请日：2004-08-18
申请人： Jung-Ho Moon , Jae-Min Yu , Don-Woo Lee , Chul-Soon Kwon , In-Gu Yoon , Yong-Sun Lee , Jae-Hyun Park
发明人： Jung-Ho Moon , Jae-Min Yu , Don-Woo Lee , Chul-Soon Kwon , In-Gu Yoon , Yong-Sun Lee , Jae-Hyun Park
IPC分类号： H01L27/10 , H01L21/336 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11539
摘要： A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.

5. 发明授权

US08053342B2 Mask ROM device, semiconductor device including the mask ROM device, and methods of fabricating mask ROM device and semiconductor device 失效
标题翻译：掩模ROM器件，包括掩模ROM器件的半导体器件，以及制造掩模ROM器件和半导体器件的方法
公开(公告)号：US08053342B2
公开(公告)日：2011-11-08
申请号：US12836066
申请日：2010-07-14
申请人： Yong-Kyu Lee , Jeong-Uk Han , Hee-Seog Jeon , Young-Ho Kim , Myung-Jo Chun , Jung-Ho Moon
发明人： Yong-Kyu Lee , Jeong-Uk Han , Hee-Seog Jeon , Young-Ho Kim , Myung-Jo Chun , Jung-Ho Moon
IPC分类号： H01L21/8238
CPC分类号： H01L27/105 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L27/1052 , H01L27/11266 , H01L27/11293
摘要： A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structure on the substrate and an off-cell junction structure within the substrate. The on-cell gate structure includes an on-cell gate insulating film, an on-cell gate electrode and an on-cell gate spacer. The on-cell junction structure includes first and second on-cell ion implantation regions of a first polarity and third and fourth on-cell ion implantation regions of a second polarity. The off-cell gate structure includes an off-cell gate insulating film, an off-cell gate electrode and an off-cell gate spacer. The off-cell junction structure includes first and second off-cell ion implantation regions of the first polarity and a third off-cell ion implantation region of the second polarity.
摘要翻译：可以稳定地输出数据的掩模只读存储器（ROM）装置包括接通电池和截止电池。开放单元包括衬底上的孔上栅极结构和衬底内的电池单元结结构。离子电池包括在衬底上的离子电池栅极结构和衬底内的细胞外结合结构。单体栅极结构包括单元间栅极绝缘膜，单晶体栅极电极和单元间栅极间隔物。该单电池结结构包括具有第一极性的第一和第二开孔离子注入区和第二极性的第三和第四接通电离子注入区。离群栅极结构包括离子栅极绝缘膜，离子阱栅极电极和非电池栅极间隔物。离电池结结构包括具有第一极性的第一和第二离子外离子注入区域和第二极性的第三离子间离子注入区域。

6. 发明申请

US20110069611A1 WIRELESS SENSOR NETWORK 审中-公开
标题翻译：无线传感器网络
公开(公告)号：US20110069611A1
公开(公告)日：2011-03-24
申请号：US12992016
申请日：2009-05-08
申请人： Tae-Yun Chung , Yong-Soon Park , Jung-Ho Moon
发明人： Tae-Yun Chung , Yong-Soon Park , Jung-Ho Moon
IPC分类号： H04L12/28 , H04B7/14
CPC分类号： H04W40/32 , H04L67/12 , H04W40/22 , H04W84/18
摘要： Provided is a wireless sensor network including: a plurality of sensor nodes connected linearly; a sink node connected to the uppermost node among the sensor nodes; a control server; a gateway connected between the sink node and the control server to transmit and receive data; and a plurality of relay gateways. In the case where the plurality of the sensor nodes are divided into a predetermined number of subgroups, the sensor nodes located at the highest levels in the divided subgroups and which are connected to the relay gateways are designated as relay nodes. In the case where an amount of data stored in the relay node exceeds a predetermined threshold value, the relay node transmits the stored data through the connected relay gateway to the control server. Accordingly, in the case where the data of the sensor nodes are increased, it is possible to minimize a problem in that the increased data are lost during transmission.
摘要翻译：提供了一种无线传感器网络，包括：线性连接的多个传感器节点; 连接到传感器节点中最上层节点的汇聚节点; 控制服务器连接在汇点节点和控制服务器之间以传送和接收数据的网关; 和多个中继网关。在将多个传感器节点划分为预定数量的子组的情况下，分配的子组中位于最高级并且连接到中继网关的传感器节点被指定为中继节点。在存储在中继节点中的数据量超过预定阈值的情况下，中继节点通过所连接的中继网关将存储的数据发送到控制服务器。因此，在传感器节点的数据增加的情况下，可以最小化在传输期间增加的数据丢失的问题。

7. 发明申请

US20070252190A1 Nonvolatile memory device and method for manufacturing the same 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20070252190A1
公开(公告)日：2007-11-01
申请号：US11653962
申请日：2007-01-17
申请人： Jae-Hyun Park , Chul-Soon Kwon , Jae-Min Yu , Ji-Woon Rim , Young-Cheon Jeong , In-Gu Yoon , Jung-Ho Moon
发明人： Jae-Hyun Park , Chul-Soon Kwon , Jae-Min Yu , Ji-Woon Rim , Young-Cheon Jeong , In-Gu Yoon , Jung-Ho Moon
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521 , H01L29/7885
摘要： Provided are a nonvolatile memory device and a method for manufacturing the same. The nonvolatile memory device may include a semiconductor substrate, a floating gate, a second insulation layer, a third insulation layer, a control gate, and a common source line. The semiconductor substrate may have an active region limited by a device isolation region. The floating gate may be formed on the active region with a first insulation layer between the floating gate and the active region. The second insulation layer covers one side of the floating gate, and the third insulation layer covers the floating gate and the second insulation layer. The control gate may be formed on the other side of the floating gate with a fourth insulation layer between the control gate and the floating gate. The common source line may be formed in a portion of the substrate that is located under the second insulation layer.
摘要翻译：提供一种非易失性存储器件及其制造方法。非易失性存储器件可以包括半导体衬底，浮置栅极，第二绝缘层，第三绝缘层，控制栅极和公共源极线。半导体衬底可以具有被器件隔离区限制的有源区。浮置栅极可以在有源区上形成在浮置栅极和有源区域之间的第一绝缘层。第二绝缘层覆盖浮栅的一侧，第三绝缘层覆盖浮栅和第二绝缘层。控制栅极可以在浮动栅极的另一侧上形成在控制栅极和浮动栅极之间的第四绝缘层。公共源极线可以形成在位于第二绝缘层下方的衬底的一部分中。

8. 发明申请

US20110038252A1 DOUBLE LINKED WIRELESS SENSOR NETWORK BEING CAPABLE OF BIDIRECTIONAL COMMUNICATION AND METHOD THEREOF 有权
标题翻译：双向无线传感器网络可双向通信及其方法
公开(公告)号：US20110038252A1
公开(公告)日：2011-02-17
申请号：US12990131
申请日：2009-02-11
申请人： Tae-Yun Chung , Han-Su Chung , Jung-Ho Moon
发明人： Tae-Yun Chung , Han-Su Chung , Jung-Ho Moon
IPC分类号： H04L12/26 , H04W4/00
CPC分类号： H04W74/04 , H04W84/18
摘要： Provided are a double linked wireless sensor network capable of performing bidirectional communication and a method of transmitting and receiving data. In each of nodes constituting the wireless sensor network, an active duration and an inactive duration are alternately repeated, and the active duration is configured to include an upstream duration, an intermission duration, and a downstream duration. Each of the downstream duration and the upstream duration is configured to sequentially include a second receive slot, a second receive processing slot, a first receive slot, a first receive processing slot, a transmit slot, a transmit processing slot, a first acknowledge slot, a first acknowledge processing slot, a second acknowledge slot, and a second acknowledge processing slot, and wherein bidirectional communication can be performed between the sink node and the terminal node in a single period of the active duration. In the wireless sensor network, a transmit processing duration TXP is maintained in a receiving mode capable of receiving data from other nodes, so that a new node can be easily joined as a terminal node or an intermediate node. In addition, in the wireless sensor network, each of the upstream duration and the downstream duration is provided with consecutive two receiving durations, so that, although links to consecutive two nodes are disconnected, it is possible to simply recover the links.
摘要翻译：提供能够执行双向通信的双联无线传感器网络和发送和接收数据的方法。在构成无线传感器网络的每个节点中，交替地重复活动持续时间和非活跃持续时间，并且活动持续时间被配置为包括上行持续时间，中断持续时间和下游持续时间。下游持续时间和上游持续时间中的每个被配置为顺序地包括第二接收时隙，第二接收处理时隙，第一接收时隙，第一接收处理时隙，发射时隙，发射处理时隙，第一确认时隙，第一确认处理时隙，第二确认时隙和第二确认处理时隙，并且其中可以在活动持续时间的单个周期内在汇聚节点和终端节点之间执行双向通信。在无线传感器网络中，发送处理持续时间TXP保持在能够从其他节点接收数据的接收模式，使得新节点可以容易地连接为终端节点或中间节点。此外，在无线传感器网络中，上游持续时间和下游持续时间中的每一个具有连续的两个接收持续时间，使得尽管到连续的两个节点的链路被断开，但是可以简单地恢复链路。

9. 发明申请

US20110038210A1 Electrically Erasable Programmable Read-Only Memory (EEPROM) Cell and Methods for Forming and Reading the Same 有权
标题翻译：电可擦除可编程只读存储器（EEPROM）单元及其形成和读取方法
公开(公告)号：US20110038210A1
公开(公告)日：2011-02-17
申请号：US12912517
申请日：2010-10-26
申请人： Yong-Kyu Lee , Jeong-Uk Han , Hee-Seog Jeon , Jung-Ho Moon , Soung-Youb Ha
发明人： Yong-Kyu Lee , Jeong-Uk Han , Hee-Seog Jeon , Jung-Ho Moon , Soung-Youb Ha
IPC分类号： G11C16/26 , G11C16/04 , G11C16/30
CPC分类号： G11C16/0433 , G11C16/26 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： In a method of reading data in an EEPROM cell, a bit line voltage for reading is applied to the EEPROM cell including a memory transistor and a selection transistor. A first voltage is applied to a sense line of the memory transistor. A second voltage greater than the first voltage is applied to a word line of the selection transistor. A current passing through the EEPROM cell is compared with a predetermined reference current to read the data stored in the EEPROM cell. An on-cell current of the EEPROM cell may be increased in an erased state and the data in the cell may be readily discriminated.
摘要翻译：在EEPROM单元中读取数据的方法中，用于读取的位线电压被施加到包括存储晶体管和选择晶体管的EEPROM单元。第一电压被施加到存储晶体管的感测线。大于第一电压的第二电压被施加到选择晶体管的字线。将通过EEPROM单元的电流与预定的参考电流进行比较，以读取存储在EEPROM单元中的数据。可以在擦除状态下增加EEPROM单元的通电池电流，并且可以容易地区分单元中的数据。

10. 发明申请

US20050064661A1 Method of fabricating a flash memory cell 有权
标题翻译：制造闪存单元的方法
公开(公告)号：US20050064661A1
公开(公告)日：2005-03-24
申请号：US10874579
申请日：2004-06-24
申请人： Yong-Sun Lee , Jae-Min Yu , Don-Woo Lee , Jung-Hun Cho , Chul-Soon Kwon , Jung-Ho Moon , In-Gu Yoon , Jae-Hyun Park
发明人： Yong-Sun Lee , Jae-Min Yu , Don-Woo Lee , Jung-Hun Cho , Chul-Soon Kwon , Jung-Ho Moon , In-Gu Yoon , Jae-Hyun Park
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/336 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324
摘要： A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is etched to form an opening exposing a portion of the floating gate layer. A gate interlayer insulating layer pattern is formed inside the opening. After removing the sacrificial layer pattern and etching the floating gate layer (using the gate interlayer insulating layer pattern as an etch mask), a floating gate is formed under the gate interlayer insulating layer pattern. A control gate is formed overlapping a portion of the floating gate.
摘要翻译：一种制造具有分裂栅极结构的闪存单元的方法。牺牲层形成在形成在半导体衬底上的浮栅上。牺牲层被蚀刻以形成暴露浮动栅极层的一部分的开口。在开口内部形成栅极层间绝缘层图案。在去除牺牲层图案并蚀刻浮栅（使用栅极层间绝缘层图案作为蚀刻掩模）之后，在栅极层间绝缘层图案下方形成浮栅。控制栅极形成为与浮置栅极的一部分重叠。

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