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1. 发明申请

US20110316092A1 Mask Rom 有权
标题翻译：面具Rom
公开(公告)号：US20110316092A1
公开(公告)日：2011-12-29
申请号：US13050241
申请日：2011-03-17
申请人： Seung-Jin Yang , Yong-Tae Kim , Hyuck-Soo Yang , Jung-Ho Moon
发明人： Seung-Jin Yang , Yong-Tae Kim , Hyuck-Soo Yang , Jung-Ho Moon
IPC分类号： H01L27/112
CPC分类号： H01L27/0203 , H01L27/112 , H01L27/11253
摘要： A mask read-only memory (ROM) includes parallel doping lines of a second conductivity type formed in a substrate of a first conductivity type, a first insulation film formed on the doping lines and the substrate, conductive pads fainted on the first insulation film, a second insulation film formed on the first insulation film and the conductive pads, parallel wires formed on the second insulation film extending perpendicular to the doping lines, contact plugs formed in the first insulation film that connect the doping lines to the conductive pads, and vias formed in the second insulation film that connect the conductive pads to the wires, wherein crossings of the doping lines and the wires define memory cells, contact plugs and vias are formed in memory cells of a first type, and at least one of the contact plug and via are missing from memory cells of a second type.
摘要翻译：掩模只读存储器（ROM）包括形成在第一导电类型的衬底中的第二导电类型的并行掺杂线，形成在掺杂线和衬底上的第一绝缘膜，位于第一绝缘膜上的导电焊盘，形成在所述第一绝缘膜和所述导电焊盘上的第二绝缘膜，形成在垂直于所述掺杂线延伸的所述第二绝缘膜上的平行布线，形成在将所述掺杂线连接到所述导电焊盘的所述第一绝缘膜中的接触插塞，以及通孔形成在所述第二绝缘膜中，所述第二绝缘膜将所述导电焊盘连接到所述导线，其中所述掺杂线和所述布线的交叉限定存储器单元，接触插塞和通孔形成在第一类型的存储器单元中，并且所述接触插塞并且第二类型的存储器单元中缺少通孔。

2. 发明授权

US08507997B2 Mask read-only memory having a fake select transistor 有权
标题翻译：具有假选择晶体管的掩模只读存储器
公开(公告)号：US08507997B2
公开(公告)日：2013-08-13
申请号：US13050241
申请日：2011-03-17
申请人： Seung-Jin Yang , Yong-Tae Kim , Hyuck-Soo Yang , Jung-Ho Moon
发明人： Seung-Jin Yang , Yong-Tae Kim , Hyuck-Soo Yang , Jung-Ho Moon
IPC分类号： H01L21/70
CPC分类号： H01L27/0203 , H01L27/112 , H01L27/11253
摘要： A mask read-only memory (ROM) includes parallel doping lines of a second conductivity type formed in a substrate of a first conductivity type, a first insulation film formed on the doping lines and the substrate, conductive pads fainted on the first insulation film, a second insulation film formed on the first insulation film and the conductive pads, parallel wires formed on the second insulation film extending perpendicular to the doping lines, contact plugs formed in the first insulation film that connect the doping lines to the conductive pads, and vias formed in the second insulation film that connect the conductive pads to the wires, wherein crossings of the doping lines and the wires define memory cells, contact plugs and vias are formed in memory cells of a first type, and at least one of the contact plug and via are missing from memory cells of a second type.
摘要翻译：掩模只读存储器（ROM）包括形成在第一导电类型的衬底中的第二导电类型的并行掺杂线，形成在掺杂线和衬底上的第一绝缘膜，位于第一绝缘膜上的导电焊盘，形成在所述第一绝缘膜和所述导电焊盘上的第二绝缘膜，形成在垂直于所述掺杂线延伸的所述第二绝缘膜上的平行布线，形成在将所述掺杂线连接到所述导电焊盘的所述第一绝缘膜中的接触插塞，以及通孔形成在所述第二绝缘膜中，所述第二绝缘膜将所述导电焊盘连接到所述导线，其中所述掺杂线和所述布线的交叉限定存储器单元，接触插塞和通孔形成在第一类型的存储器单元中，并且所述接触插塞并且第二类型的存储器单元中缺少通孔。

3. 发明申请

US20070170491A1 Nonvolatile memory device and method of fabricating the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20070170491A1
公开(公告)日：2007-07-26
申请号：US11698658
申请日：2007-01-26
申请人： Yong-Suk Choi , Jeong-Uk Han , Hee-Seog Jeon , Yong-Tae Kim , Seung-Jin Yang , Hyok-Ki Kwon
发明人： Yong-Suk Choi , Jeong-Uk Han , Hee-Seog Jeon , Yong-Tae Kim , Seung-Jin Yang , Hyok-Ki Kwon
IPC分类号： H01L29/788
CPC分类号： H01L29/42336 , H01L27/115 , H01L27/11521 , H01L29/7881
摘要： a nonvolatile memory device Includes an active region defined in a semiconductor substrate and a control gate electrode crossing over the active region. A gate insulating layer is interposed between the control gate electrode and the active reigon. A floating gate is formed in the active region to penetrate the control gate electrode and extend to a predetermined depth into the semiconductor substrate. A tunnel insulating layer is successively interposed between the control gate electrode and the floating gate, and between the semiconductor substrate and the floating gate. The floating gate may be formed after a trench is formed by sequentially etching a control gate conductive layer and the semiconductor substrate, and a tunnel insulating layer is formed on the trench and sidewalls of the control gate conductive layer. The floating gate is formed in the trench to extend into a predetermined depth into the semiconductor substrate.
摘要翻译：非易失性存储器件包括限定在半导体衬底中的有源区和跨越有源区的控制栅电极。栅极绝缘层介于控制栅极电极和活性电极之间。在有源区中形成浮栅，以穿透控制栅电极并延伸到预定深度进入半导体衬底。隧道绝缘层被连续插入在控制栅电极和浮栅之间以及半导体衬底和浮栅之间。可以在通过顺序蚀刻控制栅极导电层和半导体衬底形成沟槽之后形成浮置栅极，并且在控制栅极导电层的沟槽和侧壁上形成隧道绝缘层。浮动栅极形成在沟槽中，以延伸到预定深度进入半导体衬底。

4. 发明申请

US20110175175A1 SEMICONDUCTOR DEVICE FOR APPLYING COMMON SOURCE LINES WITH INDIVIDUAL BIAS VOLTAGES 有权
标题翻译：用于应用具有独立偏置电压的公共源线的半导体器件
公开(公告)号：US20110175175A1
公开(公告)日：2011-07-21
申请号：US12956920
申请日：2010-11-30
申请人： Seung-Jin Yang , Yong-Tae Kim
发明人： Seung-Jin Yang , Yong-Tae Kim
IPC分类号： H01L27/088
CPC分类号： H01L21/823425 , H01L27/112 , H01L27/11253 , H01L27/11519 , H01L27/11521
摘要： Provided is a semiconductor device for applying common source lines with individual bias voltages. The device includes a substrate, cell transistors arrayed in a cell matrix shape on the substrate and configured to have gate insulating patterns, gate electrodes, common source regions, drain regions and channel regions. Word lines are configured to electrically interconnect the gate electrodes with each other. Common source lines are shared between only a pair of the neighboring word lines and are configured to electrically interconnect the common source regions with each other. Drain metal contacts and source metal contacts are arranged in a straight line on the drain regions. Bit lines are electrically connected to the drain metal contacts. And impurity regions are configured to control the threshold voltage of the channel regions.
摘要翻译：提供了一种用于以单独的偏置电压施加公共源极线的半导体器件。该器件包括衬底，在衬底上以单元矩阵形状排列的单元晶体管，并且被配置为具有栅极绝缘图案，栅极电极，公共源极区域，漏极区域和沟道区域。字线被配置为将栅电极彼此电互连。公共源极线仅在一对相邻字线之间共享并且被配置为将公共源极区域彼此电互连。漏极金属触点和源极金属触点排列在漏极区域的直线上。位线电连接到漏极金属触点。并且杂质区域被配置为控制沟道区域的阈值电压。

5. 发明授权

US07973314B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07973314B2
公开(公告)日：2011-07-05
申请号：US12117630
申请日：2008-05-08
申请人： Seung-Jin Yang , Jeong-Uk Han , Yong-Tae Kim , Yong-Suk Choi , Hyok-Ki Kwon
发明人： Seung-Jin Yang , Jeong-Uk Han , Yong-Tae Kim , Yong-Suk Choi , Hyok-Ki Kwon
IPC分类号： H01L29/76 , H01L31/036 , H01L31/112
CPC分类号： H01L27/105 , H01L21/76898 , H01L21/8221 , H01L23/485 , H01L27/0688 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11551 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a first semiconductor layer including a first circuit, a second semiconductor layer disposed on the first semiconductor layer and having a second circuit, and a via extending through portions of the first and second semiconductor layers and by which the first and second circuits are electrically connected. One of the circuits is a logic circuit and the other of the circuits is a memory circuit. The semiconductor device is manufactured by fabricating transistors of the logic and memory circuits on respective substrates, stacking the substrates, and electrically connecting the logic and memory circuits with a via.
摘要翻译：半导体器件具有第一半导体层，其包括第一电路，设置在第一半导体层上并具有第二电路的第二半导体层，以及延伸穿过第一和第二半导体层的部分的通孔，并且第一半导体层和第二电路电连接。电路中的一个是逻辑电路，另一个电路是存储器电路。半导体器件通过在各个衬底上制造逻辑电路和存储器电路的晶体管，堆叠衬底以及将逻辑电路和存储器电路与通孔电连接来制造。

6. 发明申请

US20100001328A1 SEMICONDUCTOR DEVICE HAVING AN ANTI-PAD PEELING-OFF STRUCTURE 审中-公开
标题翻译：具有防褪色结构的半导体器件
公开(公告)号：US20100001328A1
公开(公告)日：2010-01-07
申请号：US12498724
申请日：2009-07-07
申请人： Seung-Jin Yang , Jeong-Uk Han , Yong-Tae Kim , Yong-Suk Choi , Bae-Seong Kwon
发明人： Seung-Jin Yang , Jeong-Uk Han , Yong-Tae Kim , Yong-Suk Choi , Bae-Seong Kwon
IPC分类号： H01L27/105 , H01L29/40 , H01L27/108 , H01L29/792
CPC分类号： H01L24/05 , H01L24/03 , H01L27/11526 , H01L2224/05093 , H01L2224/05096 , H01L2224/05166 , H01L2224/05187 , H01L2224/05556 , H01L2224/05557 , H01L2224/05567 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/85375 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/10253 , H01L2924/13091 , H01L2924/19041 , H01L2924/30105 , H01L2924/3025 , H01L2924/04941 , H01L2924/04953 , H01L2924/00014 , H01L2924/00 , H01L2224/05552
摘要： A bonding pad having an anti-pad peeling-off structure is disclosed. In a method of forming the bonding pad, after a metal pad layer is formed, a slit is formed in the metal pad layer. A protecting layer is formed on the metal pad layer. The protecting layer is partially removed to expose the metal pad such that a portion of the protecting layer remains in the slits to be connected to the main protecting layer. The protecting layer formed in the slit is connected to the protecting layer such that the residual protecting layer pattern buffer when physical impacts are generated, to prevent peeling-off of the metal pad layer.
摘要翻译：公开了一种具有防焊垫剥离结构的焊盘。在形成接合焊盘的方法中，在形成金属焊盘层之后，在金属焊盘层中形成狭缝。在金属垫层上形成保护层。部分去除保护层以露出金属垫，使得保护层的一部分保留在狭缝中以连接到主保护层。形成在狭缝中的保护层连接到保护层，使得当产生物理冲击时残留保护层图案缓冲，以防止金属垫层的剥离。

7. 发明授权

US07642593B2 Nonvolatile memory device and method of fabricating the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07642593B2
公开(公告)日：2010-01-05
申请号：US11698658
申请日：2007-01-26
申请人： Yong-Suk Choi , Jeong-Uk Han , Hee-Seog Jeon , Yong-Tae Kim , Seung-Jin Yang , Hyok-Ki Kwon
发明人： Yong-Suk Choi , Jeong-Uk Han , Hee-Seog Jeon , Yong-Tae Kim , Seung-Jin Yang , Hyok-Ki Kwon
IPC分类号： H01L21/336
CPC分类号： H01L29/42336 , H01L27/115 , H01L27/11521 , H01L29/7881
摘要： a nonvolatile memory device Includes an active region defined in a semiconductor substrate and a control gate electrode crossing over the active region. A gate insulating layer is interposed between the control gate electrode and the active reigon. A floating gate is formed in the active region to penetrate the control gate electrode and extend to a predetermined depth into the semiconductor substrate. A tunnel insulating layer is successively interposed between the control gate electrode and the floating gate, and between the semiconductor substrate and the floating gate. The floating gate may be formed after a trench is formed by sequentially etching a control gate conductive layer and the semiconductor substrate, and a tunnel insulating layer is formed on the trench and sidewalls of the control gate conductive layer. The floating gate is formed in the trench to extend into a predetermined depth into the semiconductor substrate.
摘要翻译：非易失性存储器件包括限定在半导体衬底中的有源区和跨越有源区的控制栅电极。栅极绝缘层介于控制栅极电极和活性电极之间。在有源区中形成浮栅，以穿透控制栅电极并延伸到预定深度进入半导体衬底。隧道绝缘层被连续插入在控制栅电极和浮栅之间以及半导体衬底和浮栅之间。可以在通过顺序蚀刻控制栅极导电层和半导体衬底形成沟槽之后形成浮置栅极，并且在控制栅极导电层的沟槽和侧壁上形成隧道绝缘层。浮动栅极形成在沟槽中，以延伸到预定深度进入半导体衬底。

8. 发明授权

US08450809B2 Semiconductor device for applying common source lines with individual bias voltages 有权
标题翻译：用于应用具有单独偏置电压的公共源极线的半导体器件
公开(公告)号：US08450809B2
公开(公告)日：2013-05-28
申请号：US12956920
申请日：2010-11-30
申请人： Seung-Jin Yang , Yong-Tae Kim
发明人： Seung-Jin Yang , Yong-Tae Kim
IPC分类号： H01L29/76 , H01L29/94 , H01L27/10 , H01L27/108 , H01L31/062
CPC分类号： H01L21/823425 , H01L27/112 , H01L27/11253 , H01L27/11519 , H01L27/11521
摘要： Provided is a semiconductor device for applying common source lines with individual bias voltages. The device includes a substrate, cell transistors arrayed in a cell matrix shape on the substrate and configured to have gate insulating patterns, gate electrodes, common source regions, drain regions and channel regions. Word lines are configured to electrically interconnect the gate electrodes with each other. Common source lines are shared between only a pair of the neighboring word lines and are configured to electrically interconnect the common source regions with each other. Drain metal contacts and source metal contacts are arranged in a straight line on the drain regions. Bit lines are electrically connected to the drain metal contacts. And impurity regions are configured to control the threshold voltage of the channel regions.
摘要翻译：提供了一种用于以单独的偏置电压施加公共源极线的半导体器件。该器件包括衬底，在衬底上以单元矩阵形状排列的单元晶体管，并且被配置为具有栅极绝缘图案，栅极电极，公共源极区域，漏极区域和沟道区域。字线被配置为将栅电极彼此电互连。公共源极线仅在一对相邻字线之间共享并且被配置为将公共源极区域彼此电互连。漏极金属触点和源极金属触点排列在漏极区域的直线上。位线电连接到漏极金属触点。并且杂质区域被配置为控制沟道区域的阈值电压。

9. 发明授权

US08320184B2 Method of programming nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件编程方法
公开(公告)号：US08320184B2
公开(公告)日：2012-11-27
申请号：US12961133
申请日：2010-12-06
申请人： Seung-Jin Yang , Yong-Tae Kim
发明人： Seung-Jin Yang , Yong-Tae Kim
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/10
摘要： A method of programming a nonvolatile semiconductor memory device using a negative bias voltage. The method includes turning ON the string selection transistors connected to selected bit lines and turning OFF the string selection transistors connected to unselected bit lines in the same memory block, in a program mode. This can be achieved by applying a negative bias voltage to a bulk substrate and applying a voltage having a voltage level higher than the threshold voltage of string selection transistors connected to selected bit lines and lower than the threshold voltage of string selection transistors connected to unselected bit lines. The method may reduce programming disturbance between a selected cell string and an unselected cell string.
摘要翻译：一种使用负偏置电压编程非易失性半导体存储器件的方法。该方法包括在编程模式中接通连接到选定位线的串选择晶体管，并将连接到同一存储块中的未选择位线的串选择晶体管截止。这可以通过将负偏置电压施加到体基板并且施加具有高于连接到选定位线的串选择晶体管的阈值电压的电压电平并且低于连接到未选位的串选择晶体管的阈值电压的电压线条。该方法可以减少所选择的单元串与未选择的单元串之间的编程干扰。

10. 发明申请

US20110182117A1 METHOD OF PROGRAMMING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件的编程方法
公开(公告)号：US20110182117A1
公开(公告)日：2011-07-28
申请号：US12961133
申请日：2010-12-06
申请人： Seung-Jin Yang , Yong-Tae Kim
发明人： Seung-Jin Yang , Yong-Tae Kim
IPC分类号： G11C16/12 , G11C16/04
CPC分类号： G11C16/0483 , G11C16/10
摘要： A method of programming a nonvolatile semiconductor memory device using a negative bias voltage. The method includes turning ON the string selection transistors connected to selected bit lines and turning OFF the string selection transistors connected to unselected bit lines in the same memory block, in a program mode. This can be achieved by applying a negative bias voltage to a bulk substrate and applying a voltage having a voltage level higher than the threshold voltage of string selection transistors connected to selected bit lines and lower than the threshold voltage of string selection transistors connected to unselected bit lines. The method may reduce programming disturbance between a selected cell string and an unselected cell string.
摘要翻译：一种使用负偏置电压编程非易失性半导体存储器件的方法。该方法包括在编程模式中接通连接到选定位线的串选择晶体管，并将连接到同一存储块中的未选择位线的串选择晶体管截止。这可以通过将负偏置电压施加到体基板并且施加具有高于连接到选定位线的串选择晶体管的阈值电压的电压电平并且低于连接到未选位的串选择晶体管的阈值电压的电压线条。该方法可以减少所选择的单元串与未选择的单元串之间的编程干扰。

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