专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070252190A1 Nonvolatile memory device and method for manufacturing the same 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20070252190A1
公开(公告)日：2007-11-01
申请号：US11653962
申请日：2007-01-17
申请人： Jae-Hyun Park , Chul-Soon Kwon , Jae-Min Yu , Ji-Woon Rim , Young-Cheon Jeong , In-Gu Yoon , Jung-Ho Moon
发明人： Jae-Hyun Park , Chul-Soon Kwon , Jae-Min Yu , Ji-Woon Rim , Young-Cheon Jeong , In-Gu Yoon , Jung-Ho Moon
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521 , H01L29/7885
摘要： Provided are a nonvolatile memory device and a method for manufacturing the same. The nonvolatile memory device may include a semiconductor substrate, a floating gate, a second insulation layer, a third insulation layer, a control gate, and a common source line. The semiconductor substrate may have an active region limited by a device isolation region. The floating gate may be formed on the active region with a first insulation layer between the floating gate and the active region. The second insulation layer covers one side of the floating gate, and the third insulation layer covers the floating gate and the second insulation layer. The control gate may be formed on the other side of the floating gate with a fourth insulation layer between the control gate and the floating gate. The common source line may be formed in a portion of the substrate that is located under the second insulation layer.
摘要翻译：提供一种非易失性存储器件及其制造方法。非易失性存储器件可以包括半导体衬底，浮置栅极，第二绝缘层，第三绝缘层，控制栅极和公共源极线。半导体衬底可以具有被器件隔离区限制的有源区。浮置栅极可以在有源区上形成在浮置栅极和有源区域之间的第一绝缘层。第二绝缘层覆盖浮栅的一侧，第三绝缘层覆盖浮栅和第二绝缘层。控制栅极可以在浮动栅极的另一侧上形成在控制栅极和浮动栅极之间的第四绝缘层。公共源极线可以形成在位于第二绝缘层下方的衬底的一部分中。

2. 发明申请

US20080050875A1 Methods of fabricating embedded flash memory devices 审中-公开
标题翻译：制造嵌入式闪存设备的方法
公开(公告)号：US20080050875A1
公开(公告)日：2008-02-28
申请号：US11645576
申请日：2006-12-27
申请人： Jung-Ho Moon , Chul-Soon Kwon , Jae-Min Yu , Young-Cheon Jeong , In-Gu Yoon , Byeong-Cheol Lim
发明人： Jung-Ho Moon , Chul-Soon Kwon , Jae-Min Yu , Young-Cheon Jeong , In-Gu Yoon , Byeong-Cheol Lim
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11539
摘要： A method of fabricating a compound device includes forming a first gate insulating pattern on a semiconductor substrate including a first region and a second region, forming a second gate insulating layer on the first gate insulating pattern, and after forming the second gate insulating layer, forming a well in the second region of the semiconductor substrate.
摘要翻译：一种复合器件的制造方法包括在包括第一区域和第二区域的半导体衬底上形成第一栅极绝缘图案，在第一栅极绝缘图案上形成第二栅极绝缘层，在形成第二栅极绝缘层之后，形成在半导体衬底的第二区域中的阱。

3. 发明授权

US06974748B2 Semiconductor device with split gate electrode structure and method for manufacturing the semiconductor device 失效
公开(公告)号：US06974748B2
公开(公告)日：2005-12-13
申请号：US10920158
申请日：2004-08-18
申请人： Jung-Ho Moon , Jae-Min Yu , Don-Woo Lee , Chul-Soon Kwon , In-Gu Yoon , Yong-Sun Lee , Jae-Hyun Park
发明人： Jung-Ho Moon , Jae-Min Yu , Don-Woo Lee , Chul-Soon Kwon , In-Gu Yoon , Yong-Sun Lee , Jae-Hyun Park
IPC分类号： H01L27/10 , H01L21/336 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11539
摘要： A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.

4. 发明申请

US20050064661A1 Method of fabricating a flash memory cell 有权
标题翻译：制造闪存单元的方法
公开(公告)号：US20050064661A1
公开(公告)日：2005-03-24
申请号：US10874579
申请日：2004-06-24
申请人： Yong-Sun Lee , Jae-Min Yu , Don-Woo Lee , Jung-Hun Cho , Chul-Soon Kwon , Jung-Ho Moon , In-Gu Yoon , Jae-Hyun Park
发明人： Yong-Sun Lee , Jae-Min Yu , Don-Woo Lee , Jung-Hun Cho , Chul-Soon Kwon , Jung-Ho Moon , In-Gu Yoon , Jae-Hyun Park
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/336 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324
摘要： A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is etched to form an opening exposing a portion of the floating gate layer. A gate interlayer insulating layer pattern is formed inside the opening. After removing the sacrificial layer pattern and etching the floating gate layer (using the gate interlayer insulating layer pattern as an etch mask), a floating gate is formed under the gate interlayer insulating layer pattern. A control gate is formed overlapping a portion of the floating gate.
摘要翻译：一种制造具有分裂栅极结构的闪存单元的方法。牺牲层形成在形成在半导体衬底上的浮栅上。牺牲层被蚀刻以形成暴露浮动栅极层的一部分的开口。在开口内部形成栅极层间绝缘层图案。在去除牺牲层图案并蚀刻浮栅（使用栅极层间绝缘层图案作为蚀刻掩模）之后，在栅极层间绝缘层图案下方形成浮栅。控制栅极形成为与浮置栅极的一部分重叠。

5. 发明授权

US07375391B2 Semiconductor device with split gate electrode structure and method for manufacturing the semiconductor device 失效
标题翻译：具有分裂栅电极结构的半导体器件和用于制造半导体器件的方法
公开(公告)号：US07375391B2
公开(公告)日：2008-05-20
申请号：US11246590
申请日：2005-10-11
申请人： Jung-Ho Moon , Jae-Min Yu , Don-Woo Lee , Chul-Soon Kwon , In-Gu Yoon , Yong-Sun Lee , Jae-Hyun Park
发明人： Jung-Ho Moon , Jae-Min Yu , Don-Woo Lee , Chul-Soon Kwon , In-Gu Yoon , Yong-Sun Lee , Jae-Hyun Park
IPC分类号： H01L29/76 , H01L29/788 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11539
摘要： A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.
摘要翻译：半导体器件包括分为存储单元区域和逻辑区域的衬底。在基板的存储单元区域中形成分割栅电极结构。在分离栅电极结构的侧壁和基板的表面上形成氧化硅层。在位于分离栅电极结构的侧壁上的氧化硅层上形成字线。字线具有上宽度和下宽度。较低的宽度大于上部宽度。在基板的逻辑区域上形成逻辑门图案。逻辑门图案具有比字线的较低宽度更薄的厚度。

6. 发明授权

US07205194B2 Method of fabricating a flash memory cell 有权
标题翻译：制造闪存单元的方法
公开(公告)号：US07205194B2
公开(公告)日：2007-04-17
申请号：US10874579
申请日：2004-06-24
申请人： Yong-Sun Lee , Jae-Min Yu , Don-Woo Lee , Jung-Hun Cho , Chul-Soon Kwon , Jung-Ho Moon , In-Gu Yoon , Jae-Hyun Park
发明人： Yong-Sun Lee , Jae-Min Yu , Don-Woo Lee , Jung-Hun Cho , Chul-Soon Kwon , Jung-Ho Moon , In-Gu Yoon , Jae-Hyun Park
IPC分类号： H01L21/336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324
摘要： A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is etched to form an opening exposing a portion of the floating gate layer. A gate interlayer insulating layer pattern is formed inside the opening. After removing the sacrificial layer pattern and etching the floating gate layer (using the gate interlayer insulating layer pattern as an etch mask), a floating gate is formed under the gate interlayer insulating layer pattern. A control gate is formed overlapping a portion of the floating gate.
摘要翻译：一种制造具有分裂栅极结构的闪存单元的方法。牺牲层形成在形成在半导体衬底上的浮栅上。牺牲层被蚀刻以形成暴露浮动栅极层的一部分的开口。在开口内部形成栅极层间绝缘层图案。在去除牺牲层图案并蚀刻浮栅（使用栅极层间绝缘层图案作为蚀刻掩模）之后，在栅极层间绝缘层图案下方形成浮栅。控制栅极形成为与浮置栅极的一部分重叠。

7. 发明申请

US20060027858A1 Semiconductor device with split gate electrode structure and method for manufacturing the semiconductor device 失效
标题翻译：具有分裂栅电极结构的半导体器件和用于制造半导体器件的方法
公开(公告)号：US20060027858A1
公开(公告)日：2006-02-09
申请号：US11246590
申请日：2005-10-11
申请人： Jung-Ho Moon , Jae-Min Yu , Don-Woo Lee , Chul-Soon Kwon , In-Gu Yoon , Yong-Sun Lee , Jae-Hyun Park
发明人： Jung-Ho Moon , Jae-Min Yu , Don-Woo Lee , Chul-Soon Kwon , In-Gu Yoon , Yong-Sun Lee , Jae-Hyun Park
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11539
摘要： A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.
摘要翻译：半导体器件包括分为存储单元区域和逻辑区域的衬底。在基板的存储单元区域中形成分割栅电极结构。在分离栅电极结构的侧壁和基板的表面上形成氧化硅层。在位于分离栅电极结构的侧壁上的氧化硅层上形成字线。字线具有上宽度和下宽度。较低的宽度大于上部宽度。在基板的逻辑区域上形成逻辑门图案。逻辑门图案具有比字线的较低宽度更薄的厚度。

8. 发明申请

US20050042828A1 Semiconductor device with split gate electrode structure and method for manufacturing the semiconductor device 失效
标题翻译：具有分裂栅电极结构的半导体器件和用于制造半导体器件的方法
公开(公告)号：US20050042828A1
公开(公告)日：2005-02-24
申请号：US10920158
申请日：2004-08-18
申请人： Jung-Ho Moon , Jae-Min Yu , Don-Woo Lee , Chul-Soon Kwon , In-Gu Yoon , Yong-Sun Lee , Jae-Hyun Park
发明人： Jung-Ho Moon , Jae-Min Yu , Don-Woo Lee , Chul-Soon Kwon , In-Gu Yoon , Yong-Sun Lee , Jae-Hyun Park
IPC分类号： H01L27/10 , H01L21/336 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11539
摘要： A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.
摘要翻译：半导体器件包括分为存储单元区域和逻辑区域的衬底。在基板的存储单元区域中形成分割栅电极结构。在分离栅电极结构的侧壁和基板的表面上形成氧化硅层。在位于分离栅电极结构的侧壁上的氧化硅层上形成字线。字线具有上宽度和下宽度。较低的宽度大于上部宽度。在基板的逻辑区域上形成逻辑门图案。逻辑门图案具有比字线的较低宽度更薄的厚度。

9. 发明申请

US20070200165A1 Floating gate, a nonvolatile memory device including the floating gate and method of fabricating the same 审中-公开
标题翻译：浮动栅极，包括浮动栅极的非易失性存储器件及其制造方法
公开(公告)号：US20070200165A1
公开(公告)日：2007-08-30
申请号：US11656454
申请日：2007-01-23
申请人： Young-Cheon Jeong , Chul-Soon Kwon , Jae-Min Yu , Jae-Hyun Park , Jung-Ho Moon , Soung-Youb Ha , Byeong-Cheol Lim
发明人： Young-Cheon Jeong , Chul-Soon Kwon , Jae-Min Yu , Jae-Hyun Park , Jung-Ho Moon , Soung-Youb Ha , Byeong-Cheol Lim
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521 , H01L29/7885
摘要： Example embodiments may provide a nonvolatile memory device. The example embodiment nonvolatile memory device may include a floating gate structure formed on a semiconductor substrate with a gate insulating layer between them and/or a control gate formed adjacent to the floating gate with a tunneling insulation layer between them. The floating gate may include a first floating gate formed on the gate insulating layer, a second floating gate formed on the first floating gate with a first insulating pattern between them, and/or a gate connecting layer formed on at least one sidewall of the first insulating pattern so that the gate conducting layer may electrically connect the first floating gate and the second floating gate. The second floating gate may have a tip formed at its longitudinal end that may not contact the gate connecting layer.
摘要翻译：示例性实施例可以提供非易失性存储器件。示例性实施例非易失性存储器件可以包括形成在半导体衬底上的浮置栅极结构，其间具有栅极绝缘层和/或与浮置栅极相邻形成的控制栅极，在它们之间具有隧道绝缘层。浮置栅极可以包括形成在栅极绝缘层上的第一浮动栅极，形成在第一浮动栅极上的第二浮置栅极，其间具有第一绝缘图案，和/或形成在第一浮动栅极的至少一个侧壁上的栅极连接层绝缘图案，使得栅极导电层可以电连接第一浮动栅极和第二浮动栅极。第二浮栅可以在其纵向端形成有可能不接触栅极连接层的尖端。

10. 发明授权

US08203981B2 Wireless sensor network with linear structure being capable of bidirectional communication and method thereof 有权
标题翻译：具有线性结构的无线传感器网络能够进行双向通信及其方法
公开(公告)号：US08203981B2
公开(公告)日：2012-06-19
申请号：US12449103
申请日：2008-01-09
申请人： Tae-Yun Chung , Han-Su Chung , Jung-Ho Moon
发明人： Tae-Yun Chung , Han-Su Chung , Jung-Ho Moon
IPC分类号： H04L5/14
CPC分类号： H04W72/1257 , H04W56/0015 , H04W84/18
摘要： Disclosed is a wireless sensor network with a linear structure capable of bidirectional communication. The wireless sensor network includes a plurality of nodes linearly connected from a sink node to a terminal node by connecting each node to a single upper-level node and a single lower-level node, each node has an active period for transmitting/receiving data to/from its upper-level node and lower-level node, the active period includes a downstream duration for transmitting data/commands from the sink node to the terminal node and an upstream duration for transmitting data/commands from the terminal node to the sink node, and each of the upstream and downstream durations sequentially includes RX, TX, and ACK intervals, so that bidirectional communication between the sink node and the terminal node can be performed within a single active period.
摘要翻译：公开了具有能够双向通信的线性结构的无线传感器网络。无线传感器网络包括通过将每个节点连接到单个上层节点和单个下级节点而从宿节点线路连接到终端节点的多个节点，每个节点具有用于发送/接收数据的活动周期 /从其上级节点和下级节点，活动时段包括用于从汇聚节点向终端节点发送数据/命令的下游持续时间，以及从终端节点向汇聚节点发送数据/命令的上行持续时间，并且上游和下游持续时间中的每一个顺序地包括RX，TX和ACK间隔，使得宿节点和终端节点之间的双向通信可以在单个活动时段内执行。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式