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1. 发明授权

US07741168B2 Systems and methods for fabricating nanometric-scale semiconductor devices with dual-stress layers using double-stress oxide/nitride stacks 失效
标题翻译：使用双应力氧化物/氮化物叠层制造具有双应力层的纳米尺度半导体器件的系统和方法
公开(公告)号：US07741168B2
公开(公告)日：2010-06-22
申请号：US11782984
申请日：2007-07-25
申请人： Seung-Chul Song , Joel Barnett , Byong Sun Ju
发明人： Seung-Chul Song , Joel Barnett , Byong Sun Ju
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L29/7843
摘要： Systems and methods for fabricating semiconductor devices with dual-stress layers using double-stress oxide/nitride stacks. A method comprises providing NMOS and PMOS regions, selectively forming a dual-stack tensile stress layer over the NMOS region by depositing a tensile silicon nitride layer over the NMOS and PMOS regions, depositing a tensile silicon oxide layer over the tensile silicon nitride layer, removing a portion of the tensile silicon oxide layer from the PMOS region, and removing a portion of the tensile silicon nitride layer from the NMOS region and selectively forming a dual stack compressive stress layer over the PMOS region by depositing a compressive silicon nitride layer over the NMOS and PMOS regions, depositing a compressive silicon oxide layer over the compressive silicon nitride layer, removing a portion of the compressive silicon oxide layer from the NMOS region, and removing a portion of the compressive silicon nitride layer from the NMOS region.
摘要翻译：使用双应力氧化物/氮化物叠层制造具有双应力层的半导体器件的系统和方法。一种方法包括提供NMOS和PMOS区域，通过在NMOS和PMOS区域上沉积拉伸氮化硅层，在拉伸氮化硅层上方沉积拉伸氧化硅层，去除来自所述PMOS区的所述拉伸氧化硅层的一部分，以及从所述NMOS区域去除所述拉伸氮化硅层的一部分，并且在所述PMOS区上选择性地形成双层压应力层，通过在所述NMOS上沉积压缩氮化硅层和PMOS区域，在所述压缩氮化硅层上沉积压缩氧化硅层，从所述NMOS区域去除所述压缩氧化硅层的一部分，以及从所述NMOS区域移除所述压缩氮化硅层的一部分。

2. 发明申请

US20090026548A1 Systems And Methods For Fabricating Nanometric-Scale Semiconductor Devices With Dual-Stress Layers Using Double-Stress Oxide/Nitride Stacks 失效
标题翻译：使用双应力氧化物/氮化物叠层制造具有双应力层的纳米尺度半导体器件的系统和方法
公开(公告)号：US20090026548A1
公开(公告)日：2009-01-29
申请号：US11782984
申请日：2007-07-25
申请人： Seung-Chul Song , Joel Barnett , Byong Sun Ju
发明人： Seung-Chul Song , Joel Barnett , Byong Sun Ju
IPC分类号： H01L21/31 , H01L29/78
CPC分类号： H01L21/823807 , H01L29/7843
摘要： Systems and methods for fabricating semiconductor devices with dual-stress layers using double-stress oxide/nitride stacks. A method comprises providing NMOS and PMOS regions, selectively forming a dual-stack tensile stress layer over the NMOS region by depositing a tensile silicon nitride layer over the NMOS and PMOS regions, depositing a tensile silicon oxide layer over the tensile silicon nitride layer, removing a portion of the tensile silicon oxide layer from the PMOS region, and removing a portion of the tensile silicon nitride layer from the NMOS region and selectively forming a dual stack compressive stress layer over the PMOS region by depositing a compressive silicon nitride layer over the NMOS and PMOS regions, depositing a compressive silicon oxide layer over the compressive silicon nitride layer, removing a portion of the compressive silicon oxide layer from the NMOS region, and removing a portion of the compressive silicon nitride layer from the NMOS region.
摘要翻译：使用双应力氧化物/氮化物叠层制造具有双应力层的半导体器件的系统和方法。一种方法包括提供NMOS和PMOS区域，通过在NMOS和PMOS区域上沉积拉伸氮化硅层，在拉伸氮化硅层上方沉积拉伸氧化硅层，去除来自所述PMOS区的所述拉伸氧化硅层的一部分，以及从所述NMOS区域去除所述拉伸氮化硅层的一部分，并且在所述PMOS区上选择性地形成双层压应力层，通过在所述NMOS上沉积压缩氮化硅层和PMOS区域，在所述压缩氮化硅层上沉积压缩氧化硅层，从所述NMOS区域去除所述压缩氧化硅层的一部分，以及从所述NMOS区域移除所述压缩氮化硅层的一部分。

3. 发明申请

US20070048920A1 Methods for dual metal gate CMOS integration 审中-公开
标题翻译：双金属栅极CMOS集成方法
公开(公告)号：US20070048920A1
公开(公告)日：2007-03-01
申请号：US11212127
申请日：2005-08-25
申请人： Seung-Chul Song , Zhibo Zhang , Byoung Lee , Naim Moumen , Joel Barnett , Muhammad Hussain , Rino Choi , Husam Alshareef
发明人： Seung-Chul Song , Zhibo Zhang , Byoung Lee , Naim Moumen , Joel Barnett , Muhammad Hussain , Rino Choi , Husam Alshareef
IPC分类号： H01L21/8238 , H01L21/8234 , H01L21/4763 , H01L21/3205
CPC分类号： H01L21/823842
摘要： Methods for fabricating two metal gate stacks for complementary metal oxide semiconductor (CMOS) devices are provided. A first metal layer may be deposited onto a gate dielectric. Next a mask layer may be deposited on the first metal layer and subsequently etch. The first metal layer is then etched. Without removing the mask layer, a second metal layer may be deposited. In one embodiment, the mask layer is a second metal layer. In other embodiments, the mask layer is a silicon layer. Subsequent fabrication steps include depositing another metal layer (e.g., another PMOS metal layer), depositing a cap, etching the cap to define gate stacks, and simultaneously etching the first and second gate region having a similar thickness with differing metal layers.
摘要翻译：提供了用于制造用于互补金属氧化物半导体（CMOS）器件的两个金属栅极叠层的方法。可以将第一金属层沉积到栅极电介质上。接下来，掩模层可以沉积在第一金属层上并随后蚀刻。然后蚀刻第一金属层。在不去除掩模层的情况下，可沉积第二金属层。在一个实施例中，掩模层是第二金属层。在其他实施例中，掩模层是硅层。随后的制造步骤包括沉积另一金属层（例如，另一个PMOS金属层），沉积帽，蚀刻帽以限定栅极堆叠，以及同时用不同的金属层蚀刻具有相似厚度的第一和第二栅极区域。

4. 发明申请

US20070059874A1 Dual Metal Gate and Method of Manufacture 审中-公开
标题翻译：双金属门和制造方法
公开(公告)号：US20070059874A1
公开(公告)日：2007-03-15
申请号：US11456054
申请日：2006-07-06
申请人： Naim Moumen , Husam Alshareef , Joel Barnett , Muhammad Hussain , Hongfa Luan , Seung-Chul Song , Raj Jammy
发明人： Naim Moumen , Husam Alshareef , Joel Barnett , Muhammad Hussain , Hongfa Luan , Seung-Chul Song , Raj Jammy
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： Methods for fabricating two metal gate stacks for complementary metal oxide semiconductor (CMOS) devices are provided. A common layer, such as a metal layer, a metal alloy layer, or a metal nitride layer may be deposited on to a gate dielectric. A first mask layer may be deposited and patterned over an active region, exposing a portion of the common layer. A first ion may be deposited in the common layer forming a first mask layer. Similarly, a second mask layer may be deposited and patterned over the other active region and the first metal layer, and another portion of the common layer is exposed. A second ion may be deposited in the common layer, forming a second mask layer.
摘要翻译：提供了用于制造用于互补金属氧化物半导体（CMOS）器件的两个金属栅极叠层的方法。诸如金属层，金属合金层或金属氮化物层的公共层可以沉积到栅极电介质上。可以在有源区上沉积和图案化第一掩模层，暴露公共层的一部分。可以在形成第一掩模层的公共层中沉积第一离子。类似地，第二掩模层可以在另一个有源区和第一金属层上沉积和图案化，并且公共层的另一部分被暴露。可以在公共层中沉积第二离子，形成第二掩模层。

5. 发明授权

US08796777B2 Fin-type device system and method 有权
标题翻译：翅片式装置系统及方法
公开(公告)号：US08796777B2
公开(公告)日：2014-08-05
申请号：US12552359
申请日：2009-09-02
申请人： Seung-Chul Song , Mohamed Abu-Rahma , Beom-Mo Han
发明人： Seung-Chul Song , Mohamed Abu-Rahma , Beom-Mo Han
IPC分类号： H01L29/786 , H01L29/78
CPC分类号： H01L29/785 , G11C11/40 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L27/10879 , H01L29/66795 , H01L29/7831 , H01L29/7841 , H01L29/7855 , H01L29/78648
摘要： A method includes forming a gate of a transistor within a substrate having a surface and forming a buried oxide (BOX) layer within the substrate and adjacent to the gate at a first BOX layer face. The method also includes forming a raised source-drain channel (“fin”), where at least a portion of the fin extends from the surface of the substrate, and where the fin has a first fin face adjacent a second BOX layer face of the BOX layer.
摘要翻译：一种方法包括在具有表面的衬底内形成晶体管的栅极，并在衬底内形成掩埋氧化物（BOX）层，并在第一BOX层面与栅极相邻。该方法还包括形成凸起的源极 - 漏极通道（“鳍”），其中鳍的至少一部分从衬底的表面延伸，并且其中鳍具有邻近第二BOX层的第一鳍面 BOX层。

6. 发明申请

US20090294867A1 DUAL METAL GATES USING ONE METAL TO ALTER WORK FUNCTION OF ANOTHER METAL 失效
标题翻译：使用一种金属的双金属门可以改善其他金属的工作功能
公开(公告)号：US20090294867A1
公开(公告)日：2009-12-03
申请号：US12129984
申请日：2008-05-30
申请人： Byoung H. Lee , Sang Ho Bae , Kisik Choi , Rino Choi , Craig Huffman , Prashant Majhi , Jong Hoan Sim , Seung-Chul Song , Zhibo Zhang
发明人： Byoung H. Lee , Sang Ho Bae , Kisik Choi , Rino Choi , Craig Huffman , Prashant Majhi , Jong Hoan Sim , Seung-Chul Song , Zhibo Zhang
IPC分类号： H01L29/49 , H01L21/28
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/4966 , H01L29/517
摘要： Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process.
摘要翻译：公开了形成双金属栅极和形成的栅极的方法。一种方法可以包括在第一金属层上的栅极电介质层和第二金属（例如，PMOS金属）层上形成第一金属（例如，NMOS金属）层，由此第二金属层改变第一金属层（形成PMOS金属）。该方法可以移除第二金属层的一部分以暴露第一区域中的第一金属层; 在第一区域中的暴露的第一金属层上和在第二区域中的第二金属层上形成硅层; 并在第一和第二区域形成双金属栅极。由于栅极电介质层被第一金属连续覆盖，所以不会受到金属蚀刻工艺的损害。

7. 发明申请

US20060270224A1 Methods for forming metal-silicon layer using a silicon cap layer 审中-公开
标题翻译：使用硅帽层形成金属硅层的方法
公开(公告)号：US20060270224A1
公开(公告)日：2006-11-30
申请号：US11349737
申请日：2006-02-08
申请人： Seung-Chul Song , Byung Lee , Zhibo Zhang
发明人： Seung-Chul Song , Byung Lee , Zhibo Zhang
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L29/41783 , H01L29/665
摘要： Techniques for forming a layer of MetalxSiy without overly depleting the source/drain region of a silicon substrate are disclosed. In one respect, a cobalt layer is formed on a silicon-containing substrate. A metal layer is formed on the cobalt layer. A CoSi layer is formed through heating. Un-reacted cobalt and metal from the cobalt and metal layers are removed. A silicon cap layer is formed on the CoSi layer. A CoSi2 layer is then formed through heating, the CoSi2 layer being formed upward into the silicon cap layer.
摘要翻译：公开了用于形成金属层Si层的技术，而不会过度耗尽硅衬底的源极/漏极区域。在一个方面，在含硅基板上形成钴层。在钴层上形成金属层。通过加热形成CoSi层。从钴和金属层去除未反应的钴和金属。在CoSi层上形成硅覆盖层。然后通过加热形成CoSi 2层，将CoSi 2层向上形成硅帽层。

8. 发明申请

US20060145183A1 Method of manufacturing a semiconductor device having a photon absorption layer to prevent plasma damage 审中-公开
标题翻译：制造具有光子吸收层以防止等离子体损伤的半导体器件的方法
公开(公告)号：US20060145183A1
公开(公告)日：2006-07-06
申请号：US11367420
申请日：2006-03-06
申请人： Seung-Chul Song
发明人： Seung-Chul Song
IPC分类号： H01L33/00
CPC分类号： H01L21/76825 , H01L21/265 , H01L21/76832 , H01L21/76834 , H01L21/76837 , H01L29/6659 , H01L2924/0002 , H01L2924/00
摘要： A MOSFET device structure and a method of manufacturing the same, in which a photon absorption layer is formed over a gate structure and a substrate in order to avoid plasma induced damage to the gate oxide during high density plasma deposition of a interlayer dielectric layer. The device structure may include an etch stop layer below the photon absorption layer. The photon absorption layer is formed entirely of silicon germanium or it may be a multi-layer formed of a silicon layer and a silicon germanium layer. In the multi-layer structure the silicon germanium layer may be formed on top of the silicon layer or vice-versa. The silicon germanium layer may be formed by implanting germanium ions into a silicon layer or by an epitaxial growth of the silicon germanium alloy layer. In the photon absorption layer the germanium may be substituted by another element whose band gap energy is less than that of silicon.
摘要翻译： MOSFET器件结构及其制造方法，其中在栅极结构和衬底上形成光子吸收层，以便在层间电介质层的高密度等离子体沉积期间避免等离子体对栅极氧化物的损伤。器件结构可以包括在光子吸收层下面的蚀刻停止层。光子吸收层完全由硅锗形成，或者它可以是由硅层和硅锗层形成的多层。在多层结构中，硅锗层可以形成在硅层的顶部上，反之亦然。硅锗层可以通过将锗离子注入到硅层中或者通过硅锗合金层的外延生长来形成。在光子吸收层中，锗可以被带隙能量小于硅的另一元素取代。

9. 发明申请

US20140011340A1 Method of Forming a CMOS Device with a Stressed-Channel NMOS Transistor and a Strained-Channel PMOS Transistor 有权
标题翻译：用高压沟道NMOS晶体管和应变通道PMOS晶体管形成CMOS器件的方法
公开(公告)号：US20140011340A1
公开(公告)日：2014-01-09
申请号：US13541957
申请日：2012-07-05
申请人： Seung-Chul Song , Amitabh Jain , Deborah J. Riley
发明人： Seung-Chul Song , Amitabh Jain , Deborah J. Riley
IPC分类号： H01L21/20
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L27/092 , H01L29/6653 , H01L29/6656 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7847 , H01L29/7848
摘要： A method of forming stressed-channel NMOS transistors and strained-channel PMOS transistors forms p-type source and drain regions before an n-type source and drain dopant is implanted and a stress memorization layer is formed, thereby reducing the stress imparted to the n-channel of the PMOS transistors. In addition, a non-conductive layer is formed after the p-type source and drain regions are formed, but before the n-type dopant is implanted. The non-conductive layer allows shallower n-type implants to be realized, and also serves as a buffer layer for the stress memorization layer.
摘要翻译：形成应力通道NMOS晶体管和应变通道PMOS晶体管的方法在植入n型源极和漏极掺杂剂之前形成p型源极和漏极区，并且形成应力记忆层，由此减小施加到n - 沟道的PMOS晶体管。此外，在形成p型源极和漏极区之后，但在植入n型掺杂剂之前，形成非导电层。不导电层允许实现较浅的n型植入物，并且还用作应力记忆层的缓冲层。

10. 发明申请

US20120113708A1 Stable SRAM Bitcell Design Utilizing Independent Gate Finfet 有权
标题翻译：稳定的SRAM位单元设计采用独立的门极Finfet
公开(公告)号：US20120113708A1
公开(公告)日：2012-05-10
申请号：US12939260
申请日：2010-11-04
申请人： Seong-Ook Jung , Mingu Kang , Hyunkook Park , Seung-Chul Song , Mohamed Abu-Rahma , Beom-Mo Han , Lixin Ge , Zhongze Wang
发明人： Seong-Ook Jung , Mingu Kang , Hyunkook Park , Seung-Chul Song , Mohamed Abu-Rahma , Beom-Mo Han , Lixin Ge , Zhongze Wang
IPC分类号： G11C11/00 , H01R43/00
CPC分类号： G11C11/4125 , H01L27/1104 , Y10T29/49117
摘要： Stable SRAM cells utilizing Independent Gate FinFET architectures provide improvements over conventional SRAM cells in device parameters such as Read Static Noise Margin (RSNM) and Write Noise Margin (WNM). Exemplary SRAM cells comprise a pair of storage nodes, a pair of bit lines, a pair of pull-up devices, a pair of pull-down devices and a pair of pass-gate devices. A first control signal and a second control signal are configured to adjust drive strengths of the pass-gate devices, and a third control signal is configured to adjust drive strengths of the pull-up devices, wherein the first control signal is routed orthogonal to a bit line direction, and the second and third control signals are routed in a direction same as the bit line direction. RSNM and WNM are improved by adjusting drive strengths of the pull-up and pass-gate devices during read and write operations.
摘要翻译：利用独立栅极FinFET架构的稳定SRAM单元提供了诸如读静态噪声余量（RSNM）和写噪声余量（WNM）的器件参数中的常规SRAM单元的改进。示例性SRAM单元包括一对存储节点，一对位线，一对上拉器件，一对下拉器件和一对通栅器件。第一控制信号和第二控制信号被配置为调整传递门装置的驱动强度，并且第三控制信号被配置为调节上拉装置的驱动强度，其中第一控制信号被正交地传送到位线方向，并且第二和第三控制信号沿与位线方向相同的方向路由。通过在读写操作期间调整上拉和通过栅极器件的驱动强度，RSNM和WNM得到了改进。

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