专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07741168B2 Systems and methods for fabricating nanometric-scale semiconductor devices with dual-stress layers using double-stress oxide/nitride stacks 失效
标题翻译：使用双应力氧化物/氮化物叠层制造具有双应力层的纳米尺度半导体器件的系统和方法
公开(公告)号：US07741168B2
公开(公告)日：2010-06-22
申请号：US11782984
申请日：2007-07-25
申请人： Seung-Chul Song , Joel Barnett , Byong Sun Ju
发明人： Seung-Chul Song , Joel Barnett , Byong Sun Ju
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L29/7843
摘要： Systems and methods for fabricating semiconductor devices with dual-stress layers using double-stress oxide/nitride stacks. A method comprises providing NMOS and PMOS regions, selectively forming a dual-stack tensile stress layer over the NMOS region by depositing a tensile silicon nitride layer over the NMOS and PMOS regions, depositing a tensile silicon oxide layer over the tensile silicon nitride layer, removing a portion of the tensile silicon oxide layer from the PMOS region, and removing a portion of the tensile silicon nitride layer from the NMOS region and selectively forming a dual stack compressive stress layer over the PMOS region by depositing a compressive silicon nitride layer over the NMOS and PMOS regions, depositing a compressive silicon oxide layer over the compressive silicon nitride layer, removing a portion of the compressive silicon oxide layer from the NMOS region, and removing a portion of the compressive silicon nitride layer from the NMOS region.
摘要翻译：使用双应力氧化物/氮化物叠层制造具有双应力层的半导体器件的系统和方法。一种方法包括提供NMOS和PMOS区域，通过在NMOS和PMOS区域上沉积拉伸氮化硅层，在拉伸氮化硅层上方沉积拉伸氧化硅层，去除来自所述PMOS区的所述拉伸氧化硅层的一部分，以及从所述NMOS区域去除所述拉伸氮化硅层的一部分，并且在所述PMOS区上选择性地形成双层压应力层，通过在所述NMOS上沉积压缩氮化硅层和PMOS区域，在所述压缩氮化硅层上沉积压缩氧化硅层，从所述NMOS区域去除所述压缩氧化硅层的一部分，以及从所述NMOS区域移除所述压缩氮化硅层的一部分。

2. 发明申请

US20090026548A1 Systems And Methods For Fabricating Nanometric-Scale Semiconductor Devices With Dual-Stress Layers Using Double-Stress Oxide/Nitride Stacks 失效
标题翻译：使用双应力氧化物/氮化物叠层制造具有双应力层的纳米尺度半导体器件的系统和方法
公开(公告)号：US20090026548A1
公开(公告)日：2009-01-29
申请号：US11782984
申请日：2007-07-25
申请人： Seung-Chul Song , Joel Barnett , Byong Sun Ju
发明人： Seung-Chul Song , Joel Barnett , Byong Sun Ju
IPC分类号： H01L21/31 , H01L29/78
CPC分类号： H01L21/823807 , H01L29/7843
摘要： Systems and methods for fabricating semiconductor devices with dual-stress layers using double-stress oxide/nitride stacks. A method comprises providing NMOS and PMOS regions, selectively forming a dual-stack tensile stress layer over the NMOS region by depositing a tensile silicon nitride layer over the NMOS and PMOS regions, depositing a tensile silicon oxide layer over the tensile silicon nitride layer, removing a portion of the tensile silicon oxide layer from the PMOS region, and removing a portion of the tensile silicon nitride layer from the NMOS region and selectively forming a dual stack compressive stress layer over the PMOS region by depositing a compressive silicon nitride layer over the NMOS and PMOS regions, depositing a compressive silicon oxide layer over the compressive silicon nitride layer, removing a portion of the compressive silicon oxide layer from the NMOS region, and removing a portion of the compressive silicon nitride layer from the NMOS region.
摘要翻译：使用双应力氧化物/氮化物叠层制造具有双应力层的半导体器件的系统和方法。一种方法包括提供NMOS和PMOS区域，通过在NMOS和PMOS区域上沉积拉伸氮化硅层，在拉伸氮化硅层上方沉积拉伸氧化硅层，去除来自所述PMOS区的所述拉伸氧化硅层的一部分，以及从所述NMOS区域去除所述拉伸氮化硅层的一部分，并且在所述PMOS区上选择性地形成双层压应力层，通过在所述NMOS上沉积压缩氮化硅层和PMOS区域，在所述压缩氮化硅层上沉积压缩氧化硅层，从所述NMOS区域去除所述压缩氧化硅层的一部分，以及从所述NMOS区域移除所述压缩氮化硅层的一部分。

3. 发明申请

US20070059874A1 Dual Metal Gate and Method of Manufacture 审中-公开
标题翻译：双金属门和制造方法
公开(公告)号：US20070059874A1
公开(公告)日：2007-03-15
申请号：US11456054
申请日：2006-07-06
申请人： Naim Moumen , Husam Alshareef , Joel Barnett , Muhammad Hussain , Hongfa Luan , Seung-Chul Song , Raj Jammy
发明人： Naim Moumen , Husam Alshareef , Joel Barnett , Muhammad Hussain , Hongfa Luan , Seung-Chul Song , Raj Jammy
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： Methods for fabricating two metal gate stacks for complementary metal oxide semiconductor (CMOS) devices are provided. A common layer, such as a metal layer, a metal alloy layer, or a metal nitride layer may be deposited on to a gate dielectric. A first mask layer may be deposited and patterned over an active region, exposing a portion of the common layer. A first ion may be deposited in the common layer forming a first mask layer. Similarly, a second mask layer may be deposited and patterned over the other active region and the first metal layer, and another portion of the common layer is exposed. A second ion may be deposited in the common layer, forming a second mask layer.
摘要翻译：提供了用于制造用于互补金属氧化物半导体（CMOS）器件的两个金属栅极叠层的方法。诸如金属层，金属合金层或金属氮化物层的公共层可以沉积到栅极电介质上。可以在有源区上沉积和图案化第一掩模层，暴露公共层的一部分。可以在形成第一掩模层的公共层中沉积第一离子。类似地，第二掩模层可以在另一个有源区和第一金属层上沉积和图案化，并且公共层的另一部分被暴露。可以在公共层中沉积第二离子，形成第二掩模层。

4. 发明申请

US20070048920A1 Methods for dual metal gate CMOS integration 审中-公开
标题翻译：双金属栅极CMOS集成方法
公开(公告)号：US20070048920A1
公开(公告)日：2007-03-01
申请号：US11212127
申请日：2005-08-25
申请人： Seung-Chul Song , Zhibo Zhang , Byoung Lee , Naim Moumen , Joel Barnett , Muhammad Hussain , Rino Choi , Husam Alshareef
发明人： Seung-Chul Song , Zhibo Zhang , Byoung Lee , Naim Moumen , Joel Barnett , Muhammad Hussain , Rino Choi , Husam Alshareef
IPC分类号： H01L21/8238 , H01L21/8234 , H01L21/4763 , H01L21/3205
CPC分类号： H01L21/823842
摘要： Methods for fabricating two metal gate stacks for complementary metal oxide semiconductor (CMOS) devices are provided. A first metal layer may be deposited onto a gate dielectric. Next a mask layer may be deposited on the first metal layer and subsequently etch. The first metal layer is then etched. Without removing the mask layer, a second metal layer may be deposited. In one embodiment, the mask layer is a second metal layer. In other embodiments, the mask layer is a silicon layer. Subsequent fabrication steps include depositing another metal layer (e.g., another PMOS metal layer), depositing a cap, etching the cap to define gate stacks, and simultaneously etching the first and second gate region having a similar thickness with differing metal layers.
摘要翻译：提供了用于制造用于互补金属氧化物半导体（CMOS）器件的两个金属栅极叠层的方法。可以将第一金属层沉积到栅极电介质上。接下来，掩模层可以沉积在第一金属层上并随后蚀刻。然后蚀刻第一金属层。在不去除掩模层的情况下，可沉积第二金属层。在一个实施例中，掩模层是第二金属层。在其他实施例中，掩模层是硅层。随后的制造步骤包括沉积另一金属层（例如，另一个PMOS金属层），沉积帽，蚀刻帽以限定栅极堆叠，以及同时用不同的金属层蚀刻具有相似厚度的第一和第二栅极区域。

5. 发明申请

US20110298090A1 Capacitors, Systems, and Methods 失效
标题翻译：电容器，系统和方法
公开(公告)号：US20110298090A1
公开(公告)日：2011-12-08
申请号：US12794251
申请日：2010-06-04
申请人： Chanro Park , Sangduk Park , Paul D. Kirsch , David Gilmer , Chang Yong Kang , Joel Barnett
发明人： Chanro Park , Sangduk Park , Paul D. Kirsch , David Gilmer , Chang Yong Kang , Joel Barnett
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/40 , H01L28/65
摘要： Capacitors, systems, and methods are disclosed. In one embodiment, the capacitor includes a first electrode. The capacitor may also include a first insulator layer having a positive VCC adjacent to the first electrode. The capacitor may further include a second insulator layer having a negative VCC adjacent to the first insulator layer. The capacitor may also include a third insulator layer having a positive VCC adjacent to the second insulator layer. The capacitor may also include a second electrode adjacent to the third insulator layer.
摘要翻译：公开了电容器，系统和方法。在一个实施例中，电容器包括第一电极。电容器还可以包括具有与第一电极相邻的正VCC的第一绝缘体层。电容器还可以包括具有与第一绝缘体层相邻的负VCC的第二绝缘体层。电容器还可以包括具有与第二绝缘体层相邻的正VCC的第三绝缘体层。电容器还可以包括与第三绝缘体层相邻的第二电极。

6. 发明授权

US08432020B2 Capacitors, systems, and methods 失效
标题翻译：电容器，系统和方法
公开(公告)号：US08432020B2
公开(公告)日：2013-04-30
申请号：US12794251
申请日：2010-06-04
申请人： Chanro Park , Sangduk Park , Paul D. Kirsch , David Gilmer , Chang Yong Kang , Joel Barnett
发明人： Chanro Park , Sangduk Park , Paul D. Kirsch , David Gilmer , Chang Yong Kang , Joel Barnett
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/40 , H01L28/65
摘要： Capacitors, systems, and methods are disclosed. In one embodiment, the capacitor includes a first electrode. The capacitor may also include a first insulator layer having a positive VCC adjacent to the first electrode. The capacitor may further include a second insulator layer having a negative VCC adjacent to the first insulator layer. The capacitor may also include a third insulator layer having a positive VCC adjacent to the second insulator layer. The capacitor may also include a second electrode adjacent to the third insulator layer.
摘要翻译：公开了电容器，系统和方法。在一个实施例中，电容器包括第一电极。电容器还可以包括具有与第一电极相邻的正VCC的第一绝缘体层。电容器还可以包括具有邻近第一绝缘体层的负VCC的第二绝缘体层。电容器还可以包括具有与第二绝缘体层相邻的正VCC的第三绝缘体层。电容器还可以包括与第三绝缘体层相邻的第二电极。

7. 发明申请

US20060115937A1 Devices for an insulated dielectric interface between high-k material and silicon 审中-公开
标题翻译：高k材料和硅之间绝缘电介质界面的器件
公开(公告)号：US20060115937A1
公开(公告)日：2006-06-01
申请号：US11324934
申请日：2006-01-04
申请人： Joel Barnett , Mark Gardner , Naim Moumen , Jim Gutt
发明人： Joel Barnett , Mark Gardner , Naim Moumen , Jim Gutt
IPC分类号： H01L21/84 , H01L21/31 , H01L21/302
CPC分类号： H01L21/02337 , H01L21/02142 , H01L21/02148 , H01L21/02175 , H01L21/022 , H01L21/02238 , H01L21/28185 , H01L21/28194 , H01L21/31116 , H01L21/3144 , H01L21/31662 , H01L21/31691 , H01L29/513 , H01L29/517 , H01L29/6659
摘要： Methods and devices are described for an insulated dielectric interface between a high-k material and silicon for improving electrical characteristics of devices. A method includes forming an oxide layer on a silicon substrate using an in situ steam generation process, etching the oxide layer to form a reduced thickness oxide layer of less than 10 Angstroms, and annealing the reduced thickness oxide layer with ammonia. A semiconductor wafer comprises a silicon substrate, an oxide layer coupled to the silicon substrate where the oxide layer having a thickness of less than 10 Angstroms, and a high-k dielectric material deposited onto the oxide layer.
摘要翻译：描述了用于高k材料和硅之间的绝缘电介质界面的方法和装置，以改善器件的电特性。一种方法包括使用原位蒸汽产生工艺在硅衬底上形成氧化物层，蚀刻氧化物层以形成小于10埃的厚度减小的氧化物层，并且用氨将还原厚度的氧化物层退火。半导体晶片包括硅衬底，耦合到硅衬底的氧化物层，其中氧化物层具有小于10埃的厚度，以及沉积在氧化物层上的高k电介质材料。

8. 发明申请

US20050070120A1 Methods and devices for an insulated dielectric interface between high-k material and silicon 审中-公开
标题翻译：高k材料与硅之间绝缘电介质界面的方法和装置
公开(公告)号：US20050070120A1
公开(公告)日：2005-03-31
申请号：US10911981
申请日：2004-08-05
申请人： Joel Barnett , Mark Gardner , Naim Moumen , Jim Gutt
发明人： Joel Barnett , Mark Gardner , Naim Moumen , Jim Gutt
IPC分类号： H01L21/28 , H01L21/311 , H01L21/314 , H01L21/316 , H01L21/336 , H01L21/8242 , H01L29/51
CPC分类号： H01L21/02337 , H01L21/02142 , H01L21/02148 , H01L21/02175 , H01L21/022 , H01L21/02238 , H01L21/28185 , H01L21/28194 , H01L21/31116 , H01L21/3144 , H01L21/31662 , H01L21/31691 , H01L29/513 , H01L29/517 , H01L29/6659
摘要： Methods and devices are described for an insulated dielectric interface between a high-k material and silicon for improving electrical characteristics of devices. A method includes forming an oxide layer on a silicon substrate using an in situ steam generation process, etching the oxide layer to form a reduced thickness oxide layer of less than 10 Angstroms, and annealing the reduced thickness oxide layer with ammonia. A semiconductor wafer comprises a silicon substrate, an oxide layer coupled to the silicon substrate where the oxide layer having a thickness of less than 10 Angstroms, and a high-k dielectric material deposited onto the oxide layer.
摘要翻译：描述了用于高k材料和硅之间的绝缘电介质界面的方法和装置，以改善器件的电特性。一种方法包括使用原位蒸汽产生工艺在硅衬底上形成氧化物层，蚀刻氧化物层以形成小于10埃的厚度减小的氧化物层，并且用氨将还原厚度的氧化物层退火。半导体晶片包括硅衬底，耦合到硅衬底的氧化物层，其中氧化物层具有小于10埃的厚度，以及沉积在氧化物层上的高k电介质材料。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式