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1. 发明授权

US07257163B2 Method and system for reducing inter-symbol interference effects in transmission over a serial link with mapping of each word in a cluster of received words to a single transmitted word 有权
标题翻译：用于通过串行链路传输中减少符号间干扰效应的方法和系统，其中接收到的字组中的每个字映射到单个发送字
公开(公告)号：US07257163B2
公开(公告)日：2007-08-14
申请号：US10095422
申请日：2002-03-12
申请人： Seung Ho Hwang , Jano Banks , Paul Daniel Wolf , Eric Lee , William Sheet , Albert M. Scalise
发明人： Seung Ho Hwang , Jano Banks , Paul Daniel Wolf , Eric Lee , William Sheet , Albert M. Scalise
IPC分类号： H04B14/04
CPC分类号： H04L1/0041 , G09G5/006 , H04L1/0057 , H04L1/007 , H04L1/203 , H04L1/206 , H04L25/49 , H04L25/4915 , H04N11/042 , H04N19/89
摘要： A system in which encoded data (e.g., encoded video and auxiliary data) are transmitted over a serial link. Other aspects of the invention are transmitters for use in encoding data for transmission over a serial link, receivers for receiving such data, and methods for sending encoded data over a serial link. Source data to be transmitted are encoded using a subset of a full set of code words. The subset consists of preferred code words. Disjoint clusters of code words in the full set are predetermined. Each cluster includes one or more of the preferred words, and optionally also at least one additional code word that is similar to a preferred word of the cluster in the sense that it is likely to be generated as a result of probable bit errors in transmission, or transmission and decoding, of such preferred word. Each preferred word of a cluster is indicative of a single source data value. Each received code word in a cluster is mapped to the source data value determined by each preferred word of the cluster.
摘要翻译：编码数据（例如编码视频和辅助数据）通过串行链路发送的系统。本发明的其他方面是用于编码用于通过串行链路传输的数据的发射机，用于接收这种数据的接收机以及通过串行链路发送编码数据的方法。要发送的源数据使用全套码字的子集进行编码。该子集由优选的代码字组成。完整集合中的不一致的码字群被预先确定。每个群集包括一个或多个优选单词，以及可选地还有至少一个附加代码字，其类似于群集的优选单词，其意图是可能由于传输中可能的比特错误而产生，或传输和解码。簇的每个优选单词表示单个源数据值。集群中的每个接收的码字被映射到由集群的每个优选字确定的源数据值。

2. 发明授权

US07359437B2 Encoding method and system for reducing inter-symbol interference effects in transmission over a serial link 有权
公开(公告)号：US07359437B2
公开(公告)日：2008-04-15
申请号：US10036234
申请日：2001-12-24
申请人： Seung Ho Hwang , Jano Banks , Paul Daniel Wolf , Eric Lee , Baegin Sung , Albert M. Scalise
发明人： Seung Ho Hwang , Jano Banks , Paul Daniel Wolf , Eric Lee , Baegin Sung , Albert M. Scalise
IPC分类号： H04B1/66
CPC分类号： H04L1/0057 , G09G5/006 , H04L1/203 , H04L1/206 , H04L25/49 , H04N19/89
摘要： A communication system including a transmitter, a receiver, and a serial link, in which encoded data (e.g., encoded video data and encoded auxiliary data) are transmitted from the transmitter to the receiver. The serial link can but need not be a TMDS or TMDS-like link. In typical embodiments, alternating bursts of encoded video data and encoded auxiliary data are transmitted over each of one or more channels of the link. Other aspects of the invention are transmitters for use in encoding data for transmission over a serial link, and methods for sending encoded data over a serial link. In accordance with the invention, the data to be transmitted are encoded using a subset (sometimes referred to as a selected set of code words) of a full set of code words. The selected set of code words is selected such that each stream of encoded data (comprising only such code words) transmitted over a serial link has a bit pattern that is less susceptible to inter-symbol interference (“ISI”) during transmission than is the bit pattern determined by a conventionally encoded version of the same data (comprising not only the selected set of code words but also other members of the full set). In general, the best choice for the selected set of code words selected from a full set of binary code words depends on the particular coding implemented by the full set. Typically, the selected set of code words includes words whose serial patterns (during transmission) have fewer contiguous zeros and ones (and thus are less susceptible to ISI during transmission) than do those code words in the full set that are not selected. In preferred embodiments in which the bits of the selected set of code words are transmitted over a serial link as sequences of rising and falling voltage transitions, the bit pattern of each transmitted stream of the selected set of code words implements DC balancing to limit the voltage drift over time.

3. 发明授权

US07088398B1 Method and apparatus for regenerating a clock for auxiliary data transmitted over a serial link with video data 有权
标题翻译：用于再生通过串行链路与视频数据传输的辅助数据的时钟的方法和装置
公开(公告)号：US07088398B1
公开(公告)日：2006-08-08
申请号：US10171860
申请日：2002-06-14
申请人： Paul Daniel Wolf , Adrian Sfarti , John D. Banks , Stephen J. Keating , Duane Siemens , Eric Lee , Albert M. Scalise , Gijung Ahn , Seung Ho Hwang , Keewook Jung
发明人： Paul Daniel Wolf , Adrian Sfarti , John D. Banks , Stephen J. Keating , Duane Siemens , Eric Lee , Albert M. Scalise , Gijung Ahn , Seung Ho Hwang , Keewook Jung
IPC分类号： H04N7/08 , H04N7/12 , H04N7/52
CPC分类号： H04L1/0057 , G09G5/006 , H04L1/203 , H04L1/206 , H04L25/49 , H04N5/126 , H04N5/4401 , H04N19/89 , H04N21/233 , H04N21/23602 , H04N21/2368 , H04N21/2383 , H04N21/242 , H04N21/4341 , H04N21/4342
摘要： A communication system including a transmitter, a receiver, and a serial link, in which encoded data (e.g., video, audio, and optionally also other auxiliary data) are transmitted from the transmitter to the receiver. The serial link can but need not be a TMDS or TMDS-like link. In typical embodiments, packets of encoded audio data are transmitted over each of one or more channels of the link during data islands between bursts of encoded video data, a pixel clock is transmitted over the link, and the receiver regenerates a clock for the audio data using time code data in the packets and the pixel clock. Other aspects of the invention are transmitters for transmitting encoded data and a pixel clock over a serial link, receivers for receiving such data and pixel clock and performing audio clock regeneration, and methods for transmitting encoded data and a pixel clock over a serial link and performing clock regeneration using the transmitted data and pixel clock.
摘要翻译：包括发射机，接收机和串行链路的通信系统，其中编码数据（例如，视频，音频，以及可选地还有其他辅助数据）从发射机发射到接收机。串行链接可以但不一定是TMDS或类似TMDS的链接。在典型实施例中，编码音频数据的分组在编码视频数据的脉冲串之间的数据岛期间在链路的一个或多个信道中的每一个上传输，像素时钟通过链路发送，并且接收机重新生成音频数据的时钟使用分组中的时间码数据和像素时钟。本发明的其他方面是用于通过串行链路发射编码数据和像素时钟的发射机，用于接收这种数据和像素时钟并执行音频时钟再生的接收机，以及用于通过串行链路传输编码数据和像素时钟的方法，并执行使用发送的数据和像素时钟进行时钟再生。

4. 发明授权

US06914637B1 Method and system for video and auxiliary data transmission over a serial link 有权
标题翻译：通过串行链路传输视频和辅助数据的方法和系统
公开(公告)号：US06914637B1
公开(公告)日：2005-07-05
申请号：US10192296
申请日：2002-07-10
申请人： Paul Daniel Wolf , John D. Banks , Stephen J. Keating , Duane Siemens , Eric Lee , Albert M. Scalise , Gijung Ahn , Seung Ho Hwang , Keewook Jung , James D. Lyle , Michael Anthony Schumacher , Vladimir Grekhov
发明人： Paul Daniel Wolf , John D. Banks , Stephen J. Keating , Duane Siemens , Eric Lee , Albert M. Scalise , Gijung Ahn , Seung Ho Hwang , Keewook Jung , James D. Lyle , Michael Anthony Schumacher , Vladimir Grekhov
IPC分类号： H04N7/04 , G09G5/00 , H04J3/00 , H04L1/00 , H04L1/20 , H04L25/49 , H04N5/12 , H04N7/045 , H04N19/89 , H04N21/233 , H04N21/236 , H04N21/2368 , H04N21/2383 , H04N21/242 , H04N21/434 , H04N7/52
CPC分类号： H04L1/0057 , G09G5/006 , H04L1/203 , H04L1/206 , H04L25/49 , H04N5/126 , H04N5/4401 , H04N19/89 , H04N21/233 , H04N21/23602 , H04N21/2368 , H04N21/2383 , H04N21/242 , H04N21/4341 , H04N21/4342
摘要： A communication system including a transmitter, a receiver, and a serial link, in which encoded data (e.g., video, audio, and optionally also other auxiliary data) are transmitted from the transmitter to the receiver. The serial link can but need not be a TMDS or TMDS-like link. In typical embodiments, packets of encoded audio data are transmitted over each of one or more channels of the link during data islands between bursts of encoded video data. Other aspects of the invention are transmitters for use in encoding data for transmission over a serial link, receivers for receiving such data, and methods for sending encoded data over a serial link.
摘要翻译：包括发射机，接收机和串行链路的通信系统，其中编码数据（例如，视频，音频，以及可选地还有其他辅助数据）从发射机发射到接收机。串行链接可以但不一定是TMDS或类似TMDS的链接。在典型的实施例中，编码的音频数据的分组在编码的视频数据的脉冲之间的数据岛期间，通过链路的一个或多个信道中的每一个传送。本发明的其他方面是用于编码用于通过串行链路传输的数据的发射机，用于接收这种数据的接收机以及通过串行链路发送编码数据的方法。

5. 发明授权

US5191653A IO adapter for system and IO buses having different protocols and speeds 失效
标题翻译：适用于具有不同协议和速度的系统和IO总线的IO适配器
公开(公告)号：US5191653A
公开(公告)日：1993-03-02
申请号：US635923
申请日：1990-12-28
申请人： John D. (J.) Banks , Kenneth M. Karakotsios , Albert M. Scalise
发明人： John D. (J.) Banks , Kenneth M. Karakotsios , Albert M. Scalise
IPC分类号： G06F13/40
CPC分类号： G06F13/4027
摘要： A bi-directional bus adapter coupling a system bus, which operates at a first speed using a first protocol, and an IO bus, which operates at a second speed using a second protocol, and allowing data transfering devices on either bus to transfer data to or from devices on the other bus. The bus adapter includes a cycle generation mechanism which is responsive to data cycles from one of the buses in order to generate bus cycles needed to complete a data transfer to a device on the other bus. The bus adapter includes a synchronization mechanism for converting the plurality of data cycles generated by the cycle generation mechanism from either the first speed to the second speed or vice versa. The bus adapter includes bi-directional data path mechanism for routing data between the system and IO buses according to said protocols, such that the data path directs bytes of data to specific data lines to perform byte steering and dynamic bus sizing on the data from the system bus to the IO bus. The bus adapter also includes a bi-directional address transceiver mechanism for routing addresses between said system and said IO buses.
摘要翻译：耦合使用第一协议以第一速度操作的系统总线的双向总线适配器和使用第二协议以第二速度操作的IO总线，并允许任一总线上的数据传输设备将数据传输到或从另一条总线上的设备。总线适配器包括循环生成机构，其响应于来自总线之一的数据周期，以便产生完成对另一总线上的设备的数据传输所需的总线周期。总线适配器包括一个同步机构，用于将由循环发生机制产生的多个数据循环从第一速度转换到第二速度，反之亦然。总线适配器包括用于根据所述协议在系统和IO总线之间路由数据的双向数据路径机制，使得数据路径将数据字节指向特定的数据线，以对数据进行字节转向和动态总线大小调整系统总线到IO总线。总线适配器还包括用于在所述系统和所述IO总线之间路由地址的双向地址收发机机构。

6. 发明授权

US06393505B1 Methods and apparatus for data bus arbitration 有权
标题翻译：数据总线仲裁的方法和装置
公开(公告)号：US06393505B1
公开(公告)日：2002-05-21
申请号：US09227502
申请日：1999-01-06
申请人： Albert M. Scalise , Jano D. Banks
发明人： Albert M. Scalise , Jano D. Banks
IPC分类号： G06F1300
CPC分类号： G06F13/161 , G06F13/364
摘要： A data bus arbitration system is disclosed including a bus status monitor which is coupled to a data bus and generates a bus status signal for use by an arbiter. The arbiter is coupled to a number of requesters, each of which belongs to a distinct class of requesters. The arbiter arbitrates between multiple requests using heuristics dependent upon the classes of the requesters. The nature of one class of requestors is that the requestors have real time requirements which must be met in order to maintain data integrity within the system. The nature of a second class of requestors is such that the requestors have semi-real time requirements which must be met in order to maintain data integrity within the system. The nature of the system is such that the available bandwidth must be utilized very efficiently in order to maintain data integrity within the system. The arbiter system disclosed grants access to the requesters using the heuristics disclosed while maintaining an efficiency of at least 80% of the total bandwidth for all requestors.
摘要翻译：公开了一种数据总线仲裁系统，其包括耦合到数据总线的总线状态监视器，并产生总线状态信号供仲裁器使用。仲裁器耦合到一些请求者，每个请求者属于不同类别的请求者。仲裁者根据请求者的类别使用启发式方式在多个请求之间进行仲裁。一类请求者的性质是请求者具有必须满足的实时要求，以便保持系统内的数据完整性。第二类请求者的性质使得请求者具有必须满足的半实时要求，以便保持系统内的数据完整性。系统的性质使得必须非常有效地利用可用的带宽，以便保持系统内的数据完整性。所公开的仲裁系统使用所公开的启发式方式来访问请求者，同时保持所有请求者的总带宽的至少80％的效率。

7. 发明授权

US5253348A Method of arbitration for buses operating at different speeds 失效
标题翻译：以不同速度运行的公共汽车的仲裁方法
公开(公告)号：US5253348A
公开(公告)日：1993-10-12
申请号：US951937
申请日：1992-09-25
申请人： Albert M. Scalise
发明人： Albert M. Scalise
IPC分类号： G06F13/366 , G06F13/40 , G06F13/364
CPC分类号： G06F13/366 , G06F13/4031
摘要： In a bus adapter coupling a system bus and an I/O bus which operate at different speeds and contain a plurality of devices, a method by which an arbiter in the bus adapter prevents contention for ownership of both buses by a device on either of the buses. The method includes the steps of sampling each of the devices requesting ownership of said buses and asserting a bus grant to one of the devices on one of the buses based on its assigned priority number. The method also includes the step of waiting for the device granted the bus to send an acknowledge signal to display ownership of the buses and for each of the devices not on the bus containing the device granted the bus to see the acknowledge signal before resampling and reasserting a new bus grant to another of the requesting devices.
摘要翻译：在总线适配器中，耦合系统总线和以不同速度操作并包含多个设备的I / O总线，总线适配器中的仲裁器通过该总线适配器阻止两个总线的所有权的争用，巴士该方法包括以下步骤：对请求所有总线的所有设备的每个设备进行采样，并且基于其分配的优先级号，向其中一条总线上的设备之一断言总线授权。该方法还包括等待授予总线的设备发送确认信号以显示总线的所有权的步骤，并且对于不包括授予总线的设备的总线上的每个设备，在重新采样和重新取样之前看到确认信号另一个请求设备的新总线授权。

8. 发明授权

US06385692B2 Methods and apparatus for variable length SDRAM transfers 有权
标题翻译：用于可变长度SDRAM传输的方法和装置
公开(公告)号：US06385692B2
公开(公告)日：2002-05-07
申请号：US09805588
申请日：2001-03-12
申请人： Jano D. Banks , Dale R. Adams , Albert M. Scalise
发明人： Jano D. Banks , Dale R. Adams , Albert M. Scalise
IPC分类号： G06F1200
CPC分类号： G06F13/1647 , G11C7/1072 , G11C2207/2281 , G11C2207/229
摘要： Disclosed is a SDRAM system including a SDRAM having multiple banks of memory, a plurality of bank state machines associated the multiple banks of memory of the SDRAM, and a data control state machine. The data state machine is responsive to a memory request for a variable length data transfer with the SDRAM and as well as the bank state machines. The data control state machine determines the current state of a first bank of memory of the SDRAM. The current state may be either a read in progress, a write in progress, or idle. The data control state machine then handles the memory request with a different bank of memory RAM depending upon the current state of the first bank of memory.
摘要翻译：公开了一种SDRAM系统，包括具有多组存储器的SDRAM，与SDRAM的多组存储器相关联的多个存储体状态机以及数据控制状态机。数据状态机响应于与SDRAM以及银行状态机的可变长度数据传输的存储器请求。数据控制状态机确定SDRAM的第一存储体的当前状态。当前状态可能是正在读取，正在进行中或空闲。然后，数据控制状态机根据第一存储器组的当前状态来处理具有不同存储器RAM组的存储器请求。

9. 发明授权

US09640067B1 Determining commands on a media device interface 有权
公开(公告)号：US09640067B1
公开(公告)日：2017-05-02
申请号：US13602794
申请日：2012-09-04
申请人： Albert M. Scalise , Jano D. Banks , Andrew S. Brenner , Christopher D. Painter
发明人： Albert M. Scalise , Jano D. Banks , Andrew S. Brenner , Christopher D. Painter
IPC分类号： G08C19/00
CPC分类号： G08C19/00 , G08C17/02 , G08C2201/20 , G08C2201/21
摘要： Described herein are systems and methods for a media controller configured to associate data from a media device received using a media device interface with actions on the media devices. The associated data and actions may be used to build a media device interface command map. The media device interface command map may be used by the media controller to control the media device. A user interface provided by the media controller may thus be used to control disparate devices, allowing for a coordinated and consistent user experience across multiple media devices, even when they are from different manufacturers.

10. 发明授权

US06219747B1 Methods and apparatus for variable length SDRAM transfers 有权
标题翻译：用于可变长度SDRAM传输的方法和装置
公开(公告)号：US06219747B1
公开(公告)日：2001-04-17
申请号：US09226776
申请日：1999-01-06
申请人： Jano D. Banks , Dale R. Adams , Albert M. Scalise
发明人： Jano D. Banks , Dale R. Adams , Albert M. Scalise
IPC分类号： G06F1200
CPC分类号： G06F13/1647 , G11C7/1072 , G11C2207/2281 , G11C2207/229
摘要： Disclosed is a SDRAM system including a SDRAM having multiple banks of memory, a plurality of bank state machines associated the multiple banks of memory of the SDRAM, and a data control state machine. The data state machine is responsive to a memory request for a variable length data transfer with the SDRAM and as well as the bank state machines. The data control state machine determines the current state of a first bank of memory of the SDRAM. The current state may be either a read in progress, a write in progress, or idle. The data control state machine then handles the memory request with a different bank of memory RAM depending upon the current state of the first bank of memory.
摘要翻译：公开了一种SDRAM系统，包括具有多组存储器的SDRAM，与SDRAM的多组存储器相关联的多个存储体状态机以及数据控制状态机。数据状态机响应于与SDRAM以及银行状态机的可变长度数据传输的存储器请求。数据控制状态机确定SDRAM的第一存储体的当前状态。当前状态可能是正在读取，正在进行中或空闲。然后，数据控制状态机根据第一存储器组的当前状态来处理具有不同存储器RAM组的存储器请求。

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