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1. 发明授权

US08625110B2 Methods of inspecting structures 有权
标题翻译：检查结构的方法
公开(公告)号：US08625110B2
公开(公告)日：2014-01-07
申请号：US12662079
申请日：2010-03-30
申请人： Seouk-Hoon Woo , Jeong-Ho Yeo , Byeong-Ok Cho , Joo-On Park , Chang-Min Park , Won-Sun Kim
发明人： Seouk-Hoon Woo , Jeong-Ho Yeo , Byeong-Ok Cho , Joo-On Park , Chang-Min Park , Won-Sun Kim
IPC分类号： G01B11/28
CPC分类号： G01B11/06 , G01B11/02 , G01B11/24 , G01B2210/56 , G01N21/956 , G01N2021/95615 , G03F7/70625
摘要： A method of inspecting a structure. The method includes preparing preliminary spectrums of reference diffraction intensities according to critical dimensions of reference structures, obtaining a linear spectrum from the preliminary spectrums in a set critical dimension range, radiating light to respective measurement structures formed on a substrate, measuring measurement diffraction intensities of the light diffracted by the measurement structures, and obtaining respective critical dimensions of the measurement structures from the measurement diffraction intensities using the linear spectrum.
摘要翻译：检查结构的方法。该方法包括根据参考结构的临界尺寸准备参考衍射强度的初步光谱，从设定的临界尺寸范围内的初步光谱获得线性光谱，将光照射到形成在基板上的各个测量结构，测量测量衍射强度由测量结构衍射的光，并且使用线性光谱从测量衍射强度获得测量结构的临界尺寸。

2. 发明申请

US20110007329A1 Methods of inspecting structures 有权
标题翻译：检查结构的方法
公开(公告)号：US20110007329A1
公开(公告)日：2011-01-13
申请号：US12662079
申请日：2010-03-30
申请人： Seouk-Hoon Woo , Jeong-Ho Yeo , Byeong-Ok Cho , Joo-On Park , Chang-Min Park , Won-Sun Kim
发明人： Seouk-Hoon Woo , Jeong-Ho Yeo , Byeong-Ok Cho , Joo-On Park , Chang-Min Park , Won-Sun Kim
IPC分类号： G01B11/06 , G01B11/14
CPC分类号： G01B11/06 , G01B11/02 , G01B11/24 , G01B2210/56 , G01N21/956 , G01N2021/95615 , G03F7/70625
摘要： A method of inspecting a structure. The method includes preparing preliminary spectrums of reference diffraction intensities according to critical dimensions of reference structures, obtaining a linear spectrum from the preliminary spectrums in a set critical dimension range, radiating light to respective measurement structures formed on a substrate, measuring measurement diffraction intensities of the light diffracted by the measurement structures, and obtaining respective critical dimensions of the measurement structures from the measurement diffraction intensities using the linear spectrum.
摘要翻译：检查结构的方法。该方法包括根据参考结构的临界尺寸准备参考衍射强度的初步光谱，从设定的临界尺寸范围内的初步光谱获得线性光谱，将光照射到形成在基板上的各个测量结构，测量测量衍射强度由测量结构衍射的光，并且使用线性光谱从测量衍射强度获得测量结构的临界尺寸。

3. 发明申请

US20110263081A1 METHODS OF MANUFACTURING CMOS TRANSISTOR 有权
标题翻译：制造CMOS晶体管的方法
公开(公告)号：US20110263081A1
公开(公告)日：2011-10-27
申请号：US13173670
申请日：2011-06-30
申请人： Sang-Hun Jeon , Moon-Sook Lee , Byeong-Ok Cho
发明人： Sang-Hun Jeon , Moon-Sook Lee , Byeong-Ok Cho
IPC分类号： H01L21/336
CPC分类号： H01L27/124 , B82Y10/00 , H01L27/095 , H01L27/1214 , H01L27/1222 , H01L27/1225 , H01L27/1251 , H01L29/0665 , H01L29/0673 , H01L29/45 , H01L29/7839 , H01L29/78681 , H01L29/7869
摘要： A method of manufacturing a CMOS transistor can be provided by forming first and second gate electrodes on a substrate and forming a gate insulation layer on the first and second gate electrodes. A semiconductor channel material having a first conductivity type can be formed on the gate insulation layer. A pair of ohmic contacts can be formed on the semiconductor channel material such that the ohmic contacts cross over both side portions of the first gate electrode, respectively. A pair of Schottky contacts can be formed on the semiconductor channel material such that the Schottky contacts cross over both side portions of the second gate electrode, respectively.
摘要翻译：可以通过在衬底上形成第一和第二栅电极并在第一和第二栅电极上形成栅极绝缘层来提供制造CMOS晶体管的方法。可以在栅极绝缘层上形成具有第一导电类型的半导体沟道材料。可以在半导体沟道材料上形成一对欧姆接触，使得欧姆接触分别跨过第一栅电极的两侧部分。可以在半导体沟道材料上形成一对肖特基触点，使得肖特基触点分别跨过第二栅电极的两侧部分。

4. 发明授权

US08013366B2 Biosensor using nanoscale material as transistor channel and method of fabricating the same 有权
标题翻译：使用纳米级材料作为晶体管沟道的生物传感器及其制造方法
公开(公告)号：US08013366B2
公开(公告)日：2011-09-06
申请号：US12232243
申请日：2008-09-12
申请人： Moon-Sook Lee , Byeong-Ok Cho , Man-Hyoung Ryoo , Takahiro Yasue , Jung-Hwan Hah
发明人： Moon-Sook Lee , Byeong-Ok Cho , Man-Hyoung Ryoo , Takahiro Yasue , Jung-Hwan Hah
IPC分类号： G01N27/403 , H01L21/00
CPC分类号： G01N27/4145 , B82Y10/00 , B82Y15/00 , G01N27/4146 , H01L51/0595 , H01L2924/0002 , H01L2924/00
摘要： Example embodiments relate to a biosensor using a nanoscale material as a channel of a transistor and a method of fabricating the same. A biosensor according to example embodiments may include a plurality of insulating films. A first signal line and a second signal line may be interposed between the plurality of insulating films. A semiconductor nanostructure may be disposed on the plurality of insulating films, the semiconductor nanostructure having a first side electrically connected to the first signal line and a second side electrically connected to the second signal line. A plurality of probes may be coupled to the semiconductor nanostructure. A biosensor according to example embodiments may have a reduced analysis time.
摘要翻译：实施例涉及使用纳米级材料作为晶体管的沟道的生物传感器及其制造方法。根据示例性实施例的生物传感器可以包括多个绝缘膜。第一信号线和第二信号线可以插入在多个绝缘膜之间。半导体纳米结构可以设置在多个绝缘膜上，半导体纳米结构具有电连接到第一信号线的第一侧和与第二信号线电连接的第二侧。多个探针可以耦合到半导体纳米结构。根据示例性实施例的生物传感器可以具有减少的分析时间。

5. 发明申请

US20090258443A1 Nonvolatile memory devices and methods of fabricating the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20090258443A1
公开(公告)日：2009-10-15
申请号：US12381987
申请日：2009-03-18
申请人： Yasue Takahiro , Byeong-Ok Cho , Moon-Sook Lee
发明人： Yasue Takahiro , Byeong-Ok Cho , Moon-Sook Lee
IPC分类号： H01L21/02
CPC分类号： H01L27/11507 , B82Y10/00 , H01L21/28291 , H01L27/101 , H01L27/285 , H01L28/40 , H01L51/0004
摘要： Nonvolatile memory devices and methods of fabricating the same are provided. In some embodiments, a nonvolatile memory device includes a lower conductive member formed on an upper part of or inside a substrate, a ferroelectric organic layer formed on the lower conductive member, a protective layer formed on the ferroelectric organic layer, and an upper conductive member formed on the protective layer to cross the lower conductive member.
摘要翻译：提供非易失性存储器件及其制造方法。在一些实施例中，非易失性存储器件包括形成在衬底的上部或内部的下导电构件，形成在下导电构件上的铁电有机层，形成在铁电有机层上的保护层和上导电构件形成在保护层上以穿过下导电构件。

6. 发明授权

US08338815B2 Memory units and related semiconductor devices including nanowires 失效
标题翻译：存储器单元和包括纳米线的相关半导体器件
公开(公告)号：US08338815B2
公开(公告)日：2012-12-25
申请号：US12851268
申请日：2010-08-05
申请人： Moon-Sook Lee , Byeong-Ok Cho , Man-Hyoung Ryoo , Takahiro Yasue
发明人： Moon-Sook Lee , Byeong-Ok Cho , Man-Hyoung Ryoo , Takahiro Yasue
IPC分类号： H01L29/04 , H01L47/00
CPC分类号： H01L27/11507 , B82Y10/00 , H01L27/10 , H01L27/1021 , H01L27/24
摘要： Methods of fabricating a memory unit are provided including forming a plurality of first nanowire structures, each of which includes a first nanowire extending in a first direction parallel to the first substrate and a first electrode layer enclosing the first nanowire, on a first substrate. The first electrode layers are partially removed to form first electrodes beneath the first nanowires. A first insulation layer filling up spaces between structures, each of which includes the first nanowire and the first electrode, is formed on the first substrate. A second electrode layer is formed on the first nanowires and the first insulation layer. A plurality of second nanowires is formed on the second electrode layer, each of which extends in a second direction perpendicular to the first direction. The second electrode layer is partially etched using the second nanowires as an etching mask to form a plurality of second electrodes. Related memory units, methods of fabricating semiconductor devices and semiconductor devices are also provided.
摘要翻译：提供了一种制造存储器单元的方法，包括形成多个第一纳米线结构，每个第一纳米线结构包括在第一衬底上沿与第一衬底平行的第一方向延伸的第一纳米线和包围第一纳米线的第一电极层。第一电极层被部分地去除以在第一纳米线下方形成第一电极。填充第一基板上形成有第一纳米线和第一电极的结构之间的空间的第一绝缘层。在第一纳米线和第一绝缘层上形成第二电极层。多个第二纳米线形成在第二电极层上，每个第二纳米线沿垂直于第一方向的第二方向延伸。使用第二纳米线作为蚀刻掩模来部分蚀刻第二电极层以形成多个第二电极。还提供了相关的存储单元，制造半导体器件和半导体器件的方法。

7. 发明申请

US20100013018A1 CMOS TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译： CMOS晶体管及其制造方法
公开(公告)号：US20100013018A1
公开(公告)日：2010-01-21
申请号：US12506656
申请日：2009-07-21
申请人： Sang-Hun Jeon , Moon-Sook Lee , Byeong-Ok Cho
发明人： Sang-Hun Jeon , Moon-Sook Lee , Byeong-Ok Cho
IPC分类号： H01L27/092
CPC分类号： H01L27/124 , B82Y10/00 , H01L27/095 , H01L27/1214 , H01L27/1222 , H01L27/1225 , H01L27/1251 , H01L29/0665 , H01L29/0673 , H01L29/45 , H01L29/7839 , H01L29/78681 , H01L29/7869
摘要： In a complementary metal-oxide semiconductor (CMOS) transistor and a method of manufacturing the same, a semiconductor channel material having a first conductivity type is provided on a substrate. A first transistor having the first conductivity type and a second transistor having a second conductivity type are positioned on the substrate, respectively. The first transistor includes a first gate positioned on a first surface of the channel material through a medium of a gate insulation layer and a pair of ohmic contacts positioned on a second surface of the channel material and crossing over both side portions of the first gate electrode, respectively. The second transistor includes a second gate positioned on the first surface of the channel material through a medium of the gate insulation layer and a pair of Schottky contacts positioned on the second surface of the channel material and crossing over both side portions of the second gate electrode, respectively.
摘要翻译：在互补金属氧化物半导体（CMOS）晶体管及其制造方法中，在基板上设置具有第一导电类型的半导体沟道材料。具有第一导电类型的第一晶体管和具有第二导电类型的第二晶体管分别位于衬底上。第一晶体管包括位于通道材料的第一表面上的第一栅极，该第一栅极通过栅极绝缘层的介质和位于沟道材料的第二表面上的一对欧姆触点，并且跨越第一栅电极的两侧部分，分别。第二晶体管包括通过栅极绝缘层的介质定位在沟道材料的第一表面上的第二栅极和位于沟道材料的第二表面上并与第二栅电极的两侧部分交叉的一对肖特基触点，分别。

8. 发明申请

US20100006849A1 Thin Film Transistors 有权
标题翻译：薄膜晶体管
公开(公告)号：US20100006849A1
公开(公告)日：2010-01-14
申请号：US12497852
申请日：2009-07-06
申请人： Sang-Hun Jeon , Moon-Sook Lee , Byeong-Ok Cho
发明人： Sang-Hun Jeon , Moon-Sook Lee , Byeong-Ok Cho
IPC分类号： H01L29/786
CPC分类号： H01L29/41733 , H01L27/1292 , H01L29/42384
摘要： A thin film transistor includes a layer structure having a gate electrode, a gate insulation layer and a channel layer. A source line may contact the channel layer, and may extend along a direction crossing over the gate electrode. The source line may partially overlap the gate electrode so that both sides of the source line overlapping the gate electrode may be entirely positioned between both sides of the gate electrode. A drain line may make contact with the channel layer and may be spaced apart from the source line by a channel length. The drain line may have a structure symmetrical to that of the source line. Overlap areas among the gate electrode, the source line and the drain line may be reduced, so that the thin film transistor may ensure a high cut-off frequency.
摘要翻译：薄膜晶体管包括具有栅电极，栅极绝缘层和沟道层的层结构。源极线可以接触沟道层，并且可以沿着与栅电极交叉的方向延伸。源极线可以部分地与栅电极重叠，使得与栅电极重叠的源极线的两侧可以完全位于栅电极的两侧之间。漏极线可以与沟道层接触并且可以与源极线隔开通道长度。漏极线可以具有与源极线对称的结构。可以减小栅电极，源极线和漏极线之间的重叠区域，使得薄膜晶体管可以确保高的截止频率。

9. 发明申请

US20090189152A1 FERROELECTRIC MEMORY DEVICE 审中-公开
标题翻译：电磁存储器件
公开(公告)号：US20090189152A1
公开(公告)日：2009-07-30
申请号：US12354990
申请日：2009-01-16
申请人： Byeong-Ok Cho , Moon-Sook Lee , Man-Hyoung Ryoo , Jung-Hyeon Kim , Takahiro Yasue
发明人： Byeong-Ok Cho , Moon-Sook Lee , Man-Hyoung Ryoo , Jung-Hyeon Kim , Takahiro Yasue
IPC分类号： H01L51/00 , H01L29/76
CPC分类号： H01L29/78391 , B82Y10/00 , G11C11/22 , H01L29/40111 , H01L29/516 , H01L29/6684
摘要： Provided is a ferroelectric memory device. The ferroelectric memory device includes an inorganic channel pattern on a substrate, a source electrode and a drain electrode spaced apart from each other on the substrate and contacting the inorganic channel pattern, a gate electrode disposed adjacent to the inorganic channel pattern, and an organic ferroelectric layer interposed between the inorganic channel pattern and the gate electrode.
摘要翻译：提供了一种铁电存储器件。铁电存储器件包括在衬底上的无机沟道图案，在衬底上彼此间隔开的源电极和漏电极，并与无机沟道图案接触，邻近无机沟道图案设置的栅电极和有机铁电体介于无机通道图案和栅电极之间的层。

10. 发明授权

US06718293B1 Etching and growth simulation method using a modified cell model 有权
标题翻译：蚀刻和增长模拟方法使用修改的细胞模型
公开(公告)号：US06718293B1
公开(公告)日：2004-04-06
申请号：US09372595
申请日：1999-08-12
申请人： Jae-Hee Ha , Sang-Heup Moon , Byeong-Ok Cho , Sung-Wook Hwang
发明人： Jae-Hee Ha , Sang-Heup Moon , Byeong-Ok Cho , Sung-Wook Hwang
IPC分类号： G06G748
CPC分类号： G06F17/5018
摘要： A computer simulation method for a semiconductor device manufacturing process, includes: a first step for forming an initial section of the material with only open cells exposed to the growth or etching among the cells; a second step for inputting information including growth or etching points into each open cell; a third step for computing a movement speed for the growth or etching points; a fourth step for moving the growth or etching points for a time determined according to the movement speed; and a fifth step for forming a new etching section by re-arranging the open cells exposed to the growth or etching, after moving the growth or etching points, the second to fifth steps being repeatedly performed on the re-arranged open cells until the sum of the predetermined time reaches the time (T).
摘要翻译：一种用于半导体器件制造工艺的计算机模拟方法，包括：第一步骤，用于仅形成暴露于单元之间的生长或蚀刻的开放单元的材料的初始部分; 用于将包括生长或蚀刻点的信息输入到每个开放单元的第二步骤; 用于计算生长或蚀刻点的移动速度的第三步骤; 第四步骤，用于根据移动速度移动生长或蚀刻点一段时间; 以及第五步骤，通过重新布置暴露于生长或蚀刻的开放单元，在移动生长或蚀刻点之后形成新的蚀刻部分，在重新排列的开放单元上重复执行第二至第五步骤，直到总和的时间达到时间（T）。

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