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1. 发明授权

US07795762B2 On-chip high frequency power supply noise sensor 失效
标题翻译：片上高频电源噪声传感器
公开(公告)号：US07795762B2
公开(公告)日：2010-09-14
申请号：US11832379
申请日：2007-08-01
申请人： Daniel M. Dreps , Seongwon Kim , Michael A. Sperling
发明人： Daniel M. Dreps , Seongwon Kim , Michael A. Sperling
IPC分类号： H03K17/82
CPC分类号： H02H9/046
摘要： The on-chip power supply noise sensor detects high frequency overshoots and undershoots of the power supply voltage. By creating two identical current sources and attaching a time constant circuit to only one, the high frequency transient behavior differs while the low frequency behavior is equivalent. By comparing these currents, the magnitude of very high frequency power supply noise can be sensed and used to either set latches or add to a digital counter. This has the advantage of directly sensing the power supply noise in a manner that does not require calibration. Also, since the sensor requires only one power supply, it can be used anywhere on a chip. Finally, it filters out any lower frequency noise that is not interesting to the circuit designer and can be tuned to detect down to whatever frequency is needed.
摘要翻译：片上电源噪声传感器检测电源电压的高频超频和欠压。通过产生两个相同的电流源并将时间常数电路连接到一个，高频瞬态行为在低频行为相当时不同。通过比较这些电流，可以感测到非常高频率的电源噪声的幅度，并用于设置锁存器或添加到数字计数器。这具有以不需要校准的方式直接感测电源噪声的优点。此外，由于传感器只需要一个电源，所以它可以在芯片的任何地方使用。最后，它滤除电路设计人员不感兴趣的任何较低频率的噪声，并且可以将其调谐到需要的频率。

2. 发明申请

US20090034144A1 On-Chip High Frequency Power Supply Noise Sensor 失效
标题翻译：片上高频电源噪声传感器
公开(公告)号：US20090034144A1
公开(公告)日：2009-02-05
申请号：US11832379
申请日：2007-08-01
申请人： Daniel M. Dreps , Seongwon Kim , Michael A. Sperling
发明人： Daniel M. Dreps , Seongwon Kim , Michael A. Sperling
IPC分类号： H02H9/06
CPC分类号： H02H9/046
摘要： The on-chip power supply noise sensor detects high frequency overshoots and undershoots of the power supply voltage. By creating two identical current sources and attaching a time constant circuit to only one, the high frequency transient behavior differs while the low frequency behavior is equivalent. By comparing these currents, the magnitude of very high frequency power supply noise cars be sensed and used to either set latches or add to a digital counter. This has the advantage of directly sensing the power supply noise in a matter that does not require calibration. Also, since the sensor requires only one power supply, it can he used anywhere on a chip. Finally, it filters out any lower frequency noise that is not interesting to the circuit designer and can he timed to detect down to whatever frequency is needed.
摘要翻译：片上电源噪声传感器检测电源电压的高频超频和欠压。通过产生两个相同的电流源并将时间常数电路连接到一个，高频瞬态行为在低频行为相当时不同。通过比较这些电流，将检测非常高频率的电源噪声汽车的大小，并将其用于设置锁存器或添加到数字计数器。这具有直接感测不需要校准的物质中的电源噪声的优点。此外，由于传感器只需要一个电源，所以它可以在芯片的任何地方使用。最后，它滤除电路设计人员不感兴趣的任何低频噪声，并且可以定时检测到任何需要的频率。

3. 发明授权

US07279949B2 Programmable delay element 有权
标题翻译：可编程延迟元件
公开(公告)号：US07279949B2
公开(公告)日：2007-10-09
申请号：US11215416
申请日：2005-08-30
申请人： Daniel M. Dreps , Frank D. Ferraiolo , Daniel J. Friedman , Seongwon Kim , Hector Saenz , Michael A. Sperling
发明人： Daniel M. Dreps , Frank D. Ferraiolo , Daniel J. Friedman , Seongwon Kim , Hector Saenz , Michael A. Sperling
IPC分类号： H03H11/26
CPC分类号： H03H11/265 , H03K5/133 , H03K2005/00039
摘要： Delay elements and delay lines having glitchless operation are disclosed. By way of example, apparatus for delaying an input signal comprises a reference current generator for generating a constant current, wherein the constant current is insensitive to a variation of a power supply voltage, at least one variable bias voltage generator coupled to the reference current generator for generating a set of bias voltages based on the constant current generated by the reference current generator and a digitally programmable delay control input, and at least one delay element coupled to the at least one variable bias voltage generator for delaying the input signal by a constant delay which is determined by the set of bias voltages generated by the at least one variable bias voltage generator.
摘要翻译：公开了具有无毛刺操作的延迟元件和延迟线。作为示例，用于延迟输入信号的装置包括用于产生恒定电流的参考电流发生器，其中恒定电流对电源电压的变化不敏感，耦合到参考电流发生器的至少一个可变偏置电压发生器用于基于由参考电流发生器和数字可编程延迟控制输入产生的恒定电流产生一组偏置电压，以及耦合到所述至少一个可变偏置电压发生器的至少一个延迟元件，用于将输入信号延迟常数由所述至少一个可变偏置电压发生器产生的偏置电压组确定的延迟。

4. 发明授权

US07932705B2 Variable input voltage regulator 失效
标题翻译：可变输入电压调节器
公开(公告)号：US07932705B2
公开(公告)日：2011-04-26
申请号：US12178678
申请日：2008-07-24
申请人： Seongwon Kim , Daniel M. Dreps
发明人： Seongwon Kim , Daniel M. Dreps
IPC分类号： G05F1/563 , G05F1/59 , G05F5/08
CPC分类号： G05F1/561
摘要： A variable input voltage regulator includes a first circuit configured to convert a first voltage from a first voltage source to a first current, and a second circuit electrically coupled to the first circuit and configured to mirror the first current to a voltage output node. The variable input voltage regulator further includes a third circuit electrically coupled to the voltage output node of the second circuit and configured to supply additional current to the voltage output node from a second voltage of a second voltage source in response to a control input.
摘要翻译：可变输入电压调节器包括被配置为将第一电压从第一电压源转换为第一电流的第一电路，以及电耦合到第一电路并被配置为将第一电流镜像到电压输出节点的第二电路。可变输入电压调节器还包括电耦合到第二电路的电压输出节点并被配置为响应于控制输入从第二电压源的第二电压向电压输出节点提供附加电流的第三电路。

5. 发明申请

US20100019744A1 VARIABLE INPUT VOLTAGE REGULATOR 失效
标题翻译：可变输入电压调节器
公开(公告)号：US20100019744A1
公开(公告)日：2010-01-28
申请号：US12178678
申请日：2008-07-24
申请人： Seongwon Kim , Daniel M. Dreps
发明人： Seongwon Kim , Daniel M. Dreps
IPC分类号： G05F1/10
CPC分类号： G05F1/561
摘要： A variable input voltage regulator includes a first circuit configured to convert a first voltage from a first voltage source to a first current, and a second circuit electrically coupled to the first circuit and configured to mirror the first current to a voltage output node. The variable input voltage regulator further includes a third circuit electrically coupled to the voltage output node of the second circuit and configured to supply additional current to the voltage output node from a second voltage of a second voltage source in response to a control input.
摘要翻译：可变输入电压调节器包括被配置为将第一电压从第一电压源转换为第一电流的第一电路，以及电耦合到第一电路并被配置为将第一电流镜像到电压输出节点的第二电路。可变输入电压调节器还包括电耦合到第二电路的电压输出节点并被配置为响应于控制输入从第二电压源的第二电压向电压输出节点提供附加电流的第三电路。

6. 发明授权

US07301320B2 On-chip high frequency power supply noise sensor 有权
标题翻译：片上高频电源噪声传感器
公开(公告)号：US07301320B2
公开(公告)日：2007-11-27
申请号：US11040225
申请日：2005-01-21
申请人： Daniel M. Dreps , Seongwon Kim , Michael A. Sperling
发明人： Daniel M. Dreps , Seongwon Kim , Michael A. Sperling
IPC分类号： G05F5/00 , H02J1/02
CPC分类号： H03K5/08 , G01R19/16552 , G01R29/26
摘要： The on-chip power supply noise sensor detects high frequency overshoots and undershoots of the power supply voltage. By creating two identical current sources and attaching a time constant circuit to only one, the high frequency transient behavior differs while the low frequency behavior is equivalent. By comparing these currents, the magnitude of very high frequency power supply noise can be sensed and used to either set latches or add to a digital counter. This has the advantage of directly sensing the power supply noise in a manner that does not require calibration. Also, since the sensor requires only one power supply, it can be used anywhere on a chip. Finally, it filters out any lower frequency noise that is not interesting to the circuit designer and can be tuned to detect down to whatever frequency is needed.
摘要翻译：片上电源噪声传感器检测电源电压的高频超频和欠压。通过产生两个相同的电流源并将时间常数电路连接到一个，高频瞬态行为在低频行为相当时不同。通过比较这些电流，可以感测到非常高频率的电源噪声的幅度，并用于设置锁存器或添加到数字计数器。这具有以不需要校准的方式直接感测电源噪声的优点。此外，由于传感器只需要一个电源，所以它可以在芯片的任何地方使用。最后，它滤除电路设计人员不感兴趣的任何较低频率的噪声，并且可以将其调谐到需要的频率。

7. 发明授权

US08718216B2 Digital phase detector with zero phase offset 失效
公开(公告)号：US08718216B2
公开(公告)日：2014-05-06
申请号：US13242053
申请日：2011-09-23
申请人： Daniel M. Dreps , Kyu-hyoun Kim , Glen A. Wiedemeier
发明人： Daniel M. Dreps , Kyu-hyoun Kim , Glen A. Wiedemeier
IPC分类号： H03D3/24
CPC分类号： H04L7/0037 , H03L7/0814 , H03L7/085 , H03L7/089
摘要： An embodiment of the invention comprises a digital phase detector with substantially zero phase offset. The digital phase detector receives a clock signal and a reference clock signal and provides a phase indicator signal to identify whether the clock signal leads or lags the reference clock signal. An embodiment of the invention comprises a method that adds substantially zero phase offset in processing an input clock signal and a delayed clock signal to generate a control signal. The control signal is processed in a variable delay line to generate the delayed clock signal. In an embodiment, a first processor comprises a delay locked loop having a digital phase detector, the digital phase detector comprising a first differential sense amplifier cross-coupled to a second differential sense amplifier, the digital phase detector receiving a clock signal and generating one or more delayed clock signals, a control signal, and a gated data signal.

8. 发明授权

US08452919B2 Advanced memory device having improved performance, reduced power and increased reliability 有权
标题翻译：先进的存储器件具有改进的性能，降低的功率和增加的可靠性
公开(公告)号：US08452919B2
公开(公告)日：2013-05-28
申请号：US13567357
申请日：2012-08-06
申请人： Kyu-Hyoun Kim , George L. Chiu , Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Warren E. Maule
发明人： Kyu-Hyoun Kim , George L. Chiu , Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Warren E. Maule
IPC分类号： G06F13/00
CPC分类号： G11C7/1078 , G06F11/1028 , G11C7/04 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/109 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/406 , G11C11/40611 , G11C11/40615 , G11C11/40626 , G11C11/4076 , G11C11/4096 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.
摘要翻译：具有改进性能，降低功耗和增加可靠性的高级内存。存储器件包括存储器阵列，用于接收命令和相关联的数据的接收器，用于对接收到的命令执行错误控制检查的差错控制编码电路以及用于防止相关联的数据被响应地写入存储器阵列的数据屏蔽电路对错误控制编码电路检测接收到的命令中的错误。另一个存储器件包括可编程序序。另一存储器件包括快速退出自刷新模式。另一种存储装置包括由特征装置控制的自动刷新功能。另一存储器件包括由存储器件的特性控制的自动刷新功能。

9. 发明授权

US08089813B2 Controllable voltage reference driver for a memory system 失效
标题翻译：用于存储系统的可控参考电压驱动器
公开(公告)号：US08089813B2
公开(公告)日：2012-01-03
申请号：US12175555
申请日：2008-07-18
申请人： Daniel M. Dreps
发明人： Daniel M. Dreps
IPC分类号： G11C16/06
CPC分类号： G11C29/02 , G11C5/04 , G11C5/063 , G11C5/147 , G11C8/08 , G11C29/021 , G11C29/028
摘要： A voltage reference driver includes a voltage divider circuit with a voltage reference output node to output a voltage between a first voltage and a second voltage. The voltage reference driver also includes a first selectable impedance circuit coupled to a node at the first voltage and further coupled to the voltage reference output node, and a second selectable impedance circuit coupled to a node at the second voltage and further coupled to the voltage reference output node. Combinations of the first selectable impedance circuit and the second selectable impedance circuit are selectable such that a constant impedance is maintained at the voltage reference output node within a threshold value.
摘要翻译：电压参考驱动器包括具有电压参考输出节点的分压器电路，以输出第一电压和第二电压之间的电压。电压参考驱动器还包括耦合到处于第一电压的节点的第一可选择阻抗电路并进一步耦合到电压参考输出节点，以及第二可选阻抗电路，耦合到处于第二电压的节点，并且还耦合到电压基准输出节点。可选择第一可选择阻抗电路和第二可选择阻抗电路的组合，使得在阈值内的电压参考输出节点处保持恒定的阻抗。

10. 发明申请

US20110289270A1 SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR DATA TRANSFER MANAGEMENT 有权
标题翻译：用于数据传输管理的系统，方法和计算机程序产品
公开(公告)号：US20110289270A1
公开(公告)日：2011-11-24
申请号：US12786072
申请日：2010-05-24
申请人： Robert H. Bell, JR. , Louis Bennie Capps, JR. , Daniel M. Dreps , Luis A. Lastras-Montano , Michael Jay Shapiro
发明人： Robert H. Bell, JR. , Louis Bennie Capps, JR. , Daniel M. Dreps , Luis A. Lastras-Montano , Michael Jay Shapiro
IPC分类号： G06F17/30 , G06F12/00
CPC分类号： G06F17/30899 , G06F17/30259 , G06K9/6202
摘要： According to one aspect of the present disclosure a method and technique for managing data transfer is disclosed. The method includes comparing, by a processor unit of a data processing system, data to be written to a memory subsystem to a stored data pattern and, responsive to determining that the data matches the stored data pattern, replacing the matching data with a pattern tag corresponding to the matching data pattern. The method also includes transmitting the pattern tag to the memory subsystem.
摘要翻译：根据本公开的一个方面，公开了一种用于管理数据传送的方法和技术。该方法包括将由数据处理系统的处理器单元将要写入存储器子系统的数据与存储的数据模式进行比较，并且响应于确定数据与存储的数据模式匹配，用模式标签替换匹配数据对应于匹配的数据模式。该方法还包括将模式标签发送到存储器子系统。

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