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1. 发明申请

US20110289270A1 SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR DATA TRANSFER MANAGEMENT 有权
标题翻译：用于数据传输管理的系统，方法和计算机程序产品
公开(公告)号：US20110289270A1
公开(公告)日：2011-11-24
申请号：US12786072
申请日：2010-05-24
申请人： Robert H. Bell, JR. , Louis Bennie Capps, JR. , Daniel M. Dreps , Luis A. Lastras-Montano , Michael Jay Shapiro
发明人： Robert H. Bell, JR. , Louis Bennie Capps, JR. , Daniel M. Dreps , Luis A. Lastras-Montano , Michael Jay Shapiro
IPC分类号： G06F17/30 , G06F12/00
CPC分类号： G06F17/30899 , G06F17/30259 , G06K9/6202
摘要： According to one aspect of the present disclosure a method and technique for managing data transfer is disclosed. The method includes comparing, by a processor unit of a data processing system, data to be written to a memory subsystem to a stored data pattern and, responsive to determining that the data matches the stored data pattern, replacing the matching data with a pattern tag corresponding to the matching data pattern. The method also includes transmitting the pattern tag to the memory subsystem.
摘要翻译：根据本公开的一个方面，公开了一种用于管理数据传送的方法和技术。该方法包括将由数据处理系统的处理器单元将要写入存储器子系统的数据与存储的数据模式进行比较，并且响应于确定数据与存储的数据模式匹配，用模式标签替换匹配数据对应于匹配的数据模式。该方法还包括将模式标签发送到存储器子系统。

2. 发明授权

US08862944B2 Isolation of faulty links in a transmission medium 有权
标题翻译：隔离传输介质中的故障链路
公开(公告)号：US08862944B2
公开(公告)日：2014-10-14
申请号：US12822508
申请日：2010-06-24
申请人： John S. Dodson , Frank D. Ferraiolo , Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Kenneth L. Wright , Lisa C. Gower
发明人： John S. Dodson , Frank D. Ferraiolo , Michele M. Franceschini , Kevin C. Gower , Ashish Jagmohan , Luis A. Lastras-Montano , Kenneth L. Wright
IPC分类号： G06F11/00 , G06F11/20 , G06F11/10 , H04L1/00
CPC分类号： G06F11/10 , G06F11/2005 , H04L1/0061 , H04L2001/0096
摘要： Isolation of faulty links in a transmission medium including a method that includes receiving an atomic data unit via a multi-link transmission medium that has a plurality of transmission links. An error condition is detected and it is determined that the error condition is isolated to a single transmission link. It is determined if the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer. If the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer then: identifying the single transmission link as a faulty transmission link; resetting the timer; and outputting an identifier of the single transmission link.
摘要翻译：隔离传输介质中的故障链路，包括包括通过具有多个传输链路的多链路传输介质接收原子数据单元的方法。检测到错误状况，并且确定错误状况被隔离到单个传输链路。在由定时器指定的间隔内，确定单个传输链路是否已经被隔离为先前被隔离的传输链路指定的次数。如果单个传输链路在由定时器指定的间隔内已经被隔离为失败的传输链路指定的次数，则：将单个传输链路识别为有故障的传输链路; 重置定时器; 并输出单个传输链路的标识符。

3. 发明授权

US08566682B2 Failing bus lane detection using syndrome analysis 有权
标题翻译：使用综合征分析的公交车道检测失败
公开(公告)号：US08566682B2
公开(公告)日：2013-10-22
申请号：US12822498
申请日：2010-06-24
申请人： Luis A. Lastras-Montano , Patrick J. Meaney , Lisa C. Gower
发明人： Kevin C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney
IPC分类号： H03M13/00
CPC分类号： G06F11/10 , H03M13/09 , H04L1/0061 , H04L1/24 , H04L2001/0094
摘要： Failing bus lane detection using syndrome analysis, including a method for receiving a plurality of syndromes of an error detection code, the error detection code associated with a plurality of frames that have been transmitted on a bus that includes a plurality of lanes and is protected by the error detection code. The method includes performing for each of the lanes in each of the syndromes: decoding the syndrome under an assumption that the lane is a failing lane, the decoding outputting a decode result; determining if the decode result is a valid decode; and voting for the lane in response to determining that the decode result is a valid decode. A failing lane is then identified in response to the voting, with the failing lane being characterized by having more votes than at least one other lane on the bus.
摘要翻译：包括用于接收错误检测码的多个综合征的方法，所述错误检测码与已经在包括多个车道的总线上发送并被由多个车道保护的多个帧相关联的错误检测码错误检测码。该方法包括对每个综合征中的每个通道执行：在所述通道是故障通道的假设下解码所述综合征，所述解码输出解码结果; 确定解码结果是否是有效的解码; 并且响应于确定解码结果是有效解码而对该通道进行投票。然后，响应于投票，确定失败的车道，失败的车道的特征在于比公车上的至少另一个车道具有更多的票数。

4. 发明授权

US08407410B2 Wear-leveling and bad block management of limited lifetime memory devices 有权
标题翻译：有限寿命内存设备的磨损均衡和坏块管理
公开(公告)号：US08407410B2
公开(公告)日：2013-03-26
申请号：US13445172
申请日：2012-04-12
申请人： Bulent Abali , John P. Karidis , Luis A. Lastras-Montano
发明人： Bulent Abali , John P. Karidis , Luis A. Lastras-Montano
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7211 , G11C16/349 , G11C16/3495 , G11C29/76 , G11C29/82
摘要： Performing wear-leveling and bad block management of limited lifetime memory devices. A method for performing wear-leveling in a memory includes receiving logical memory addresses and applying a randomizing function to the logical memory addresses to generate intermediate addresses within a range of intermediate addresses. The intermediate addresses are mapped into physical addresses of a memory using an algebraic mapping. The physical addresses are within a range of physical addresses that include at least one more location than the range of intermediate addresses. The physical addresses are output for use in accessing the memory. The mapping between the intermediate addresses and the physical addresses is periodically shifted. In addition, contents of bad blocks are replaced with redundantly encoded redirection addresses.
摘要翻译：执行有限寿命内存设备的磨损均衡和坏块管理。用于在存储器中执行磨损均衡的方法包括接收逻辑存储器地址并将随机化功能应用于逻辑存储器地址以在中间地址的范围内生成中间地址。使用代数映射将中间地址映射到存储器的物理地址。物理地址在物理地址的范围内，其包括比中间地址的范围至少一个以上的位置。输出物理地址用于访问存储器。中间地址和物理地址之间的映射周期性地移位。此外，坏块的内容被替换为冗余编码的重定向地址。

5. 发明申请

US20130018889A1 Lossless compression of high nominal-range data 有权
公开(公告)号：US20130018889A1
公开(公告)日：2013-01-17
申请号：US13181880
申请日：2011-07-13
申请人： Ashish Jagmohan , Joshua W. Knight , Luis A. Lastras-Montano
发明人： Ashish Jagmohan , Joshua W. Knight , Luis A. Lastras-Montano
IPC分类号： G06F17/30
CPC分类号： H03M7/3084 , G06F17/30613 , G06F2212/401
摘要： A method for receiving a data stream that includes data samples, each data sample having one of a plurality of actual values. For each data sample in the data stream, a first index in a dictionary is selected. The dictionary includes indices corresponding to each of the plurality of actual values. The first index corresponds to an actual value of the data sample. A predicted value of the data sample is generated in response to previously received data samples in the data stream and to a prediction algorithm. A second index in the dictionary that corresponds to an actual value in the dictionary that is closest to the value of the predicted value is selected. The difference between the first index and the second index is calculated and compressed. The compressed difference between the first index and the second index is then output. This process is performed for each data sample in the data stream.

6. 发明申请

US20120218814A1 WRITE BANDWIDTH IN A MEMORY CHARACTERIZED BY A VARIABLE WRITE TIME 有权
标题翻译：在一个由可变写入时间表示的存储器中的写带宽
公开(公告)号：US20120218814A1
公开(公告)日：2012-08-30
申请号：US13034936
申请日：2011-02-25
申请人： John A. Bivens , Michele M. Franceschini , Luis A. Lastras-Montano
发明人： John A. Bivens , Michele M. Franceschini , Luis A. Lastras-Montano
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/1012 , G06F2213/0038 , G11C13/0004 , G11C13/0069 , G11C2013/008
摘要： A memory system that includes a plurality of memory arrays having memory cells characterized by a variable write time. The memory system also includes a memory bus configured to receive write commands, and a plurality of data buffers configured to communicate with the memory arrays. The memory system further includes an address buffer configured to communicate with the memory arrays to store the write addresses. A mechanism configured to receive a write command and to split a data line received with the write command into a number of parts is also included in the memory system. The parts of the data line are stored in different data buffers and the writing of the parts of the data line to memory arrays at the write address is initiated. The write command is completed when write completion signals specifying the write address have been received from all of the memory arrays.
摘要翻译：一种存储器系统，其包括具有由可变写入时间表征的存储器单元的多个存储器阵列。存储器系统还包括被配置为接收写入命令的存储器总线以及被配置为与存储器阵列进行通信的多个数据缓冲器。存储器系统还包括配置为与存储器阵列通信以存储写入地址的地址缓冲器。被配置为接收写入命令并将用写入命令接收的数据线分割成多个部件的机构也包括在存储器系统中。数据线的部分存储在不同的数据缓冲器中，并且开始将写入地址的数据线的部分写入存储器阵列。当从所有存储器阵列接收到指定写入地址的写入完成信号时，写入命令完成。

7. 发明授权

US08255613B2 Wear-leveling and bad block management of limited lifetime memory devices 有权
标题翻译：有限寿命内存设备的磨损均衡和坏块管理
公开(公告)号：US08255613B2
公开(公告)日：2012-08-28
申请号：US12433220
申请日：2009-04-30
申请人： Bulent Abali , John P. Karidis , Luis A. Lastras-Montano
发明人： Bulent Abali , John P. Karidis , Luis A. Lastras-Montano
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7211 , G11C16/349 , G11C16/3495 , G11C29/76 , G11C29/82
摘要： Performing wear-leveling and bad block management of limited lifetime memory devices. A method for performing wear-leveling in a memory includes receiving logical memory addresses and applying a randomizing function to the logical memory addresses to generate intermediate addresses within a range of intermediate addresses. The intermediate addresses are mapped into physical addresses of a memory using an algebraic mapping. The physical addresses are within a range of physical addresses that include at least one more location than the range of intermediate addresses. The physical addresses are output for use in accessing the memory. The mapping between the intermediate addresses and the physical addresses is periodically shifted. In addition, contents of bad blocks are replaced with redundantly encoded redirection addresses.
摘要翻译：执行有限寿命内存设备的磨损均衡和坏块管理。用于在存储器中执行磨损均衡的方法包括接收逻辑存储器地址并将随机化功能应用于逻辑存储器地址以在中间地址的范围内生成中间地址。使用代数映射将中间地址映射到存储器的物理地址。物理地址在物理地址的范围内，其包括比中间地址的范围至少一个以上的位置。输出物理地址用于访问存储器。中间地址和物理地址之间的映射周期性地移位。此外，坏块的内容被替换为冗余编码的重定向地址。

8. 发明申请

US20120127790A1 ADJUSTABLE WRITE BINS FOR MULTI-LEVEL ANALOG MEMORIES 失效
标题翻译：用于多级模拟记忆体的可调写文字
公开(公告)号：US20120127790A1
公开(公告)日：2012-05-24
申请号：US13355833
申请日：2012-01-23
申请人： Ibrahim M. Elfadel , Michele M. Franceschini , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Ibrahim M. Elfadel , Michele M. Franceschini , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C11/00 , G06F12/00
CPC分类号： G11C8/10 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C27/005 , G11C2013/0083
摘要： Selecting bins in a memory by receiving a target cost for performing writes at an analog memory that is capable of storing a range of values. Possible bins that may be created in the range of values and a cost associated with each possible bin are determined. Each possible bin includes one or more of the values. A group of bins are identified, the group of bins are among the possible bins with associated costs that are within a threshold of the target cost. A maximum number of bins are selected from the group of bins that have non-overlapping values. The selected bins are stored along with the values of the selected bins utilized to encode and decode contents of the analog memory.
摘要翻译：通过接收在能够存储一定范围的值的模拟存储器上执行写入的目标成本来选择存储器中的存储器。确定可能在值范围内创建的可能的仓和与每个可能仓相关联的成本。每个可能的仓包括一个或多个值。识别出一组垃圾箱，这些垃圾箱是可能的垃圾箱，其相关成本在目标成本的阈值之内。从具有非重叠值的分组组中选择最大数量的分区。所选择的存储槽与用于对模拟存储器的内容进行编码和解码的所选择的存储器的值一起存储。

9. 发明授权

US08185801B2 System to improve error code decoding using historical information and associated methods 有权
标题翻译：系统使用历史信息和相关方法改进错误码解码
公开(公告)号：US08185801B2
公开(公告)日：2012-05-22
申请号：US12023445
申请日：2008-01-31
申请人： Timothy J. Dell , Luis A. Lastras-Montano , Barry M. Trager , Shmuel Winograd
发明人： Timothy J. Dell , Luis A. Lastras-Montano , Barry M. Trager , Shmuel Winograd
IPC分类号： H03M13/00
CPC分类号： G06F11/1044
摘要： A system to improve error code decoding using historical information. An example system includes storage partitioned into memory ranks, and a table to record symbols having failures for each memory rank. The system generates a memory rank score for each memory rank. The system also includes an error control decoder that uses the memory rank score when each memory rank is accessed in order to determine whether an error should be corrected or not.
摘要翻译：一种使用历史信息改进错误代码解码的系统。示例性系统包括分割成存储器排名的存储器，以及用于记录具有每个存储器级别的故障的符号的表。系统为每个存储器级别生成内存等级分数。该系统还包括错误控制解码器，当访问每个存储器等级时，使用存储器等级分数，以便确定是否应该纠正错误。

10. 发明授权

US08125809B2 Adjustable write bins for multi-level analog memories 有权
标题翻译：适用于多级模拟存储器的可调式写入箱
公开(公告)号：US08125809B2
公开(公告)日：2012-02-28
申请号：US12566430
申请日：2009-09-24
申请人： Ibrahim M. Elfadel , Michele M. Franceschini , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Ibrahim M. Elfadel , Michele M. Franceschini , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C27/00
CPC分类号： G11C8/10 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C27/005 , G11C2013/0083
摘要： An analog memory having adjustable write bins including a system for writing to the memory. The system includes a write apparatus interpreting one or more write control signals, generating a write signal, and applying the write signal at a selected memory location to store a desired content. The selected memory location is subject to data dependent noise and is capable of storing a range of values grouped into “n” bins configured such that the average cost to write to at least “n-1” of the bins is within a threshold of a target cost for the selected analog memory location. The system also includes a read apparatus. The system further includes write control circuitry that includes a write signal selector selecting the one or more write control signals responsive to the desired content, current content of the selected memory location, and a bin associated with the desired content.
摘要翻译：具有可调节写入箱的模拟存储器，包括用于向存储器写入的系统。该系统包括解释一个或多个写入控制信号的写入装置，产生写入信号，以及在选择的存储器位置处施加写入信号以存储所需的内容。所选择的存储器位置受到数据相关噪声的影响，并且能够存储被分配到“n”个存储槽中的值的范围，其被配置为使得写入至少“n-1”个存储单元的平均成本在所选模拟存储器位置的目标成本。该系统还包括读取装置。该系统还包括写控制电路，其包括响应于期望内容选择一个或多个写入控制信号的写入信号选择器，所选择的存储器位置的当前内容以及与期望内容相关联的存储区。

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