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1. 发明申请

US20060257563A1 Method of fabricating silicon-doped metal oxide layer using atomic layer deposition technique 审中-公开
标题翻译：使用原子层沉积技术制造掺杂硅的金属氧化物层的方法
公开(公告)号：US20060257563A1
公开(公告)日：2006-11-16
申请号：US11329696
申请日：2006-01-11
申请人： Seok-Joo Doh , Shi-Woo Rhee , Jong-Pyo Kim , Jung-Hyoung Lee , Jong-Ho Lee , Yun-Seok Kim
发明人： Seok-Joo Doh , Shi-Woo Rhee , Jong-Pyo Kim , Jung-Hyoung Lee , Jong-Ho Lee , Yun-Seok Kim
IPC分类号： C23C16/00
CPC分类号： C23C16/401 , C23C16/45529 , C23C16/45531
摘要： There are provided methods of fabricating a silicon-doped metal oxide layer on a semiconductor substrate using an atomic layer deposition technique. The methods include an operation of repeatedly performing a metal oxide layer formation cycle K times and an operation of repeatedly performing a silicon-doped metal oxide layer formation cycle Q times. At least one of the values K and Q is an integer of 2 or more. K and Q are integers ranging from 1 to about 10 respectively. The metal oxide layer formation cycle includes the steps of supplying a metal source gas to a reactor containing the substrate, and then injecting an oxide gas into the reactor. The silicon-doped metal oxide layer formation cycle includes supplying a metal source gas including silicon into a reactor containing the substrate, and then injecting an oxide gas into the reactor. The sequence of operations of repeatedly performing the metal oxide layer formation cycle K times, followed by repeatedly performing the silicon-doped metal oxide layer formation cycle Q times, is performed one or more times until a silicon-doped metal oxide layer with a desired thickness is formed on the substrate. In addition, a method of fabricating a silicon-doped hafnium oxide (Si-doped HfO2) layer according to a similar invention method is also provided.
摘要翻译：提供了使用原子层沉积技术在半导体衬底上制造掺硅金属氧化物层的方法。这些方法包括重复进行金属氧化物层形成循环K次的操作和重复进行掺硅金属氧化物层形成循环Q次的操作。值K和Q中的至少一个是2以上的整数。 K和Q分别为1至约10的整数。金属氧化物层形成循环包括将金属源气体供给到包含基板的反应器中，然后将氧化物气体注入到反应器中的步骤。掺杂硅的金属氧化物层形成循环包括将含有硅的金属源气体供给到含有该基板的反应器中，然后将氧化物气体注入反应器。重复执行金属氧化物层形成循环K次的操作顺序，随后重复进行掺杂硅的金属氧化物层形成循环Q次，执行一次或多次，直到具有所需厚度的掺硅金属氧化物层形成在基板上。此外，还提供了根据类似的发明方法制造掺杂硅的氧化铪（Si掺杂的HfO 2 N 2）层的方法。

2. 发明申请

US20050098839A1 Semiconductor devices having different gate dielectrics and methods for manufacturing the same 审中-公开
标题翻译：具有不同栅极电介质的半导体器件及其制造方法
公开(公告)号：US20050098839A1
公开(公告)日：2005-05-12
申请号：US10930943
申请日：2004-09-01
申请人： Jong-Ho Lee , Ho-Kyu Kang , Yun-Seok Kim , Seok-Joo Doh , Hyung-Suk Jung
发明人： Jong-Ho Lee , Ho-Kyu Kang , Yun-Seok Kim , Seok-Joo Doh , Hyung-Suk Jung
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/94
CPC分类号： H01L21/823857
摘要： A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate dielectric is located between the first substrate region and the first gate electrode. The second device includes a second substrate region, a second gate electrode, and a second gate dielectric. The second gate dielectric is located between the second substrate region and the second gate electrode. The first gate dielectric includes a first high-k layer having a dielectric constant of 8 or more. Likewise, the second gate dielectric includes a second high-k layer having a dielectric constant of 8 or more. The second high-k layer has a different material composition than the first high-k layer.
摘要翻译：半导体器件包括第一和第二晶体管器件。第一器件包括第一衬底区域，第一栅极电极和第一栅极电介质。第一栅极电介质位于第一衬底区域和第一栅电极之间。第二器件包括第二衬底区域，第二栅极电极和第二栅极电介质。第二栅极电介质位于第二基板区域和第二栅极电极之间。第一栅极电介质包括介电常数为8以上的第一高k层。类似地，第二栅极电介质包括介电常数为8或更大的第二高k层。第二高k层具有与第一高k层不同的材料组成。

3. 发明授权

US07586159B2 Semiconductor devices having different gate dielectrics and methods for manufacturing the same 有权
标题翻译：具有不同栅极电介质的半导体器件及其制造方法
公开(公告)号：US07586159B2
公开(公告)日：2009-09-08
申请号：US11723705
申请日：2007-03-21
申请人： Jong-Ho Lee , Ho-Kyu Kang , Yun-Seok Kim , Seok-Joo Doh , Hyung-Suk Jung
发明人： Jong-Ho Lee , Ho-Kyu Kang , Yun-Seok Kim , Seok-Joo Doh , Hyung-Suk Jung
IPC分类号： H01L29/94
CPC分类号： H01L21/823857 , H01L27/0922
摘要： A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate dielectric is located between the first substrate region and the first gate electrode. The second device includes a second substrate region, a second gate electrode, and a second gate dielectric. The second gate dielectric is located between the second substrate region and the second gate electrode. The first gate dielectric includes a first high-k layer having a dielectric constant of 8 or more. Likewise, the second gate dielectric includes a second high-k layer having a dielectric constant of 8 or more. The second high-k layer has a different material composition than the first high-k layer.
摘要翻译：半导体器件包括第一和第二晶体管器件。第一器件包括第一衬底区域，第一栅极电极和第一栅极电介质。第一栅极电介质位于第一衬底区域和第一栅电极之间。第二器件包括第二衬底区域，第二栅极电极和第二栅极电介质。第二栅极电介质位于第二基板区域和第二栅极电极之间。第一栅极电介质包括介电常数为8以上的第一高k层。类似地，第二栅极电介质包括介电常数为8或更大的第二高k层。第二高k层具有与第一高k层不同的材料组成。

4. 发明申请

US20070176242A1 Semiconductor devices having different gate dielectrics and methods for manufacturing the same 有权
标题翻译：具有不同栅极电介质的半导体器件及其制造方法
公开(公告)号：US20070176242A1
公开(公告)日：2007-08-02
申请号：US11723705
申请日：2007-03-21
申请人： Jong-Ho Lee , Ho-Kyu Kang , Yun-Seok Kim , Seok-Joo Doh , Hyung-Suk Jung
发明人： Jong-Ho Lee , Ho-Kyu Kang , Yun-Seok Kim , Seok-Joo Doh , Hyung-Suk Jung
IPC分类号： H01L29/94
CPC分类号： H01L21/823857 , H01L27/0922
摘要： A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate dielectric is located between the first substrate region and the first gate electrode. The second device includes a second substrate region, a second gate electrode, and a second gate dielectric. The second gate dielectric is located between the second substrate region and the second gate electrode. The first gate dielectric includes a first high-k layer having a dielectric constant of 8 or more. Likewise, the second gate dielectric includes a second high-k layer having a dielectric constant of 8 or more. The second high-k layer has a different material composition than the first high-k layer.
摘要翻译：半导体器件包括第一和第二晶体管器件。第一器件包括第一衬底区域，第一栅极电极和第一栅极电介质。第一栅极电介质位于第一衬底区域和第一栅电极之间。第二器件包括第二衬底区域，第二栅极电极和第二栅极电介质。第二栅极电介质位于第二基板区域和第二栅极电极之间。第一栅极电介质包括介电常数为8以上的第一高k层。类似地，第二栅极电介质包括介电常数为8或更大的第二高k层。第二高k层具有与第一高k层不同的材料组成。

5. 发明申请

US20050148127A1 Semiconductor device including gate dielectric layer formed of high dielectric alloy and method of fabricating the same 审中-公开
标题翻译：包括由高介电合金形成的栅极介电层的半导体器件及其制造方法
公开(公告)号：US20050148127A1
公开(公告)日：2005-07-07
申请号：US10989200
申请日：2004-11-15
申请人： Hyung-Suk Jung , Jong-Ho Lee , Seok-Joo Doh , Yun-Seok Kim
发明人： Hyung-Suk Jung , Jong-Ho Lee , Seok-Joo Doh , Yun-Seok Kim
IPC分类号： H01L21/336 , H01L21/28 , H01L29/51
CPC分类号： H01L21/28194 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A semiconductor device is disclosed comprising an improved gate dielectric layer formed of a high dielectric alloy-like composite together with a method for fabricating the same. The semiconductor device comprises a semiconductor substrate and a gate dielectric layer consisting essentially of a high-k alloy-like composite containing a first element, a second element, and oxygen (O). The first element is at least one member selected from a first group consisting of Al, La, Y, Ga, and In. The second element is at least one member selected from a second group consisting of Hf, Zr, and Ti. A diffusion barrier is formed on the gate dielectric layer, and a gate is formed on the diffusion barrier.
摘要翻译：公开了一种半导体器件，其包括由高介电合金样复合材料形成的改进的栅介质层及其制造方法。半导体器件包括半导体衬底和基本上由含有第一元素，第二元素和氧（O）的高k合金样复合材料组成的栅极电介质层。第一元素是选自由Al，La，Y，Ga和In组成的第一组中的至少一种。第二元素是选自由Hf，Zr和Ti构成的第二组中的至少一种。在栅介电层上形成扩散阻挡层，在扩散阻挡层上形成栅极。

6. 发明申请

US20050255246A1 Method of fabricating metal silicate layer using atomic layer deposition technique 有权
标题翻译：使用原子层沉积技术制造金属硅酸盐层的方法
公开(公告)号：US20050255246A1
公开(公告)日：2005-11-17
申请号：US11127748
申请日：2005-05-12
申请人： Yun-Seok Kim , Jong-Pyo Kim , Ha-Jin Lim , Jae-Eun Park , Hyung-Suk Jung , Jong-Ho Lee , Jong-Ho Yang
发明人： Yun-Seok Kim , Jong-Pyo Kim , Ha-Jin Lim , Jae-Eun Park , Hyung-Suk Jung , Jong-Ho Lee , Jong-Ho Yang
IPC分类号： C23C16/00 , C23C16/40 , C23C16/455
CPC分类号： C23C16/401 , C23C16/45529 , C23C16/45531
摘要： There are provided methods of fabricating a metal silicate layer on a semiconductor substrate using an atomic layer deposition technique. The methods include performing a metal silicate layer formation cycle at least one time in order to form a metal silicate layer having a desired thickness. The metal silicate layer formation cycle includes an operation of repeatedly performing a metal oxide layer formation cycle K times and an operation of repeatedly performing a silicon oxide layer formation cycle Q times. K and Q are integers ranging from 1 to 10 respectively. The metal oxide layer formation cycle includes the steps of supplying a metal source gas to a reactor containing the substrate, exhausting the metal source gas remaining in a reactor to clean the inside of the reactor, and then supplying an oxide gas into the reactor. The silicon oxide layer formation cycle includes supplying a silicon source gas, exhausting the silicon source gas remaining in the reactor to clean the inside of the reactor, and then supplying an oxide gas into the reactor.
摘要翻译：提供了使用原子层沉积技术在半导体衬底上制造金属硅酸盐层的方法。所述方法包括至少一次执行金属硅酸盐层形成循环以形成具有所需厚度的金属硅酸盐层。金属硅酸盐层形成循环包括重复执行金属氧化物层形成循环K次的操作和重复进行氧化硅层形成循环Q次的操作。 K和Q分别为1〜10的整数。金属氧化物层形成循环包括将金属源气体供给到含有基板的反应器，排出留在反应器内的金属源气体，清洗反应器内部，然后向反应器供给氧化气体的工序。氧化硅层形成循环包括提供硅源气体，排出留在反应器中的硅源气体以清洁反应器的内部，然后将氧化物气体供应到反应器中。

7. 发明授权

US07651729B2 Method of fabricating metal silicate layer using atomic layer deposition technique 有权
标题翻译：使用原子层沉积技术制造金属硅酸盐层的方法
公开(公告)号：US07651729B2
公开(公告)日：2010-01-26
申请号：US11127748
申请日：2005-05-12
申请人： Yun-Seok Kim , Jong-Pyo Kim , Ha-Jin Lim , Jae-Eun Park , Hyung-Suk Jung , Jong-Ho Lee , Jong-Ho Yang
发明人： Yun-Seok Kim , Jong-Pyo Kim , Ha-Jin Lim , Jae-Eun Park , Hyung-Suk Jung , Jong-Ho Lee , Jong-Ho Yang
IPC分类号： C23C16/00
CPC分类号： C23C16/401 , C23C16/45529 , C23C16/45531
摘要： There are provided methods of fabricating a metal silicate layer on a semiconductor substrate using an atomic layer deposition technique. The methods include performing a metal silicate layer formation cycle at least one time in order to form a metal silicate layer having a desired thickness. The metal silicate layer formation cycle includes an operation of repeatedly performing a metal oxide layer formation cycle K times and an operation of repeatedly performing a silicon oxide layer formation cycle Q times. K and Q are integers ranging from 1 to 10 respectively. The metal oxide layer formation cycle includes the steps of supplying a metal source gas to a reactor containing the substrate, exhausting the metal source gas remaining in a reactor to clean the inside of the reactor, and then supplying an oxide gas into the reactor. The silicon oxide layer formation cycle includes supplying a silicon source gas, exhausting the silicon source gas remaining in the reactor to clean the inside of the reactor, and then supplying an oxide gas into the reactor.
摘要翻译：提供了使用原子层沉积技术在半导体衬底上制造金属硅酸盐层的方法。所述方法包括至少一次执行金属硅酸盐层形成循环以形成具有所需厚度的金属硅酸盐层。金属硅酸盐层形成循环包括重复进行金属氧化物层形成循环K次的操作和重复进行氧化硅层形成循环Q次的操作。 K和Q分别为1〜10的整数。金属氧化物层形成循环包括将金属源气体供给到含有基板的反应器，排出留在反应器内的金属源气体，清洗反应器内部，然后向反应器供给氧化气体的工序。氧化硅层形成循环包括提供硅源气体，排出留在反应器中的硅源气体以清洁反应器的内部，然后将氧化物气体供应到反应器中。

8. 发明申请

US20050233598A1 Method of fabricating high-k dielectric layer having reduced impurity 有权
标题翻译：制造具有减少的杂质的高k电介质层的方法
公开(公告)号：US20050233598A1
公开(公告)日：2005-10-20
申请号：US11107559
申请日：2005-04-15
申请人： Hyung-Suk Jung , Jong-Ho Lee , Ha-Jin Lim , Jae-Eun Park , Yun-Seok Kim , Jong-Ho Yang
发明人： Hyung-Suk Jung , Jong-Ho Lee , Ha-Jin Lim , Jae-Eun Park , Yun-Seok Kim , Jong-Ho Yang
IPC分类号： H01L21/31 , C23C16/40 , H01L21/28 , H01L21/314 , H01L21/336 , H01L21/469 , H01L29/51
CPC分类号： H01L21/022 , C23C16/402 , C23C16/45525 , C23C16/45527 , C23C16/45529 , H01L21/0228 , H01L21/02318 , H01L21/28185 , H01L21/28194 , H01L21/3142 , H01L21/3143 , H01L29/513 , H01L29/517 , H01L29/518
摘要： Methods of fabricating high-k dielectric layers having reduced impurities for use in semiconductor applications are disclosed. The methods include the steps of: forming a stacked dielectric layer having a first dielectric layer and a second dielectric layer formed on a semiconductor substrate using an ALD method, in combination with a post-treatment step performed to the stacked dielectric layer. The steps of forming the stacked dielectric layer and performing the post-treatment are repeated at least once, thereby fabricating the high-k dielectric layer.
摘要翻译：公开了制造用于半导体应用的具有减少的杂质的高k电介质层的方法。该方法包括以下步骤：结合对叠层电介质层执行的后处理步骤，使用ALD法形成具有形成在半导体衬底上的第一电介质层和第二电介质层的叠层电介质层。形成堆叠的电介质层并进行后处理的步骤至少重复一次，从而制造高k电介质层。

9. 发明授权

US07396777B2 Method of fabricating high-k dielectric layer having reduced impurity 有权
标题翻译：制造具有减少的杂质的高k电介质层的方法
公开(公告)号：US07396777B2
公开(公告)日：2008-07-08
申请号：US11107559
申请日：2005-04-15
申请人： Hyung-Suk Jung , Jong-Ho Lee , Ha-Jin Lim , Jae-Eun Park , Yun-Seok Kim , Jong-Ho Yang
发明人： Hyung-Suk Jung , Jong-Ho Lee , Ha-Jin Lim , Jae-Eun Park , Yun-Seok Kim , Jong-Ho Yang
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/022 , C23C16/402 , C23C16/45525 , C23C16/45527 , C23C16/45529 , H01L21/0228 , H01L21/02318 , H01L21/28185 , H01L21/28194 , H01L21/3142 , H01L21/3143 , H01L29/513 , H01L29/517 , H01L29/518
摘要： Methods of fabricating high-k dielectric layers having reduced impurities for use in semiconductor applications are disclosed. The methods include the steps of: forming a stacked dielectric layer having a first dielectric layer and a second dielectric layer formed on a semiconductor substrate using an ALD method, in combination with a post-treatment step performed to the stacked dielectric layer. The steps of forming the stacked dielectric layer and performing the post-treatment are repeated at least once, thereby fabricating the high-k dielectric layer.
摘要翻译：公开了制造用于半导体应用的具有减少的杂质的高k电介质层的方法。该方法包括以下步骤：结合对叠层电介质层执行的后处理步骤，使用ALD法形成具有形成在半导体衬底上的第一电介质层和第二电介质层的叠层电介质层。形成堆叠的电介质层并进行后处理的步骤至少重复一次，从而制造高k电介质层。

10. 发明申请

US20060166476A1 Method of forming a dielectric structure having a high dielectric constant and method of manufacturing a semiconductor device having the dielectric structure 有权
标题翻译：具有高介电常数的介电结构的形成方法和具有电介质结构的半导体器件的制造方法
公开(公告)号：US20060166476A1
公开(公告)日：2006-07-27
申请号：US11339416
申请日：2006-01-25
申请人： Jong-Cheol Lee , Sung-Tae Kim , Young-Sun Kim , Cha-Young Yoo , Gab-Jin Nam , Young-Geun Park , Jae-Hyoung Choi , Jae-Hyun Yeo , Ha-Jin Lim , Yun-Seok Kim
发明人： Jong-Cheol Lee , Sung-Tae Kim , Young-Sun Kim , Cha-Young Yoo , Gab-Jin Nam , Young-Geun Park , Jae-Hyoung Choi , Jae-Hyun Yeo , Ha-Jin Lim , Yun-Seok Kim
IPC分类号： H01L21/471
CPC分类号： H01L21/022 , C23C14/5826 , C23C14/586 , C23C16/56 , H01L21/02142 , H01L21/02252 , H01L21/28273 , H01L21/3141 , H01L21/3143 , H01L21/31645 , H01L27/10852 , H01L27/10873 , H01L27/115 , H01L27/11521 , H01L28/40 , H01L29/513 , H01L29/517 , H01L29/78
摘要： In a method of manufacturing a dielectric structure, after a first dielectric layer is formed on a substrate by using a metal oxide doped with silicon, the substrate is placed on a susceptor of a chamber. By treating the first dielectric layer with a plasma in controlling a voltage difference between the susceptor and a ground, a second dielectric layer is formed on the first dielectric layer. The second dielectric layer including a metal oxynitride doped with silicon having enough content of nitrogen is formed on the first dielectric layer. Therefore, dielectric properties of the dielectric structure comprising the first and the second dielectric layers can be improved and a leakage current can be greatly decreased. By adapting the dielectric structure to a gate insulation layer and/or to a dielectric layer of a capacitor or of a non-volatile semiconductor memory device, capacitances and electrical properties can be improved.
摘要翻译：在制造电介质结构的方法中，在通过使用掺杂有硅的金属氧化物在基板上形成第一介电层之后，将基板放置在室的基座上。通过在控制基座和接地之间的电压差的同时用等离子体处理第一电介质层，在第一电介质层上形成第二电介质层。在第一电介质层上形成包括掺杂有足够的氮含量的硅的金属氮氧化物的第二电介质层。因此，可以提高包括第一和第二电介质层的电介质结构的介电性能，并且可以大大降低泄漏电流。通过使电介质结构适应于栅极绝缘层和/或电容器或非易失性半导体存储器件的电介质层，可以提高电容和电性能。

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