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1. 发明授权

US06537914B1 Integrated circuit device isolation methods using high selectivity chemical-mechanical polishing 有权
标题翻译：集成电路器件隔离方法采用高选择性化学机械抛光
公开(公告)号：US06537914B1
公开(公告)日：2003-03-25
申请号：US09570225
申请日：2000-05-12
申请人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee , Jung-yup Kim , Chang-ki Hong , Ho-kyu Kang
发明人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee , Jung-yup Kim , Chang-ki Hong , Ho-kyu Kang
IPC分类号： H01L21302
CPC分类号： C09G1/02 , C09K3/1463 , H01L21/31053 , H01L21/76224
摘要： Trench isolation methods for integrated circuits may reduce irregularities in the formation of an isolation layer through use of a high selectivity chemical-mechanical polishing (CMP) operation. In particular, a substrate surface is etched to form a trench. An insulation layer is then formed on the substrate surface and in the trench. The insulation layer is chemical-mechanical polished using a slurry that includes a CeO2 group abrasive to form an isolation layer in the trench. The CMP selectivity ratio of a slurry that includes a CeO2 group abrasive may be sufficient to allow the substrate surface to be used as a CMP stop. As a result, a more consistent level of polishing may be maintained over the substrate surface, which may result in a more uniform thickness in the isolation layer.
摘要翻译：用于集成电路的沟槽隔离方法可以通过使用高选择性化学机械抛光（CMP）操作来减少形成隔离层的不规则性。特别地，蚀刻衬底表面以形成沟槽。然后在衬底表面和沟槽中形成绝缘层。绝缘层使用包含CeO 2基团研磨剂的浆料进行化学机械抛光，以在沟槽中形成隔离层。包括CeO 2基研磨剂的浆料的CMP选择比可能足以使基板表面用作CMP停止。结果，可以在衬底表面上保持更一致的抛光水平，这可能导致隔离层中更均匀的厚度。

2. 发明授权

US5847424A Capacitor of semiconductor memory device and manufacturing method thereof 失效
标题翻译：半导体存储器件的电容器及其制造方法
公开(公告)号：US5847424A
公开(公告)日：1998-12-08
申请号：US589712
申请日：1996-01-24
申请人： Ho-kyu Kang
发明人： Ho-kyu Kang
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L27/108
CPC分类号： H01L27/10852
摘要： A capacitor structure of a DRAM device and a method thereof, including a first electrode formed in each unit memory cell to be connected to a source of a transistor, a deteriorating prevention film formed at the lowermost surface of the first electrode, exclusive of a portion where the first electrode is connected to the source of a transistor, an underlayer formed beneath the deterioration prevention film, an undercut formed between the underlayer and deterioration prevention film, a high-dielectric film formed on surfaces of the first electrode, underlayer and deterioration prevention film which is exposed by the undercut, a reaction/diffusion prevention film formed on the high-dielectric film, formed on the first electrode and underlayer, exclusive of an area around the undercut, and a second electrode formed on the entire surface of the high-dielectric film and reaction/diffusion prevention film, thereby preventing increase of leakage current amount caused by the undercut formed during the capacitor manufacturing process.
摘要翻译：一种DRAM器件的电容器结构及其方法，包括形成在每个单元存储单元中以连接到晶体管源极的第一电极，形成在第一电极的最下表面处的劣化防止膜，不包括部分其中第一电极连接到晶体管的源极，在劣化防止膜下方形成的底层，形成在底层和劣化防止膜之间的底切，形成在第一电极，底层和防止劣化的表面上的高介电膜通过底切暴露的膜，形成在第一电极和下层上的形成在高电介质膜上的反应/扩散防止膜，不包括底切周围的区域，以及形成在高电介质膜的整个表面上的第二电极 - 电介质膜和反应/扩散膜，从而防止由形成的底切造成的漏电流量的增加环形电容器制造工艺。

3. 发明申请

US20070004133A1 Capacitor for a semiconductor device and method of fabricating same 失效
公开(公告)号：US20070004133A1
公开(公告)日：2007-01-04
申请号：US11519615
申请日：2006-09-12
申请人： Hong-Ki Kim , Ho-Kyu Kang , Moon-Han Park , Myong-Geun Yoon , Seok-Jun Won , Yong-Kuk Jeong , Kyung-Hun Kim
发明人： Hong-Ki Kim , Ho-Kyu Kang , Moon-Han Park , Myong-Geun Yoon , Seok-Jun Won , Yong-Kuk Jeong , Kyung-Hun Kim
IPC分类号： H01L21/8242 , H01L21/44
CPC分类号： H01L27/10852 , H01L27/10811 , H01L27/10888 , H01L27/10894 , H01L27/10897 , H01L28/55 , H01L28/60 , H01L28/75
摘要： A capacitor includes an upper electrode formed by physical vapor deposition and chemical vapor deposition. The upper electrode of the capacitor may include a first upper electrode formed by chemical vapor deposition and a second upper electrode formed by physical vapor deposition. Alternatively, the upper electrode may include a first upper electrode formed by physical vapor deposition and a second upper electrode formed by chemical vapor deposition. The upper electrode of the capacitor is formed through two steps using chemical vapor deposition and physical vapor deposition. Therefore, the upper electrode can be thick and rapidly formed, whereby electrical characteristics of the upper electrode are not deteriorated.

4. 发明授权

US07052967B2 Method for fabricating capacitor array preventing crosstalk between adjacent capacitors in semiconductor device 失效
公开(公告)号：US07052967B2
公开(公告)日：2006-05-30
申请号：US10394139
申请日：2003-03-24
申请人： Hae-jeong Lee , Ho-kyu Kang
发明人： Hae-jeong Lee , Ho-kyu Kang
IPC分类号： H01L21/20
CPC分类号： H01L21/764 , H01L27/0805 , H01L28/90
摘要： A capacitor array of a semiconductor device including a plurality of capacitors is provided. The capacitor array includes a plurality of lower electrodes, which are formed over a semiconductor substrate. A dielectric layer formed over the lower electrodes, and an upper electrode formed over the dielectric layer. The plurality of lower electrodes are insulated from each other either by an insulating layer having pores of a low dielectric constant, or by an air gap.

5. 发明申请

US20050142706A1 Method of preventing semiconductor layers from bending and semiconductor device formed thereby 有权
公开(公告)号：US20050142706A1
公开(公告)日：2005-06-30
申请号：US11059884
申请日：2005-02-17
申请人： Dong-Ho Ahn , Ho-Kyu Kang , Geum-Jong Bae
发明人： Dong-Ho Ahn , Ho-Kyu Kang , Geum-Jong Bae
IPC分类号： H01L21/76 , H01L21/265 , H01L21/316 , H01L21/762 , H01L27/12 , H01L29/786 , H01L21/00 , H01L21/84
CPC分类号： H01L21/76235 , H01L21/02238 , H01L21/02255 , H01L21/31662 , H01L21/76264 , H01L21/76283 , H01L27/1203
摘要： Disclosed herein are various methods for preventing bending of a patterned SOI layer during trench sidewall oxidation, the methods comprising providing a patterned SOI layer having at least one trench, said patterned SOI layer disposed upon an underlying buried silicon oxide layer; and blocking diffusion of oxygen between said patterned SOI and buried silicon oxide layer.

6. 发明授权

US5966614A Silicon nitride-free isolation methods for integrated circuits 失效
标题翻译：集成电路无氮化物隔离方法
公开(公告)号：US5966614A
公开(公告)日：1999-10-12
申请号：US934241
申请日：1997-09-19
申请人： Tai-su Park , Ho-kyu Kang
发明人： Tai-su Park , Ho-kyu Kang
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76232 , Y10S438/959
摘要： Trench isolation methods for integrated circuit substrates may be simplified by eliminating the steps of forming a silicon nitride layer, etching the silicon nitride layer and removing the silicon nitride layer. In particular, a silicon nitride-free mask pattern, such as a photoresist mask pattern, may be formed on a silicon nitride-free integrated circuit substrate. The silicon nitride-free integrated circuit substrate is etched through the silicon nitride-free mask pattern to form a trench in the substrate. An insulating layer is formed in the trench and is chemical-mechanical polished to form a trench isolating layer. By eliminating the silicon nitride layer, simplified processing and improved performance may be obtained.
摘要翻译：通过消除形成氮化硅层的步骤，蚀刻氮化硅层和去除氮化硅层，可以简化用于集成电路基板的沟槽隔离方法。特别地，不含氮化硅的掩模图案，例如光致抗蚀剂掩模图案，可以形成在无氮化硅的集成电路基板上。通过无氮化硅的掩模图案蚀刻无氮化硅的集成电路衬底，以在衬底中形成沟槽。在沟槽中形成绝缘层，并进行化学机械抛光以形成沟槽隔离层。通过消除氮化硅层，可以获得简化的处理和改进的性能。

7. 发明申请

US20150041944A1 IMAGE SENSOR, FABRICATING METHOD THEREOF, AND DEVICE COMPRISING THE IMAGE SENSOR 审中-公开
标题翻译：图像传感器，其制造方法和包含图像传感器的装置
公开(公告)号：US20150041944A1
公开(公告)日：2015-02-12
申请号：US14479885
申请日：2014-09-08
申请人： Hong-ki KIM , Ho-Kyu KANG , June-taeg LEE , Jae-Hee CHOI
发明人： Hong-ki KIM , Ho-Kyu KANG , June-taeg LEE , Jae-Hee CHOI
IPC分类号： H01L27/146 , H01L23/00
CPC分类号： H01L27/14636 , H01L23/564 , H01L27/14618 , H01L27/14621 , H01L27/14632 , H01L27/14638 , H01L27/1464 , H01L27/14687 , H01L2224/48095 , H01L2224/48227 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： Image sensor, fabricating method thereof, and device comprising the image sensor are provided, which comprises a substrate in which a photoelectric transformation device is formed, an interconnection structure formed on the substrate and including multiple intermetal dielectric layers and multiple metal interconnections placed in the multiple intermetal dielectric layers, the interconnection structure defining a cavity aligned corresponding to the photoelectric transformation device, a moisture absorption barrier layer conformally formed on a top of the interconnection structure and in the cavity; and a light guide unit formed on the moisture absorption barrier layer and including light transmittance material filling the cavity, wherein the moisture absorption barrier layer is formed with a uniform thickness on both sides and a bottom of the cavity and on a top surface of the multiple intermetal dielectric layer.
摘要翻译：提供了图像传感器及其制造方法以及包括图像传感器的装置，其包括形成有光电转换装置的基板，形成在基板上的互连结构，并且包括多个金属间介电层和多个金属互连金属间电介质层，所述互连结构限定对应于所述光电转换装置对准的空腔;保形地形成在所述互连结构的顶部和所述空腔中的吸湿阻挡层; 以及导光单元，其形成在吸湿阻挡层上并且包括填充空腔的透光材料，其中吸湿阻挡层在空腔的两侧和底部以及多个顶部表面上形成均匀的厚度金属间电介质层。

8. 发明授权

US07112849B2 Method of preventing semiconductor layers from bending and semiconductor device formed thereby 有权
标题翻译：防止半导体层弯曲的方法和由此形成的半导体器件
公开(公告)号：US07112849B2
公开(公告)日：2006-09-26
申请号：US11059884
申请日：2005-02-17
申请人： Dong-Ho Ahn , Ho-Kyu Kang , Geum-Jong Bae
发明人： Dong-Ho Ahn , Ho-Kyu Kang , Geum-Jong Bae
IPC分类号： H01L27/01
CPC分类号： H01L21/76235 , H01L21/02238 , H01L21/02255 , H01L21/31662 , H01L21/76264 , H01L21/76283 , H01L27/1203
摘要： Disclosed herein are various methods for preventing bending of a patterned SOI layer during trench sidewall oxidation, the methods comprising providing a patterned SOI layer having at least one trench, said patterned SOI layer disposed upon an underlying buried silicon oxide layer; and blocking diffusion of oxygen between said patterned SOI and buried silicon oxide layer.
摘要翻译：本文公开了用于在沟槽侧壁氧化期间防止图案化SOI层弯曲的各种方法，所述方法包括提供具有至少一个沟槽的图案化SOI层，所述图案化SOI层设置在下面的掩埋氧化硅层上; 并阻止氧在所述图案化SOI和掩埋氧化硅层之间的扩散。

9. 发明授权

US06930343B2 Nonvolatile memory device utilizing a vertical nanotube 有权
标题翻译：利用垂直纳米管的非易失性存储器件
公开(公告)号：US06930343B2
公开(公告)日：2005-08-16
申请号：US10713214
申请日：2003-11-17
申请人： Won-bong Choi , Jo-won Lee , Ho-kyu Kang , Chung-woo Kim
发明人： Won-bong Choi , Jo-won Lee , Ho-kyu Kang , Chung-woo Kim
IPC分类号： H01L21/8247 , G11C8/02 , G11C13/02 , G11C16/04 , H01L27/115 , H01L29/02 , H01L29/788 , H01L29/792 , H01L51/30 , H01L27/108
CPC分类号： G11C13/025 , B82Y10/00 , G11C16/0466 , G11C2213/16 , G11C2213/17 , H01L29/02 , H01L29/792 , H01L29/7923 , H01L29/7926 , H01L51/0048 , H01L51/0512 , Y10S977/943
摘要： A nonvolatile memory device includes a substrate having a source region; a nanotube array including a plurality of nanotube columns that are vertically grown on the substrate such that a first end of the nanotube array is in contact with the source region, the nanotube array functioning as an electron transport channel; a memory cell formed around an outer side surface of the nanotube array; a control gate formed around an outer side surface of the memory cell; and a drain region in contact with a second end of the nanotube array and the memory cell, wherein the second end of the nanotube array is distal to the first end of the nanotube array.
摘要翻译：非易失性存储器件包括具有源极区域的衬底; 纳米管阵列，其包括在所述基板上垂直生长的多个纳米管柱，使得所述纳米管阵列的第一端与所述源极区域接触，所述纳米管阵列用作电子传输通道; 形成在所述纳米管阵列的外侧面的记忆单元; 形成在所述存储单元的外侧表面上的控制栅; 以及与纳米管阵列和存储单元的第二端接触的漏极区，其中纳米管阵列的第二端远离纳米管阵列的第一端。

10. 发明授权

US06563190B1 Capacitor array preventing crosstalk between adjacent capacitors in semiconductor device 有权
标题翻译：电容阵列防止半导体器件中相邻电容器之间的串扰
公开(公告)号：US06563190B1
公开(公告)日：2003-05-13
申请号：US09669964
申请日：2000-09-26
申请人： Hae-jeong Lee , Ho-kyu Kang
发明人： Hae-jeong Lee , Ho-kyu Kang
IPC分类号： H01L2900
CPC分类号： H01L21/764 , H01L27/0805 , H01L28/90
摘要： A capacitor array of a semiconductor device including a plurality of capacitors is provided. The capacitor array includes a plurality of lower electrodes, which are formed over a semiconductor substrate. A dielectric layer formed over the lower electrodes, and an upper electrode formed over the dielectric layer. The plurality of lower electrodes are insulated from each other either by an insulating layer having pores of a low dielectric constant, or by an air gap.
摘要翻译：提供了包括多个电容器的半导体器件的电容器阵列。电容器阵列包括形成在半导体衬底上的多个下电极。形成在下电极上的电介质层和形成在电介质层上的上电极。多个下电极通过具有低介电常数的孔的绝缘层或通过气隙彼此绝缘。

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