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1. 发明申请

US20040150611A1 Display device and a driver circuit thereof 有权
标题翻译：显示装置及其驱动电路
公开(公告)号：US20040150611A1
公开(公告)日：2004-08-05
申请号：US10762082
申请日：2004-01-21
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Yukio Tanaka
IPC分类号： G09G005/00 , G09G003/36
CPC分类号： G09G3/3688 , G09G3/3633 , G09G2310/027 , G09G2310/0283
摘要： To provide a driver circuit that is simple and possessing a small surface area. The driver circuit comprises a shift register circuit and a plurality of latch circuits. The shift register circuit is composed of a plurality of register circuits having a clocked inverter circuit and an inverter circuit connected in series. The plurality of digital data latch circuits has a first N-channel Tr and a second N-channel Tr of which the sources or the drains are connected in series, a P-channel Tr, and a data holding circuit. The clocked inverter circuit and the inverter circuit generate a timing signal on the basis of a clock signal and a start pulse to thereby feed the timing signal to the register circuit neighboring a register circuit and to a gate electrode of the first N-channel Tr and the P-channel Tr feeds a first electric voltage to the data holding circuit in accordance with a Res signal inputted to the gate electrode. The second N-channel Tr then takes in digital data on the basis of the timing signal to thereby output the digital data to the source or the drain of the first N-channel Tr. The timing signal outputted from the register circuit neighboring a register circuit is fed to the gate electrode of the first N-channel Tr.
摘要翻译：提供简单且具有小表面积的驱动电路。驱动器电路包括移位寄存器电路和多个锁存电路。移位寄存器电路由具有时钟反相器电路和串联连接的反相器电路的多个寄存器电路组成。多个数字数据锁存电路具有其源极或漏极串联连接的第一N沟道Tr和第二N沟道Tr，P沟道Tr和数据保持电路。时钟反相器电路和反相器电路基于时钟信号和起始脉冲产生定时信号，从而将定时信号馈送到与寄存器电路相邻的寄存器电路和第一N沟道Tr的栅电极， P沟道Tr根据输入到栅电极的Res信号向数据保持电路馈送第一电压。第二N信道Tr然后基于定时信号接收数字数据，从而将数字数据输出到第一N信道Tr的源或漏极。从与寄存器电路相邻的寄存器电路输出的定时信号被馈送到第一N沟道Tr的栅电极。

2. 发明申请

US20030064552A1 Active matrix type semiconductor display device 有权
公开(公告)号：US20030064552A1
公开(公告)日：2003-04-03
申请号：US10295886
申请日：2002-11-18
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Yukio Tanaka , Shou Nagao
IPC分类号： H01L021/00 , H01L021/84
CPC分类号： G09G3/3233 , G02F2001/134318 , G09G3/3225 , G09G3/3614 , G09G3/3655 , G09G2300/0465 , G09G2300/0842 , G09G2310/0254 , G09G2310/0262 , G09G2330/021 , H01L27/12 , H01L27/1277
摘要： There is provided an active matrix type semiconductor display device which realizes low power consumption and high reliability. In the active matrix type semiconductor display device of the present invention, a counter electrode is divided into two, different potentials are applied to the two counter electrodes, respectively and inversion driving is carried out each other. Since a potential of an image signal can be made low by doing so, it is possible to lower a voltage necessary for operation of a driver circuit. As a result, it is possible to realize improvement of reliability of an element such as a TFT and reduction of consumed electric power. Moreover, since it is possible to lower a voltage of a timing pulse supplied by the driver circuit, a booster circuit can be omitted, and reduction of an area of the driver circuit can be realized.

3. 发明申请

US20020186157A1 D/A converter circuit and semiconductor device 有权
标题翻译： D / A转换器电路和半导体器件
公开(公告)号：US20020186157A1
公开(公告)日：2002-12-12
申请号：US10106924
申请日：2002-03-25
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Yukio Tanaka
IPC分类号： H03M001/66
CPC分类号： H03M1/687 , H03M1/765 , H03M1/804
摘要： Provided is a D/A converter circuit which copes with high-bit digital signals and has favorable linearity and small occupation area. In a capacitive divider type DAC, capacitances are simply provided in a one-to-one relationship correspondingly to lower order bit digital signals instead of providing capacitances one-to-one correspondingly to bits. In a reset period, voltages having a height corresponding to higher order bit digital signals are provided to one electrodes (first electrodes) of the capacitances thereby charging the capacitances. In a write period, voltages having a height corresponding to lower order bit digital signals are provided to the other electrodes (second electrodes) of the capacitances thereby charging the capacitances.
摘要翻译：提供了一种适用于高位数字信号的D / A转换电路，具有良好的线性和占用面积小的特点。在电容分压器型DAC中，相对于低位位数字信号，电容以简单的一对一关系提供，而不是相对于位提供一对一的电容。在复位期间，具有对应于高位位数字信号的高度的电压被提供给电容的一个电极（第一电极），由此对电容进行充电。在写入期间，将具有与低位位数字信号对应的高度的电压提供给电容的其他电极（第二电极），由此对电容充电。

4. 发明申请

US20030117363A1 Display device and a driver circuit thereof 有权
公开(公告)号：US20030117363A1
公开(公告)日：2003-06-26
申请号：US10277402
申请日：2002-10-22
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Yukio Tanaka
IPC分类号： G09G003/36
CPC分类号： G09G3/3688 , G09G3/3633 , G09G2310/027 , G09G2310/0283
摘要： To provide a driver circuit that is simple and possessing a small surface area. The driver circuit comprises a shift register circuit and a plurality of latch circuits. The shift register circuit is composed of a plurality of register circuits having a clocked inverter circuit and an inverter circuit connected in series. The plurality of digital data latch circuits has a first N-channel Tr and a second N-channel Tr of which the sources or the drains are connected in series, a P-channel Tr, and a data holding circuit. The clocked inverter circuit and the inverter circuit generate a timing signal on the basis of a clock signal and a start pulse to thereby feed the timing signal to the register circuit neighboring a register circuit and to a gate electrode of the first N-channel Tr and the P-channel Tr feeds a first electric voltage to the data holding circuit in accordance with a Res signal inputted to the gate electrode. The second N-channel Tr then takes in digital data on the basis of the timing signal to thereby output the digital data to the source or the drain of the first N-channel Tr. The timing signal outputted from the register circuit neighboring a register circuit is fed to the gate electrode of the first N-channel Tr.

5. 发明申请

US20040178978A1 D/A conversion circuit and semiconductor device 失效
公开(公告)号：US20040178978A1
公开(公告)日：2004-09-16
申请号：US10810573
申请日：2004-03-29
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Jun Koyama , Mitsuaki Osame , Yukio Tanaka , Munehiro Azami , Naoko Yano , Shou Nagao
IPC分类号： G09G003/36
CPC分类号： H01L27/1214 , G09G3/20 , G09G3/2011 , G09G3/3677 , G09G3/3688 , G09G2310/0218 , G09G2310/027 , G09G2310/0297 , H01L21/84 , H01L29/04 , H03K17/6872 , H03K17/693 , H03M1/682 , H03M1/765
摘要： A D/A conversion circuit with a small area is provided. In the D/A conversion circuit, according to a digital signal transmitted from address lines of an address decoder, one of four gradation voltage lines is selected. A circuit including two N-channel TFTs is connected in series to a circuit including two P-channel TFT, and a circuit including the circuits connected in series to each other is connected in parallel to each of the gradation voltage lines. Further, an arrangement of the circuit including the two N-channel TFTs and the circuit including the two P-channel TFTs is reversed for every gradation voltage line. By this, the crossings of wiring lines in the D/A conversion circuit becomes small and the area can be made small.

6. 发明申请

US20030197179A1 Semiconductor device and fabrication method thereof 失效
公开(公告)号：US20030197179A1
公开(公告)日：2003-10-23
申请号：US10456633
申请日：2003-06-09
申请人： Semiconductor Energy
发明人： Shunpei Yamazaki , Satoshi Murakami , Jun Koyama , Yukio Tanaka , Hidehito Kitakado , Hideto Ohnuma
IPC分类号： G02F001/136 , H01L029/04 , H01L031/20
CPC分类号： G02F1/1368 , G02F1/133345 , G02F1/13454 , G02F1/136227 , G02F1/136286 , G02F2201/123 , G02F2202/104 , H01L27/12 , H01L27/1222 , H01L27/124 , H01L27/1248 , H01L27/1259 , H01L27/3248 , H01L27/3258 , H01L27/3262 , H01L27/3272 , H01L27/3276 , H01L29/458 , H01L29/78621 , H01L29/78627 , H01L29/78675 , H01L2029/7863 , H01L2227/323
摘要： This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant to hot carrier injection is achieved. LDD regions 717, 718, 719 and 720 not overlapping with a gate wiring are arranged in an n-channel TFT 804 forming a pixel unit. As a result, a TFT structure having a small OFF current value is achieved. In this instance, an element belonging to the Group 15 of the Periodic Table exists in a higher concentration in the LDD region 707 than in the LDD regions 717, 718, 719 and 720.

7. 发明申请

US20040115851A1 Active matrix type semiconductor display device 有权
标题翻译：有源矩阵型半导体显示装置
公开(公告)号：US20040115851A1
公开(公告)日：2004-06-17
申请号：US10618850
申请日：2003-07-15
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Yukio Tanaka , Shou Nagao
IPC分类号： H01L021/00
CPC分类号： G09G3/3233 , G02F2001/134318 , G09G3/3225 , G09G3/3614 , G09G3/3655 , G09G2300/0465 , G09G2300/0842 , G09G2310/0254 , G09G2310/0262 , G09G2330/021 , H01L27/12 , H01L27/1277
摘要： There is provided an active matrix type semiconductor display device which realizes low power consumption and high reliability. In the active matrix type semiconductor display device of the present invention, a counter electrode is divided into two, different potentials are applied to the two counter electrodes, respectively and inversion driving is carried out each other. Since a potential of an image signal can be made low by doing so, it is possible to lower a voltage necessary for operation of a driver circuit. As a result, it is possible to realize improvement of reliability of an element such as a TFT and reduction of consumed electric power. Moreover, since it is possible to lower a voltage of a timing pulse supplied by the driver circuit, a booster circuit can be omitted, and reduction of an area of the driver circuit can be realized.
摘要翻译：提供了实现低功耗和高可靠性的有源矩阵型半导体显示装置。在本发明的有源矩阵型半导体显示装置中，对置电极分为两个，分别对两个对置电极施加不同的电位，并进行反向驱动。由于可以通过这样做使图像信号的电位变低，所以可以降低驱动电路的操作所需的电压。结果，可以实现诸如TFT的元件的可靠性的提高和消耗的电力的减少。此外，由于可以降低由驱动器电路提供的定时脉冲的电压，因此可以省略升压电路，并且可以实现驱动电路的面积的减小。

8. 发明申请

US20030137482A1 Shift register circuit, driving circuit of display device and display device using the driving circuit 失效
标题翻译：移位寄存器电路，显示装置的驱动电路和使用驱动电路的显示装置
公开(公告)号：US20030137482A1
公开(公告)日：2003-07-24
申请号：US10355404
申请日：2003-01-31
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Yukio Tanaka , Keisuke Hayashi
IPC分类号： G09G003/36
CPC分类号： G11C19/00 , G09G3/20 , G09G3/3677 , G09G3/3688 , G09G2300/0408 , G09G2310/0224 , G09G2310/027 , G09G2310/0281 , G11C19/28 , H01L27/12 , H01L27/1214
摘要： There is provided a driving circuit which is simple and has a small occupied area. A shift register circuit of the present invention includes a plurality of register circuits. Each of the register circuits includes a clocked inverter circuit and an inverter circuit. Both are connected in series with each other so that an output signal of the clocked inverter circuit becomes an input signal of the inverter circuit. Further, the register circuit includes a signal line by which an output signal of the inverter circuit is transmitted. Since a number of elements are connected to the signal line and parasitic capacitance is large, it has a high load. The shift register circuit of the present invention uses the fact that since the parasitic capacitance of the signal line is large, it has a high load.
摘要翻译：提供了一种简单且占用面积小的驱动电路。本发明的移位寄存器电路包括多个寄存器电路。每个寄存器电路包括时钟反相器电路和反相器电路。两者彼此串联连接，使得时钟反相器电路的输出信号变为逆变器电路的输入信号。此外，寄存器电路包括发送反相器电路的输出信号的信号线。由于许多元件连接到信号线并且寄生电容大，所以它具有高负载。本发明的移位寄存器电路使用由于信号线的寄生电容大而具有高负载的事实。

9. 发明申请

US20020067300A1 D/A conversion circuit and semiconductor device 有权
公开(公告)号：US20020067300A1
公开(公告)日：2002-06-06
申请号：US10034797
申请日：2001-12-28
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Yukio Tanaka
IPC分类号： H03M001/78
CPC分类号： H03M1/66 , G09G3/2011 , G09G3/3688 , G09G2310/027 , G09G2310/0289 , H03M1/662 , H03M1/682 , H03M1/765
摘要： A D/A conversion circuit in accordance with the present invention, which is provided with a switch swD, allows a writing operation of a voltage (a true gradation voltage) to be performed at a higher speed by first applying a first voltage (a voltage close to the true gradation voltage), which is supplied without passing through a resistor element, to an output line and then applying a second voltage (the true gradation voltage), which is supplied via the resistor element, to the output line. Thus, the present invention can provide a D/A conversion circuit capable of writing display data to liquid crystal cells with higher precision at higher speed, and a semiconductor device utilizing such a D/A conversion circuit.

10. 发明申请

US20030201439A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20030201439A1
公开(公告)日：2003-10-30
申请号：US10446187
申请日：2003-05-28
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Shunpei Yamazaki , Yukio Tanaka , Jun Koyama , Mitsuaki Osame , Satoshi Murakami , Hideto Ohnuma , Etsuko Fujimoto , Hidehito Kitakado
IPC分类号： H01L021/00 , H01L029/04 , H01L031/036
CPC分类号： G02F1/13454 , G02F1/136209 , G02F1/136213 , H01L27/1255 , H01L27/3244 , H01L27/3248 , H01L27/3265 , H01L27/3272 , H01L29/66757 , H01L29/78621 , H01L29/78624 , H01L29/78627 , H01L29/78633 , H01L29/78645 , H01L29/78675 , H01L51/5246 , H01L51/5284 , H01L2227/323
摘要： A semiconductor device in which TFT's of suitable structures are arranged depending upon the performances of the circuits, and storage capacitors are formed occupying small areas, the semiconductor device featuring high performance and bright image. The thickness of the gate-insulating film is differed depending upon a circuit that gives importance to the operation speed and a circuit that gives importance to the gate-insulating breakdown voltage, and the position for forming the LDD region is differed depending upon the TFT that gives importance to the countermeasure against the hot carriers and the TFT that gives importance to the countermeasure against the off current. This makes it possible to realize a semiconductor device of high performance. Further, the storage capacity is formed by a light-shielding film and an oxide thereof to minimize its area, and a semiconductor device capable of displaying a bright picture is realized.
摘要翻译：一种半导体器件，其中根据电路的性能布置适当结构的TFT，并且存储电容器占据小面积，该半导体器件具有高性能和明亮的图像。栅极绝缘膜的厚度取决于重视操作速度的电路和重要的栅极绝缘击穿电压的电路，并且用于形成LDD区域的位置取决于TFT的TFT而不同重视对抗热门运营商和TFT的对策，重点针对当前的对策。这使得可以实现高性能的半导体器件。此外，存储容量由遮光膜和其氧化物形成，以使其面积最小化，并且实现了能够显示亮画面的半导体器件。

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