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1. 发明授权

US5166087A Method of fabricating semiconductor element having lightly doped drain (LDD) without using sidewalls 失效
标题翻译：在不使用边缘的情况下制造具有轻型排水（LDD）的半导体元件的方法
公开(公告)号：US5166087A
公开(公告)日：1992-11-24
申请号：US820076
申请日：1992-01-13
申请人： Seizo Kakimoto , Katsuji Iguchi , Sung T. Ahn
发明人： Seizo Kakimoto , Katsuji Iguchi , Sung T. Ahn
IPC分类号： H01L21/265 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/26586
摘要： A method of fabricating an insulating gate type field-effect transistor in which a region having a low carrier density for mitigating electric field is provided so as to abut on a source/drain region having a high carrier density, the method comprising the steps of: forming a gate insulating film and a gate electrode on a semiconductor substrate; depositing an insulating thin film on the gate electrode and the gate insulating film to a vertical thickness; and performing from above the insulating thin film, ion implantation at an implantation energy inducing a projected range of ions approximately equal to the vertical thickness of the insulating thin film so as to form the source/drain region; wherein a horizontal thickness of the insulating thin film on opposite sides of the gate electrode is larger than a sum of a lateral diffusion distance of the source/drain region at the time of the ion implantation and a lateral diffusion distance of the source/drain region after the ion implantation.

2. 发明授权

US5298435A Application of electronic properties of germanium to inhibit n-type or p-type diffusion in silicon 失效
标题翻译：锗的电子性质的应用可以抑制硅中的n型或p型扩散
公开(公告)号：US5298435A
公开(公告)日：1994-03-29
申请号：US939982
申请日：1992-09-03
申请人： Sheldon Aronowitz , Courtney L. Hart , Sung T. Ahn
发明人： Sheldon Aronowitz , Courtney L. Hart , Sung T. Ahn
IPC分类号： H01L21/22 , H01L21/265 , H01L29/161
CPC分类号： H01L21/26506 , H01L21/22 , H01L29/161 , Y10S438/914 , Y10S438/938 , Y10S438/965
摘要： A method of inhibiting dopant diffusion in silicon using germanium is provided. Germanium is distributed in substitutional sites in a silicon lattice to form two regions of germanium interposed between a region where dopant is to be introduced and a region from which dopant is to be excluded, the two germanium regions acting as a dopant diffusion barrier.
摘要翻译：提供了使用锗抑制硅中的掺杂剂扩散的方法。锗分布在硅晶格中的取代位置，以形成两个锗区域，这两个区域插入在要引入掺杂剂的区域和掺杂剂被排除的区域之间，两个锗区域充当掺杂剂扩散势垒。

3. 发明授权

US5342796A Method for controlling gate size for semiconduction process 失效
标题翻译：控制半导体栅极尺寸的方法
公开(公告)号：US5342796A
公开(公告)日：1994-08-30
申请号：US887753
申请日：1992-05-27
申请人： Sung T. Ahn , Shigeki Hayashida
发明人： Sung T. Ahn , Shigeki Hayashida
IPC分类号： H01L21/336 , H01L21/265
CPC分类号： H01L29/66613
摘要： A method for preparing a semiconductor device comprises the following steps: (I) depositing at least nitride film on the whole surface of a semiconductor substrate having a field oxide film, (II) removing a portion of the nitride film from a gate-formation region to form an opening at the nitride film up to the substrate, (III) thereafter forming by selective oxidation a vertically projecting oxide film on the substrate at the opening portion, (IV) then removing all the films including the oxide film and the nitride film each covering the substrate to form a dug part of the substrate at the gate formation region, (V) providing on the dug part a gate oxide film and a gate electrode in the order, (VI) doping an impurity ion into the substrate in a manner of self-alignment using the gate electrode as a mask, and (VII) applying heat treatment to the substrate to form an impurity-diffused region.
摘要翻译：一种制备半导体器件的方法包括以下步骤：（I）在具有场氧化膜的半导体衬底的整个表面上至少沉积氮化物膜，（II）从栅极形成区域去除一部分氮化物膜在氮化膜上形成直到基板的开口，（III）然后通过选择性氧化在开口部分的基板上形成垂直突出的氧化膜，（IV），然后除去包括氧化物膜和氮化物膜的所有膜每个覆盖衬底以在栅极形成区域形成衬底的挖出部分，（V）按顺序在栅极氧化膜和栅电极上提供栅极氧化物膜和栅电极;（VI）以杂质离子掺杂到衬底中使用栅电极作为掩模的自对准方式，（VII）对基板进行热处理以形成杂质扩散区域。

4. 发明授权

US5280185A Application of electronic properties of germanium to inhibit n-type or p-type diffusion in silicon 失效
标题翻译：锗的电子性质的应用可以抑制硅中的n型或p型扩散
公开(公告)号：US5280185A
公开(公告)日：1994-01-18
申请号：US738798
申请日：1991-07-31
申请人： Sheldon Aronowitz , Courtney L. Hart , Sung T. Ahn
发明人： Sheldon Aronowitz , Courtney L. Hart , Sung T. Ahn
IPC分类号： H01L21/22 , H01L21/225 , H01L21/265 , H01L29/161 , H01L31/117 , H01L29/167 , H01L29/207 , H01L29/227
CPC分类号： H01L29/161 , H01L21/22 , H01L21/26506
摘要： A structure of inhibiting dopant diffusion in silicon using germanium is provided. Germanium is distributed in substitutional sites in a silicon lattice to form two regions of germanium interposed between a region where dopant is to be introduced and a region from which dopant is to be excluded, the two germanium regions acting as a dopant diffusion barrier.
摘要翻译：提供了使用锗抑制硅中的掺杂剂扩散的结构。锗分布在硅晶格中的取代位置，以形成两个锗区域，这两个区域插入在要引入掺杂剂的区域和掺杂剂被排除的区域之间，两个锗区域充当掺杂剂扩散势垒。

5. 发明授权

US5095358A Application of electronic properties of germanium to inhibit N-type or P-type diffusion in silicon 失效
标题翻译：锗的电子性质在硅中抑制N型或P型扩散的应用
公开(公告)号：US5095358A
公开(公告)日：1992-03-10
申请号：US510742
申请日：1990-04-18
申请人： Sheldon Aronowitz , Courtney L. Hart , Sung T. Ahn
发明人： Sheldon Aronowitz , Courtney L. Hart , Sung T. Ahn
IPC分类号： H01L21/22 , H01L21/225 , H01L21/265 , H01L29/161
CPC分类号： H01L29/161 , H01L21/22 , H01L21/26506
摘要： A method of inhibiting dopant diffusion in silicon using germanium is provided. Germanium is distributed in substitutional sites in a silicon lattice to form two regions of germanium interposed between a region where dopant is to be introduced and a region from which dopant is to be excluded, the two germanium regions acting as a dopant diffusion barrier.

6. 发明授权

US5094972A Means of planarizing integrated circuits with fully recessed isolation dielectric 失效
标题翻译：用完全绝缘隔离电路平面化集成电路的手段
公开(公告)号：US5094972A
公开(公告)日：1992-03-10
申请号：US538645
申请日：1990-06-14
申请人： John M. Pierce , Sung T. Ahn
发明人： John M. Pierce , Sung T. Ahn
IPC分类号： H01L21/304 , H01L21/3105 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76229 , H01L21/31053 , Y10S438/959
摘要： An integrated circuit device is fabricated upon a semiconductor wafer by first forming a stop layer upon the surface of the wafer. Holes are formed through the stop layer and wells are formed in the semiconductor material of the semiconductor wafer below the openings. A dielectric layer is formed over the the surface of the device substantially filling the wells and covering the stop layer. The dielectric layer is then planarized to substantially the level of the stop layer. A PAD oxide layer is provided between the stop layer and the surface of the semiconductor device. Conventional thin film oxidation of the wells and implants into the side walls of the wells are performed. An abrasive mechanical polisher is used to perform the planarization wherein the mechanical polisher is provided with the self-stopping feature when it encounters the stop layer.

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