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1. 发明授权

US06737705B2 Insulated gate semiconductor device 有权
标题翻译：绝缘栅半导体器件
公开(公告)号：US06737705B2
公开(公告)日：2004-05-18
申请号：US09843251
申请日：2001-04-26
申请人： Seiji Momota , Yuichi Onozawa , Masahito Otsuki , Hiroki Wakimoto
发明人： Seiji Momota , Yuichi Onozawa , Masahito Otsuki , Hiroki Wakimoto
IPC分类号： H01L29745
CPC分类号： H01L29/7397 , H01L29/1095 , H01L29/407
摘要： A trench-type IGBT includes a silicon substrate, a lightly doped n-type drift layer on the silicon substrate, and a p-type base layer on the n-type drift layer. The p-type base layer is doped more heavily than the n-type drift layer, and is formed of first regions and second regions. N+-type source regions are formed selectively in the surface portions of the first regions of p-type base layer. Trenches are dug from the surfaces of n+-type source regions down to the n-type drift layer through the p-type base layer. A gate oxide film covers the inner surface of each trench. Gate electrodes are provided in the trenches, wherein the gate electrodes face the p-type base layer via respective gate oxide films. An emitter electrode is in direct contact with the first regions of p-type base layer and n+-type source regions. A collector electrode is provided on the back surface of silicon substrate. The ratio of the width of the first regions to the width of the second regions of p-type base layer is from 1:2 to 1:7. The device facilitates in reducing the total losses by reducing the switching loss while suppressing the on-voltage thereof as low as the on-voltage of the IEGT.
摘要翻译：沟槽型IGBT包括硅衬底，硅衬底上的轻掺杂n型漂移层和n型漂移层上的p型基极层。 p型基极层比n型漂移层掺杂更多，由第一区域和第二区域形成。在p型基底层的第一区域的表面部分中选择性地形成N +型源极区域。沟槽从n +型源区的表面通过p型基底层向下到达n型漂移层。栅极氧化膜覆盖每个沟槽的内表面。栅极设置在沟槽中，其中栅电极经由相应的栅氧化膜面对p型基极层。发射极电极与p型基极层和n +型源极区域的第一区域直接接触。集电极设置在硅衬底的背面上。第一区域的宽度与p型基底层的第二区域的宽度的比例为1:2至1:7。该器件通过降低开关损耗同时将其导通电压抑制得低至IEGT的导通电压，从而有助于降低总损耗。

2. 发明授权

US07462911B2 Insulated gate semiconductor device 有权
标题翻译：绝缘栅半导体器件
公开(公告)号：US07462911B2
公开(公告)日：2008-12-09
申请号：US11561652
申请日：2006-11-20
申请人： Hiroki Wakimoto , Seiji Momota , Masahito Otsuki
发明人： Hiroki Wakimoto , Seiji Momota , Masahito Otsuki
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/0696 , H01L29/7397
摘要： A trench IGBT is disclosed which meets the specifications for turn-on losses and radiation noise. It includes a p-type base layer divided into different p-type base regions by trenches. N-type source regions are formed in only some of the p-type base regions. There is a gate runner in the active region of the trench IGBT. Contact holes formed in the vicinities of the terminal ends of the trenches and on both sides of the gate runner electrically connect some of the p-type base regions that do not include source regions to an emitter electrode. The number N1 of p-type base regions that are connected electrically to the emitter electrode and the number N2 of p-type base regions that are insulated from the emitter electrode are related with each other by the expression 25≦{N1/(N1+N2)}×100≦75.
摘要翻译：公开了一种满足导通损耗和辐射噪声规范的沟槽IGBT。它包括通过沟槽分成不同p型基极区的p型基极层。仅在一些p型基区中形成N型源极区。在沟槽IGBT的有源区域中有一个栅极流道。形成在沟槽的末端附近并且栅极流道两侧的接触孔将不包括源极区域的一些p型基极区域电连接到发射极电极。与发射极电气电连接的p型基极区域的数量N1和与发射极电极绝缘的p型基极区域的数量N2彼此相关，由式25 <= {N1 /（N1 + N2）}×100 <= 75。

3. 发明授权

US07151297B2 Insulated gate semiconductor device 有权
标题翻译：绝缘栅半导体器件
公开(公告)号：US07151297B2
公开(公告)日：2006-12-19
申请号：US10993146
申请日：2004-11-19
申请人： Hiroki Wakimoto , Seiji Momota , Masahito Otsuki
发明人： Hiroki Wakimoto , Seiji Momota , Masahito Otsuki
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/0696 , H01L29/7397
摘要： A trench IGBT is disclosed which meets the specifications for turn-on losses and radiation noise. It includes a p-type base layer divided into different p-type base regions by trenches. N-type source regions are formed in only some of the p-type base regions. There is a gate runner in the active region of the trench IGBT. Contact holes formed in the vicinities of the terminal ends of the trenches and on both sides of the gate runner electrically connect some of the p-type base regions that do not include source regions to an emitter electrode. The number N1 of p-type base regions that are connected electrically to the emitter electrode and the number N2 of p-type base regions that are insulated from the emitter electrode are related with each other by the expression 25≦{N1/(N1+N2)}×100≦75.
摘要翻译：公开了一种满足导通损耗和辐射噪声规范的沟槽IGBT。它包括通过沟槽分成不同p型基极区的p型基极层。仅在一些p型基区中形成N型源极区。在沟槽IGBT的有源区域中有一个栅极流道。形成在沟槽的末端附近并且栅极流道两侧的接触孔将不包括源极区域的一些p型基极区域电连接到发射极电极。与发射极电气电连接的p型基极区域的数量N1和与发射极电极绝缘的p型基极区域的数量N2彼此相关联，通过表达式25 <= {N1 /（N1 + N2x100 <= 75。

4. 发明申请

US20050151187A1 Insulated gate semiconductor device 有权
标题翻译：绝缘栅半导体器件
公开(公告)号：US20050151187A1
公开(公告)日：2005-07-14
申请号：US10993146
申请日：2004-11-19
申请人： Hiroki Wakimoto , Seiji Momota , Masahito Otsuki
发明人： Hiroki Wakimoto , Seiji Momota , Masahito Otsuki
IPC分类号： H01L29/78 , H01L29/06 , H01L29/739 , H01L29/76
CPC分类号： H01L29/0696 , H01L29/7397
摘要： A trench IGBT is disclosed which meets the specifications for turn-on losses and radiation noise. It includes a p-type base layer divided into different p-type base regions by trenches. N-type source regions are formed in only some of the p-type base regions. There is a gate runner in the active region of the trench IGBT. Contact holes formed in the vicinities of the terminal ends of the trenches and on both sides of the gate runner electrically connect some of the p-type base regions that do not include source regions to an emitter electrode. The number N1 of p-type base regions that are connected electrically to the emitter electrode and the number N2 of p-type base regions that are insulated from the emitter electrode are related with each other by the expression 25≦{N1/(N1+N2)}×100≦75.
摘要翻译：公开了一种满足导通损耗和辐射噪声规范的沟槽IGBT。它包括通过沟槽分成不同p型基极区的p型基极层。仅在一些p型基区中形成N型源极区。在沟槽IGBT的有源区域中存在栅极流道。形成在沟槽的末端附近并且栅极流道两侧的接触孔将不包括源极区域的一些p型基极区域电连接到发射极电极。与发射电极电连接的p型基极区域的数量N1和与发射极电极绝缘的p型基极区域的数量N2彼此相关联，表达式25 <= {N1 /（N1 + N2x100 <= 75。

5. 发明授权

US07737490B2 Vertical and trench type insulated gate MOS semiconductor device 有权
标题翻译：垂直和沟槽型绝缘栅MOS半导体器件
公开(公告)号：US07737490B2
公开(公告)日：2010-06-15
申请号：US11741015
申请日：2007-04-27
申请人： Koh Yoshikawa , Hiroki Wakimoto , Masahito Otsuki
发明人： Koh Yoshikawa , Hiroki Wakimoto , Masahito Otsuki
IPC分类号： H01L29/76
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/66348
摘要： A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.
摘要翻译：提供一种垂直和沟槽型绝缘栅极MOS半导体器件，其中p型沟道区域的表面和n型半导体衬底的部分表面在沟槽纵向方向上交替排列成平行布置，并且选择性地形成在p型沟道区域的表面上的n +型发射极区域在沟槽侧面较宽，并且朝向沟槽之间的中心点变窄。这使得器件能够实现低导通电阻和增强的关断能力。

6. 发明授权

US08008734B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08008734B2
公开(公告)日：2011-08-30
申请号：US11972932
申请日：2008-01-11
申请人： Hiroki Wakimoto , Masahito Otsuki , Takashi Shiigi
发明人： Hiroki Wakimoto , Masahito Otsuki , Takashi Shiigi
IPC分类号： H01L29/66
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0696 , H01L29/402 , H01L29/404 , H01L29/66734 , H01L29/7813
摘要： A power semiconductor device is provided having a field plate that employs a thick metal film in an edge termination structure and which permits edge termination structure width reduction even with large side etching or etching variation, which exhibits superior long-term forward blocking voltage capability reliability, and which allows minimal forward blocking voltage capability variation. The edge termination structure has multiple ring-like p-type guard rings, a first insulating film covering the guard rings, and ring-like field plates, provided via the first insulating film atop the guard rings. The field plates have a polysilicon film and a thicker metal film. The polysilicon film is provided on a first guard ring via first insulating film, and a dual field plate made of the polysilicon film and metal film is provided on a second guard ring. The dual field plate is stacked via a second insulating film. The first and second guard rings alternate.
摘要翻译：提供了一种功率半导体器件，其具有采用边缘端接结构中的厚金属膜的场板，即使具有优异的长期正向阻断电压能力可靠性的大的侧蚀刻或蚀刻变化也允许边缘终端结构宽度减小，并且其允许最小的正向阻断电压能力变化。边缘端接结构具有多个环状p型保护环，覆盖保护环的第一绝缘膜和通过护罩顶部上的第一绝缘膜提供的环状场板。场板具有多晶硅膜和较厚的金属膜。多晶硅膜通过第一绝缘膜设置在第一保护环上，并且由多晶硅膜和金属膜制成的双场板设置在第二保护环上。双场板通过第二绝缘膜堆叠。第一和第二保卫环交替出现。

7. 发明申请

US20070252195A1 VERTICAL AND TRENCH TYPE INSULATED GATE MOS SEMICONDUCTOR DEVICE 有权
标题翻译：垂直和倾斜型绝缘栅MOS半导体器件
公开(公告)号：US20070252195A1
公开(公告)日：2007-11-01
申请号：US11741015
申请日：2007-04-27
申请人： Koh Yoshikawa , Hiroki Wakimoto , Masahito Otsuki
发明人： Koh Yoshikawa , Hiroki Wakimoto , Masahito Otsuki
IPC分类号： H01L31/00
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/66348
摘要： A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.
摘要翻译：提供一种垂直和沟槽型绝缘栅极MOS半导体器件，其中p型沟道区域的表面和n型半导体衬底的部分表面在沟槽纵向方向上交替排列成平行布置，并且选择性地形成在p型沟道区域的表面上的n + + +型发射极区域在沟槽侧面较宽，并且朝向沟槽之间的中心点变窄。这使得器件能够实现低导通电阻和增强的关断能力。

8. 发明授权

US08242556B2 Vertical and trench type insulated gate MOS semiconductor device 有权
标题翻译：垂直和沟槽型绝缘栅MOS半导体器件
公开(公告)号：US08242556B2
公开(公告)日：2012-08-14
申请号：US12767356
申请日：2010-04-26
申请人： Koh Yoshikawa , Hiroki Wakimoto , Masahito Otsuki
发明人： Koh Yoshikawa , Hiroki Wakimoto , Masahito Otsuki
IPC分类号： H01L29/76
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/66348
摘要： A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.
摘要翻译：提供一种垂直和沟槽型绝缘栅极MOS半导体器件，其中p型沟道区域的表面和n型半导体衬底的部分表面在沟槽纵向方向上交替排列成平行布置，并且选择性地形成在p型沟道区域的表面上的n +型发射极区域在沟槽侧面较宽，并且朝向沟槽之间的中心点变窄。这使得器件能够实现低导通电阻和增强的关断能力。

9. 发明授权

US08399309B2 Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US08399309B2
公开(公告)日：2013-03-19
申请号：US13109660
申请日：2011-05-17
申请人： Masaaki Ogino , Hiroki Wakimoto , Masayuki Miyazaki
发明人： Masaaki Ogino , Hiroki Wakimoto , Masayuki Miyazaki
IPC分类号： H01L21/00
CPC分类号： H01L29/66333 , H01L29/045 , H01L29/0657
摘要： A manufacturing method is disclosed which ensures strength of a wafer and improves device performance. A thermal diffusion layer is formed from a front surface of a wafer. A tapered groove which reaches the thermal diffusion layer is formed from a back surface by anisotropic etching with alkaline solution. In-groove thermal diffusion layer is formed on side wall surfaces of the groove. A separation layer of a reverse blocking IGBT is configured of the thermal diffusion layer and the in-groove diffusion layer. The thermal diffusion layer is formed shallowly by forming the in-groove diffusion layer. It is possible to considerably reduce thermal diffusion time. By carrying out an ion implantation forming the in-groove diffusion layer and an ion implantation forming a collector layer separately, it is possible to select an optimum value for tradeoff between turn-on voltage and switching loss, while ensuring reverse blocking voltage of the reverse blocking IGBT.
摘要翻译：公开了一种确保晶片强度并提高器件性能的制造方法。热扩散层由晶片的前表面形成。通过各向异性蚀刻用碱性溶液从后表面形成到达热扩散层的锥形槽。槽内热扩散层形成在槽的侧壁面上。反向阻断IGBT的分离层由热扩散层和内槽扩散层构成。通过形成内槽扩散层来形成浅扩散层。可以显着地减少热扩散时间。通过进行形成槽内扩散层的离子注入和分离形成集电极的离子注入，可以选择用于折合导通电压和开关损耗之间的最优值，同时确保反向的反向阻断电压阻断IGBT。

10. 发明授权

US08604584B2 Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08604584B2
公开(公告)日：2013-12-10
申请号：US13038349
申请日：2011-03-01
申请人： Hiroki Wakimoto , Kenichi Iguchi , Koh Yoshikawa , Tsunehiro Nakajima , Shunsuke Tanaka , Masaaki Ogino
发明人： Hiroki Wakimoto , Kenichi Iguchi , Koh Yoshikawa , Tsunehiro Nakajima , Shunsuke Tanaka , Masaaki Ogino
IPC分类号： H01L21/78 , H01L21/302
CPC分类号： H01L21/308 , H01L21/302 , H01L21/78 , H01L29/06
摘要： Some embodiments of the present invention relate to a semiconductor device and a method of manufacturing a semiconductor device capable of preventing the deterioration of electrical characteristics. A p-type collector region is provided on a surface layer of a backside surface of an n-type drift region. A p+-type isolation layer for obtaining reverse blocking capability is provided at the end of an element. In addition, a concave portion is provided so as to extend from the backside surface of the n-type drift region to the p+-type isolation layer. A p-type region is provided and is electrically connected to the p+-type isolation layer. The p+-type isolation layer is provided so as to include a cleavage plane having the boundary between the bottom and the side wall of the concave portion as one side.
摘要翻译：本发明的一些实施例涉及能够防止电特性劣化的半导体器件和半导体器件的制造方法。 p型集电极区域设置在n型漂移区域的背面的表面层上。在元件的末端提供了用于获得反向阻挡能力的p +型隔离层。此外，设置从n型漂移区的背面向p +型隔离层延伸的凹部。提供p型区域并且电连接到p +型隔离层。提供p +型隔离层，以便包括具有作为一侧的凹部的底部和侧壁之间的边界的解理面。

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