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1. 发明授权

US07541858B2 Integration circuit, decrement circuit, and semiconductor devices 有权
标题翻译：集成电路，减量电路和半导体器件
公开(公告)号：US07541858B2
公开(公告)日：2009-06-02
申请号：US11187862
申请日：2005-07-25
申请人： Seigou Yukutake , Mutsuhiro Mori , Yasuhiko Kohno
发明人： Seigou Yukutake , Mutsuhiro Mori , Yasuhiko Kohno
IPC分类号： G06G7/18 , G06F7/64
CPC分类号： F02P3/0552
摘要： An ignitor comprising a circuit with a millisecond order time constant and with a minimum circuit size and area, which is capable of self-shutdown without leading to erroneous ignition upon detection of an abnormality. An ignitor 1 capable of self-shutdown upon detection of an abnormality comprises an abnormality detection circuit 12 whose rise output is applied to the gate of a self-shutdown MOSFET 33 via an integration circuit 33 comprised of a diode 8 and a capacitor 9. The gate voltage of IGBT 5a, which is a main-current switching device, can be decremented.
摘要翻译：包括具有毫秒级时间常数且具有最小电路尺寸和面积的电路的点火器，其能够在检测到异常时自动关闭而不导致错误点火。能够在检测到异常时能够自我关机的点火器1包括：异常检测电路12，其上升输出经由由二极管8和电容器9组成的积分电路33施加到自停闭MOSFET 33的栅极。作为主电流开关器件的IGBT 5a的栅极电压可以减小。

2. 发明申请

US20060022609A1 Integration circuit, decrement circuit, and semiconductor devices 有权
标题翻译：集成电路，减量电路和半导体器件
公开(公告)号：US20060022609A1
公开(公告)日：2006-02-02
申请号：US11187862
申请日：2005-07-25
申请人： Seigou Yukutake , Mutsuhiro Mori , Yasuhiko Kohno
发明人： Seigou Yukutake , Mutsuhiro Mori , Yasuhiko Kohno
IPC分类号： F02P15/00 , F02P3/04
CPC分类号： F02P3/0552
摘要： An ignitor comprising a circuit with a millisecond order time constant and with a minimum circuit size and area, which is capable of self-shutdown without leading to erroneous ignition upon detection of an abnormality. An ignitor 1 capable of self-shutdown upon detection of an abnormality comprises an abnormality detection circuit 12 whose rise output is applied to the gate of a self-shutdown MOSFET 33 via an integration circuit 33 comprised of a diode 8 and a capacitor 9. The gate voltage of IGBT 5a, which is a main-current switching device, can be decremented.
摘要翻译：包括具有毫秒级时间常数且具有最小电路尺寸和面积的电路的点火器，其能够在检测到异常时自动关闭而不导致错误点火。能够在检测到异常时能够自我关机的点火器1包括：异常检测电路12，其上升输出经由由二极管8和电容器9组成的积分电路33施加到自停闭MOSFET 33的栅极。作为主电流开关器件的IGBT5a的栅极电压可以减小。

3. 发明授权

US07638904B2 Isolated bidirectional DC-DC converter 有权
标题翻译：隔离双向DC-DC转换器
公开(公告)号：US07638904B2
公开(公告)日：2009-12-29
申请号：US11206226
申请日：2005-08-18
申请人： Hiroyuki Shoji , Akihiko Kanouda , Ryuichi Saito , Seigou Yukutake , Katsuhiro Higuchi
发明人： Hiroyuki Shoji , Akihiko Kanouda , Ryuichi Saito , Seigou Yukutake , Katsuhiro Higuchi
IPC分类号： G01R1/20
CPC分类号： H02M1/34 , H02M3/33584 , H02M2001/342 , Y02B70/1491
摘要： The DC-DC converter connects a first and a second switching circuit for converting power mutually between direct current and alternating current respectively to a first DC power source and a second DC power source and has a transformer between the AC terminals thereof. Here, between the AC terminals of the second switching circuit and the negative pole terminal of the DC power source, a voltage clamp circuit composed of a series unit of switching devices with a reverse parallel diode and a clamp condenser is connected.An isolated bidirectional DC-DC converter which prevents a reduction in a circulating current at time of buck and an occurrence of a surge voltage at time of voltage boost and realizes highly efficiency, low noise, and miniaturization is provided.
摘要翻译： DC-DC转换器将用于将直流和交流之间的功率相互转换的第一和第二开关电路分别连接到第一直流电源和第二直流电源，并且在其AC端子之间具有变压器。这里，在第二开关电路的交流端子和直流电源的负极端子之间，连接由串联的具有反向并联二极管的开关器件和钳位电容器组成的电压钳位电路。提供一种隔离的双向DC-DC转换器，其防止降压时的循环电流的降低和在升压时的浪涌电压的发生，并且实现高效率，低噪声和小型化。

4. 发明授权

US5834851A SRAM having load transistor formed above driver transistor 失效
标题翻译：具有形成在驱动晶体管上方的负载晶体管的SRAM
公开(公告)号：US5834851A
公开(公告)日：1998-11-10
申请号：US460641
申请日：1995-06-02
申请人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
发明人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
IPC分类号： H01L27/11
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.The source line is formed of a conductive layer identical to that of the word line. The individual data lines of the complementary data line are formed of an identical conductive layer which is different from that of the word line and the source line. The identical conductive layer between the word line and source line and the complementary data line is formed with two word lines: a main word line extended in the first direction identical to that of the word line and source line and used by adopting the divided word line system: and a sub-word line used by adopting the double word line system.
摘要翻译：这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。存储器单元的两个转移MISFET的各自的栅极电极与彼此间隔开并沿相同方向延伸的两个相应字线连接。由两个字线限定的区域配置有两个驱动MISFET和源极线。源极线由与字线的导电层相同的导电层形成。互补数据线的各个数据线由与字线和源极线不同的导电层形成。字线和源极线与互补数据线之间的相同的导电层由两条字线形成：主字线在第一方向上延伸，与字线和源极线相同，并通过采用分割字线系统：采用双字线系统使用的子字线。

5. 发明授权

US5646897A Logic gate circuit and parallel bit test circuit for semiconductor memory devices, capable of operation at low power source levels 失效
标题翻译：用于半导体存储器件的逻辑门电路和并行位测试电路，能够在低电源电平下工作
公开(公告)号：US5646897A
公开(公告)日：1997-07-08
申请号：US426384
申请日：1995-04-21
申请人： Seigou Yukutake , Masahiro Iwamura , Kinya Mitsumoto , Takashi Akioka , Noboru Akiyama
发明人： Seigou Yukutake , Masahiro Iwamura , Kinya Mitsumoto , Takashi Akioka , Noboru Akiyama
IPC分类号： G11C7/10 , G11C29/34 , G11C29/50 , G11C7/00
CPC分类号： G11C29/028 , G11C29/50 , G11C7/1051 , G11C11/41 , G11C2029/5004 , G11C29/34
摘要： A logic circuit is provided for a memory device which can be operated at a high speed with a lower voltage power source level than conventional devices. This logic circuit can be used in a multi-bit test circuit executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, receiving the output of the wired-OR-logic operation by an emitter follower using a bipolar transistor, and outputting an AND signal of the complementary logic signals by a level comparing circuit. A sense amplifier is also provided for executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, raising the level of the output of the wired-OR-logic operation by a level shift circuit having a semiconductor element for applying an inverse bias potential to an input signal, executing the wired-OR-operation of the shifted up output and outputs from other blocks, and receiving and amplifying the output of the wired-OR-logic operation.
摘要翻译：提供了一种用于存储器件的逻辑电路，其可以以比传统器件更低的电压电源电平在高速下操作。该逻辑电路可以用于执行来自多个预读取放大器的互补逻辑信号的有线或逻辑运算的多位测试电路，通过射极跟随器接收有线或逻辑运算的输出，使用双极晶体管，并通过电平比较电路输出互补逻辑信号的“与”信号。还提供读出放大器，用于执行来自多个预读放大器的互补逻辑信号的有线或逻辑运算，通过具有半导体的电平移位电路提高布线或逻辑运算的输出电平元件，用于对输入信号施加反向偏置电位，执行移位上升输出的线或运算和其他块的输出，以及接收和放大有线逻辑运算的输出。

6. 发明授权

US06853063B2 Semiconductor device and communication terminal using thereof 有权
标题翻译：半导体装置及其通信终端
公开(公告)号：US06853063B2
公开(公告)日：2005-02-08
申请号：US10443039
申请日：2003-05-22
申请人： Noboru Akiyama , Minehiro Nemoto , Seigou Yukutake , Yasuyuki Kojima , Kazuyuki Kamegaki
发明人： Noboru Akiyama , Minehiro Nemoto , Seigou Yukutake , Yasuyuki Kojima , Kazuyuki Kamegaki
IPC分类号： H01L25/18 , H01L23/31 , H01L23/48 , H01L23/495 , H01L25/04 , H01L25/16 , H01L23/02 , H01L23/34 , H01L22/16 , H01L23/28 , H05K7/02
CPC分类号： H01L23/3107 , H01L23/3121 , H01L23/48 , H01L23/49575 , H01L24/06 , H01L24/48 , H01L24/49 , H01L25/162 , H01L2224/0401 , H01L2224/05554 , H01L2224/05599 , H01L2224/0603 , H01L2224/16 , H01L2224/16225 , H01L2224/16245 , H01L2224/16265 , H01L2224/32245 , H01L2224/48091 , H01L2224/48095 , H01L2224/48137 , H01L2224/48247 , H01L2224/484 , H01L2224/49175 , H01L2224/73207 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01074 , H01L2924/014 , H01L2924/10161 , H01L2924/12036 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19104 , H01L2924/3011 , H01L2924/30111 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： Wire bonding or printed wiring board leads or, alternatively, lead frames or equivalents thereof are used to electrically connect external electrodes of high withstand voltage capacitors formed on a plurality of semiconductor chips. A driver circuit for signal transmission or receiver circuit for signal receipt formed on the semiconductor chips are electrically connected with substrate-side electrodes of said high withstand voltage capacitors, causing the plurality of semiconductor chips to be received within either a single package or a single module. Using this arrangement, a semiconductor device is capable of achieving both dielectricity and size reduction.
摘要翻译：引线接合或印刷电路板引线或引线框架或其等同物用于电连接形成在多个半导体芯片上的高耐压电容器的外部电极。在半导体芯片上形成的用于信号传输的信号传输或接收电路的驱动电路与所述高耐压电容器的衬底侧电极电连接，导致多个半导体芯片被接收在单个封装或单个模块内。使用这种布置，半导体器件能够实现电介质和尺寸减小。

7. 发明授权

US5731219A Process for fabricating a semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US5731219A
公开(公告)日：1998-03-24
申请号：US458616
申请日：1995-06-02
申请人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
发明人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
IPC分类号： H01L27/11 , H01L21/70
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： Herein disclosed is a semiconductor integrated circuit device comprising an SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs, and a method of forming this device. The gate electrodes of the drive MISFETs and of the transfer MISFETs of the memory cell, and the word lines, are individually formed of different conductive layers. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The source line is formed of a conductive layer identical to that of the word line. An oxidation resisting film is formed on the gate electrodes of the drive MISFETs so as to reduce stress caused by oxidization of edge portions of these gate electrodes, and to reduce a resulting leakage current. A thickness of an oxide film formed on gate electrodes of the transfer MISFETs and word lines is thicker than an oxide film formed on gate electrodes of the drive MISFETs, so that data line pads can be formed in self-alignment with the oxide film and side wall spacers on the gate electrodes of the transfer MISFETs.
摘要翻译：这里公开了一种半导体集成电路器件，其特征在于包括SRAM，其SRAM具有通过字线和驱动MISFET来控制的转移MISFET构成的存储单元，以及形成该器件的方法。驱动MISFET的栅电极和存储单元的转移MISFET以及字线分别由不同的导电层形成。存储器单元的两个转移MISFET的各自的栅极电极与彼此间隔开并沿相同方向延伸的两个相应字线连接。源极线由与字线的导电层相同的导电层形成。在驱动MISFET的栅电极上形成抗氧化膜，以减少由这些栅电极的边缘部分的氧化引起的应力，并减少产生的漏电流。形成在转移MISFET和字线的栅电极上的氧化膜的厚度比形成在驱动MISFET的栅电极上的氧化膜厚，使得数据线焊盘可以形成为与氧化膜和侧面自对准传输MISFET的栅电极上的壁间隔物。

8. 发明授权

US5656836A Semiconductor integrated circuit device and process for fabricating the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US5656836A
公开(公告)日：1997-08-12
申请号：US460129
申请日：1995-06-02
申请人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
发明人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
IPC分类号： H01L27/11 , H01L27/108 , H01L29/76
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.The two transfer MISFETs of the memory cell have their individual gate electrodes connected-with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.
摘要翻译：这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。存储单元的两个转移MISFET具有彼此间隔开并沿相同方向延伸的两个相应字线连接的各自的栅电极。由两个字线限定的区域配置有两个驱动MISFET和源极线。

9. 发明授权

US5572480A Semiconductor integrated circuit device and process for fabricating the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US5572480A
公开(公告)日：1996-11-05
申请号：US459961
申请日：1995-06-02
申请人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
发明人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
IPC分类号： H01L27/11 , G11C8/00
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903
摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.
摘要翻译：这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。

10. 发明授权

US07598605B2 Semiconductor device having capacitive insulation means and communication terminal using the device 有权
标题翻译：具有电容绝缘装置的半导体装置和使用该装置的通信终端
公开(公告)号：US07598605B2
公开(公告)日：2009-10-06
申请号：US11495585
申请日：2006-07-31
申请人： Noboru Akiyama , Minehiro Nemoto , Seigou Yukutake , Yasuyuki Kojima , Kazuyuki Kamegaki
发明人： Noboru Akiyama , Minehiro Nemoto , Seigou Yukutake , Yasuyuki Kojima , Kazuyuki Kamegaki
IPC分类号： H01L23/24 , H01L23/02 , H01L23/28 , H05K7/02
CPC分类号： H01L23/3107 , H01L23/3121 , H01L23/48 , H01L23/49575 , H01L24/06 , H01L24/48 , H01L24/49 , H01L25/162 , H01L2224/0401 , H01L2224/05554 , H01L2224/05599 , H01L2224/0603 , H01L2224/16 , H01L2224/16225 , H01L2224/16245 , H01L2224/16265 , H01L2224/32245 , H01L2224/48091 , H01L2224/48095 , H01L2224/48137 , H01L2224/48247 , H01L2224/484 , H01L2224/49175 , H01L2224/73207 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01074 , H01L2924/014 , H01L2924/10161 , H01L2924/12036 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19104 , H01L2924/3011 , H01L2924/30111 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A primary side circuit and a secondary side circuit are provided on first and second semiconductor substrates, respectively. A first capacitive insulator on the first substrate electrically insulates and isolates between the primary and secondary side circuits while permitting signal transmission between these circuits. A second capacitive insulator on the second semiconductor substrate electrically isolates the primary and secondary side circuit while permitting signal transmission therebetween. First and second frames are provided for input and output of signals to and from the primary and secondary side circuits. External electrodes of the first and second capacitive insulators are connected together by a third lead frame via a conductive adhesive body including more than one solder ball. The first and second substrates and the lead frames are sealed by a dielectric resin.
摘要翻译：初级侧电路和次级侧电路分别设置在第一和第二半导体衬底上。第一基板上的第一电容绝缘体在允许这些电路之间的信号传输的同时在一次侧电路和次侧电路之间电绝缘和隔离。第二半导体衬底上的第二电容绝缘体电隔离初级和次级侧电路，同时允许它们之间的信号传输。第一和第二帧被提供用于输入和输出到主电路和次级侧电路的信号。第一和第二电容性绝缘体的外部电极通过包括多于一个焊球的导电粘合体由第三引线框架连接在一起。第一和第二基板和引线框由绝缘树脂密封。

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