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1. 发明授权

US5700704A Process for fabricating a semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US5700704A
公开(公告)日：1997-12-23
申请号：US458615
申请日：1995-06-02
申请人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
发明人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
IPC分类号： H01L27/11 , H01L21/8244
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： A method is provided for manufacturing a semiconductor integrated circuit device which includes a capacitor element having a first electrode, a second electrode, and a dielectric film formed between said first electrode and said second electrode. In particular, the method includes the step of forming at least one of the first electrode and second electrode with a polycrystalline silicon film which is deposited over a semiconductor substrate by a CVD method and which is doped with an impurity during said deposition to decrease the resistance of the polycrystalline silicon film. The capacitor element formed by this method is particularly useful for memory cells of static random access memory devices.
摘要翻译：提供一种用于制造半导体集成电路器件的方法，该半导体集成电路器件包括具有形成在所述第一电极和所述第二电极之间的第一电极，第二电极和电介质膜的电容器元件。特别地，该方法包括用多晶硅膜形成第一电极和第二电极中的至少一个的步骤，该多晶硅膜通过CVD方法沉积在半导体衬底上，并且在所述沉积期间掺杂有杂质以降低电阻的多晶硅膜。通过该方法形成的电容器元件对静态随机存取存储器件的存储单元特别有用。

2. 发明授权

US5652457A Semiconductor integrated circuit device and process for fabricating the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US5652457A
公开(公告)日：1997-07-29
申请号：US351173
申请日：1994-11-30
申请人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
发明人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
IPC分类号： H01L27/11 , H01L29/76
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.The source line is formed of a conductive layer identical to that of the word line. The individual data lines of the complementary data line are formed of an identical conductive layer which is different from that of the word line and the source line. The identical conductive layer between the word line and source line and the complementary data line is formed with two word lines: a main word line extended in the first direction identical to that of the word line and source line and used by adopting the divided word line system: and a sub-word line used by adopting the double word line system.
摘要翻译：这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。存储器单元的两个转移MISFET的各自的栅极电极与彼此间隔开并沿相同方向延伸的两个相应字线连接。由两个字线限定的区域配置有两个驱动MISFET和源极线。源极线由与字线的导电层相同的导电层形成。互补数据线的各个数据线由与字线和源极线不同的导电层形成。字线和源极线与互补数据线之间的相同的导电层由两条字线形成：主字线在第一方向上延伸，与字线和源极线相同，并通过采用分割字线系统：采用双字线系统使用的子字线。

3. 发明授权

US5005068A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5005068A
公开(公告)日：1991-04-02
申请号：US376953
申请日：1989-07-07
申请人： Shuji Ikeda , Katsuro Sasaki , Kouichi Nagasawa , Satoshi Meguro
发明人： Shuji Ikeda , Katsuro Sasaki , Kouichi Nagasawa , Satoshi Meguro
IPC分类号： H01L21/768 , G11C11/41 , H01L21/8244 , H01L23/522 , H01L27/10 , H01L27/11
CPC分类号： H01L27/11 , H01L27/1112 , Y10S257/903 , Y10S257/904 , Y10S257/906
摘要： A static RAM having first word lines each defined by extended gate electrodes of MISFETs constituting memory cells, and second word lines which are separate from the first word lines. The RAM has a wiring for supplying a fixed potential such as a ground potential to the memory cells, the wiring being formed from the same layer as that for forming the second word lines.
摘要翻译：一种静态RAM，其具有由构成存储单元的MISFET的扩展栅极电极和由第一字线分开的第二字线构成的第一字线。 RAM具有用于向存储单元提供诸如地电位的固定电位的布线，布线由与用于形成第二字线的层相同的层形成。

4. 发明授权

US5731219A Process for fabricating a semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US5731219A
公开(公告)日：1998-03-24
申请号：US458616
申请日：1995-06-02
申请人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
发明人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
IPC分类号： H01L27/11 , H01L21/70
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： Herein disclosed is a semiconductor integrated circuit device comprising an SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs, and a method of forming this device. The gate electrodes of the drive MISFETs and of the transfer MISFETs of the memory cell, and the word lines, are individually formed of different conductive layers. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The source line is formed of a conductive layer identical to that of the word line. An oxidation resisting film is formed on the gate electrodes of the drive MISFETs so as to reduce stress caused by oxidization of edge portions of these gate electrodes, and to reduce a resulting leakage current. A thickness of an oxide film formed on gate electrodes of the transfer MISFETs and word lines is thicker than an oxide film formed on gate electrodes of the drive MISFETs, so that data line pads can be formed in self-alignment with the oxide film and side wall spacers on the gate electrodes of the transfer MISFETs.
摘要翻译：这里公开了一种半导体集成电路器件，其特征在于包括SRAM，其SRAM具有通过字线和驱动MISFET来控制的转移MISFET构成的存储单元，以及形成该器件的方法。驱动MISFET的栅电极和存储单元的转移MISFET以及字线分别由不同的导电层形成。存储器单元的两个转移MISFET的各自的栅极电极与彼此间隔开并沿相同方向延伸的两个相应字线连接。源极线由与字线的导电层相同的导电层形成。在驱动MISFET的栅电极上形成抗氧化膜，以减少由这些栅电极的边缘部分的氧化引起的应力，并减少产生的漏电流。形成在转移MISFET和字线的栅电极上的氧化膜的厚度比形成在驱动MISFET的栅电极上的氧化膜厚，使得数据线焊盘可以形成为与氧化膜和侧面自对准传输MISFET的栅电极上的壁间隔物。

5. 发明授权

US5656836A Semiconductor integrated circuit device and process for fabricating the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US5656836A
公开(公告)日：1997-08-12
申请号：US460129
申请日：1995-06-02
申请人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
发明人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
IPC分类号： H01L27/11 , H01L27/108 , H01L29/76
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.The two transfer MISFETs of the memory cell have their individual gate electrodes connected-with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.
摘要翻译：这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。存储单元的两个转移MISFET具有彼此间隔开并沿相同方向延伸的两个相应字线连接的各自的栅电极。由两个字线限定的区域配置有两个驱动MISFET和源极线。

6. 发明授权

US5572480A Semiconductor integrated circuit device and process for fabricating the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US5572480A
公开(公告)日：1996-11-05
申请号：US459961
申请日：1995-06-02
申请人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
发明人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
IPC分类号： H01L27/11 , G11C8/00
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903
摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.
摘要翻译：这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。

7. 发明授权

US5146427A High speed semiconductor memory having a direct-bypass signal path 失效
标题翻译：具有直接旁路信号路径的高速半导体存储器
公开(公告)号：US5146427A
公开(公告)日：1992-09-08
申请号：US825782
申请日：1992-01-21
申请人： Katsuro Sasaki , Nobuyuki Moriwaki , Shigeru Honjo , Hideaki Nakamura
发明人： Katsuro Sasaki , Nobuyuki Moriwaki , Shigeru Honjo , Hideaki Nakamura
IPC分类号： G11C7/10
CPC分类号： G11C7/1006 , G11C7/1051
摘要： In a semiconductor memory, a latch circuit is arranged between the outputs of a sense amplifier and the inputs of a data output buffer. First pass-gates are arranged between the outputs of the sense amplifier and the latch circuit, while second pass-gates are arranged between the latch circuit and the inputs of the data output buffer. The outputs of the sense amplifier are transmitted to the inputs of the data output buffer through signal paths which bypass the first pass-gates, the latch circuit and the second pass-gates, whereby the data output buffer generates a data output quickly. Thereafter, the first pass-gates and the second pass-gates are controllably brought to a signal-through condition, whereby the output information items of the sense amplifier are stored in the latch circuit. The data output buffer holds the data output in conformity with the stored information items of the latch circuit. For a period of time for which the data output buffer holds the data output, the sense amplifier is held in a non-activated condition, so that the power consumption of the semiconductor memory is lowered.
摘要翻译：在半导体存储器中，锁存电路布置在读出放大器的输出端和数据输出缓冲器的输入端之间。第一通过门被布置在读出放大器和锁存电路的输出之间，而第二通过门被布置在锁存电路和数据输出缓冲器的输入之间。读出放大器的输出通过旁路第一通过门，锁存电路和第二传递门的信号路径被发送到数据输出缓冲器的输入，从而数据输出缓冲器快速产生数据输出。此后，第一通过门和第二通过门被可控地带到信号通过状态，由此将读出放大器的输出信息项存储在锁存电路中。数据输出缓冲器保存符合存储的锁存电路的信息项的数据输出。在数据输出缓冲器保持数据输出的一段时间内，读出放大器保持在非激活状态，从而降低了半导体存储器的功耗。

8. 发明授权

US5132771A Semiconductor memory device having flip-flop circuits 失效
标题翻译：具有触发电路的半导体存储器件
公开(公告)号：US5132771A
公开(公告)日：1992-07-21
申请号：US503928
申请日：1990-04-04
申请人： Toshiaki Yamanaka , Naotaka Hashimoto , Takashi Hashimoto , Akihiro Shimizu , Koichiro Ishibashi , Katsuro Sasaki , Katsuhiro Shimohigashi , Eiji Takeda , Yoshio Sakai , Takashi Nishida , Osamu Minato , Toshiaki Masuhara , Shoji Hanamura , Shigeru Honjo , Nobuyuki Moriwaki
发明人： Toshiaki Yamanaka , Naotaka Hashimoto , Takashi Hashimoto , Akihiro Shimizu , Koichiro Ishibashi , Katsuro Sasaki , Katsuhiro Shimohigashi , Eiji Takeda , Yoshio Sakai , Takashi Nishida , Osamu Minato , Toshiaki Masuhara , Shoji Hanamura , Shigeru Honjo , Nobuyuki Moriwaki
IPC分类号： G11C11/412 , H01L27/11
CPC分类号： G11C11/4125 , H01L27/1104 , Y10S257/903
摘要： A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor. The gate electrode of one of the two first insulated gate field effect transistors and the drain region of the other insulated gate field effect transistor, on one hand, and the drain region of the one insulated gate field effect transistor and the gate electrode of the other insulated gate field effect transistor, on the other hand, are electrically cross-coupled mutually through first and second electrically conductive films, respectively. Also, to increase packing density and enhance immunity to soft error, the gate electrodes of the first and second insulated gate field effect transistors extend substantially in parallel with one another and the channel regions of the first and second insulated gate field effect transistors extend substantially in parallel with one another.
摘要翻译：提供了具有高α射线抗扰度和高封装密度的半导体静态随机存取存储器，其也能够进行高速操作。半导体存储器件包括每个包括触发器电路的静态随机存取存储器单元。每个触发器电路的存储节点分别形成在夹在第一绝缘栅场效应晶体管的栅电极和第二绝缘栅场效应晶体管的栅电极之间的区域处的各pn结。 pn结的面积小于第一或第二绝缘栅场效应晶体管的沟道部分的面积。两个第一绝缘栅场效应晶体管中的一个的栅极电极和另一个绝缘栅场效应晶体管的漏极区域以及一个绝缘栅场效应晶体管的漏极区域和另一个绝缘栅极场效应晶体管的栅极电极另一方面，绝缘栅场效应晶体管分别通过第一和第二导电膜互相交叉耦合。此外，为了增加封装密度并增强对软误差的抵抗力，第一和第二绝缘栅场效应晶体管的栅极彼此基本平行地延伸，并且第一和第二绝缘栅场效应晶体管的沟道区域基本上以彼此平行。

9. 发明授权

US5047706A Constant current-constant voltage circuit 失效
标题翻译：恒流恒压电路
公开(公告)号：US5047706A
公开(公告)日：1991-09-10
申请号：US577512
申请日：1990-09-05
申请人： Koichiro Ishibashi , Katsuro Sasaki , Katsuhiro Shimohigashi
发明人： Koichiro Ishibashi , Katsuro Sasaki , Katsuhiro Shimohigashi
IPC分类号： G05F1/46 , G05F3/24 , G11C11/407 , H01L21/822 , H01L27/04
CPC分类号： G05F3/247 , G05F1/463 , G05F1/465 , G05F3/245 , Y10S323/907
摘要： In a constant current-constant voltage circuit disclosed herein, gates of MOSFETs Q.sub.1 and Q.sub.2 are connected together, and the gate of the MOSFET Q.sub.1 is connected to the drain thereof. Further, the source of the MOSFET Q.sub.1 is connected to ground potential GND whereas the source of the MOSFET Q.sub.2 is connected to the drain of a MOSFET Q.sub.3 having a gate connected to power supply voltage V.sub.DD and a source connected to the ground voltage GND. A current mirror circuit including Q.sub.4 and Q.sub.5 has an input and an output respectively connected to the drain of the second MOSFET Q.sub.2 and the drain of the first MOSFET Q.sub.1. A first coefficient (W.sub.3 L.sub.2 /L.sub.3 W.sub.2) depending upon channel lengths (L.sub.2, L.sub.3) and channel widths (W.sub.2, W.sub.3) of the MOSFETs Q.sub.2 and Q.sub.3 is set at a value not larger than a predetermined value. Therefore, the MOSFET Q.sub.3 operates in a linear region as high resistance, and the MOSFETs Q.sub.1 and Q.sub.2 operate in a sub-threshold region. As a result, the dependence upon temperature is significantly improved.
摘要翻译：在本文公开的恒定电流恒定电压电路中，MOSFET Q1和Q2的栅极连接在一起，并且MOSFET Q1的栅极连接到其漏极。此外，MOSFET Q1的源极连接到地电位GND，而MOSFET Q2的源极连接到具有连接到电源电压VDD的栅极和连接到地电压GND的源极的MOSFET Q3的漏极。包括Q4和Q5的电流镜电路具有分别连接到第二MOSFET Q2的漏极和第一MOSFET Q1的漏极的输入和输出。取决于MOSFET Q2和Q3的沟道长度（L2，L3）和沟道宽度（W2，W3）的第一系数（W3L2 / L3W2）被设置为不大于预定值的值。因此，MOSFET Q3以高电阻工作在线性区域，并且MOSFET Q1和Q2在亚阈值区域中工作。结果，对温度的依赖性显着提高。

10. 发明授权

US06282611B1 Digital information system, digital audio signal processor and signal converter 失效
公开(公告)号：US06282611B1
公开(公告)日：2001-08-28
申请号：US08446278
申请日：1995-05-22
申请人： Nobuo Hamamoto , Minoru Nagata , Masatoshi Ohtake , Katsutaka Kimura , Toshio Sasaki , Hiroshi Kishida , Isamu Orita , Katsuro Sasaki , Naoki Ozawa , Kazuhiro Kondo , Toshiaki Masuhara , Tadashi Onishi , Hidehito Obayashi , Kiyoshi Aiki , Hisashi Horikoshi
发明人： Nobuo Hamamoto , Minoru Nagata , Masatoshi Ohtake , Katsutaka Kimura , Toshio Sasaki , Hiroshi Kishida , Isamu Orita , Katsuro Sasaki , Naoki Ozawa , Kazuhiro Kondo , Toshiaki Masuhara , Tadashi Onishi , Hidehito Obayashi , Kiyoshi Aiki , Hisashi Horikoshi
IPC分类号： G06F1200
CPC分类号： G07F7/1008 , G07F17/16 , H02J7/0063
摘要： In a digital information system for realizing the sale of information or the like having a commercial value in the form of a digital signal, and an audio processor, and signal processor suitably used with the system, when a digital signal is received/delivered, a digital signal source is connected directly to a player for receiving and storing a specified information, which is reproduced by the player independently. A voice interval of a digital audio signal is processed to realize the slow and fast playback. The system includes a data compressor and a data extender of simple configuration. The value of the digital signal received/delivered can be exhibited directly. A selling system is constructed easily, and the player is simple in configuration and easy to operate by anyone. The fast and slow playback are possible without deteriorating the sound quality, and ripples can be greatly reduced against the digital input signal, thereby making possible a faithful data compression of an acoustic signal or the like by a simple configuration. The self-diagnosis function permits the use of a defective memory chip, thereby leading to a very economical system.

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