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1. 发明授权

US07558138B1 Bypass circuit for memory arrays 失效
标题翻译：存储器阵列的旁路电路
公开(公告)号：US07558138B1
公开(公告)日：2009-07-07
申请号：US12242564
申请日：2008-09-30
申请人： Sebastian Ehrenreich , Werner Juchmes , Atnje Mueller , Silke Salewski
发明人： Sebastian Ehrenreich , Werner Juchmes , Atnje Mueller , Silke Salewski
IPC分类号： G11C7/00
CPC分类号： G11C7/18 , G11C7/12 , G11C29/1201 , G11C29/32 , G11C2029/1204 , G11C2029/3202
摘要： A method for bypassing a memory array in a circuit having a global bit line, a test port configured to output a logic test, a memory portion connected to the global bit line via a word line, a header device being connected to the global bit line via a pre-charge signal, the header device being configured to recharge the global bit line. A gating signal is sent to a gating device connected to the header device. The gating device is switched to a test mode upon receipt of the gating signal. The bypass data signal is sent to an evaluating device connected to the gating device, the evaluating device being configured to output a logic test. The logic test is output through the test port upon receipt of bypass data signal.
摘要翻译：一种用于绕过具有全局位线的电路中的存储器阵列的方法，被配置为输出逻辑测试的测试端口，经由字线连接到全局位线的存储器部分，连接到全局位线的标题设备通过预充电信号，头部设备被配置为对全局位线进行再充电。选通信号被发送到连接到报头装置的选通装置。门控装置在接收到门控信号时切换到测试模式。旁路数据信号被发送到连接到选通装置的评估装置，评估装置被配置为输出逻辑测试。接收到旁路数据信号后，逻辑测试通过测试端口输出。

2. 发明授权

US07626851B2 Method to improve performance of SRAM cells, SRAM cell, SRAM array, and write circuit 失效
标题翻译：提高SRAM单元，SRAM单元，SRAM阵列和写入电路性能的方法
公开(公告)号：US07626851B2
公开(公告)日：2009-12-01
申请号：US11771014
申请日：2007-06-29
申请人： Derick G. Behrends , Sebastian Ehrenreich , Juergen Pille , Otto Martin Wagner
发明人： Derick G. Behrends , Sebastian Ehrenreich , Juergen Pille , Otto Martin Wagner
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： A method to improve performance of an SRAM cell or an SRAM array comprising a plurality of SRAM cells is described. The cell is supplied by a first, higher voltage. The cell is accessible for read and write operations via at least one bit line connected to a write circuit. The cell is further addressable by at least one word line in order to access it by the bit line. To access the cell for read or write operations, the word line is supplied by the first, higher voltage and the bit line is supplied by a second, lower voltage. During write operations, the write circuit is driven by the first, higher voltage while the bit lines are still at the lower voltage. An SRAM cell, an SRAM array plus a write circuit used to perform the method are also described.
摘要翻译：描述了一种改善包括多个SRAM单元的SRAM单元或SRAM阵列性能的方法。电池由第一高电压供电。该单元可通过连接到写入电路的至少一个位线进行读取和写入操作。该单元进一步可由至少一个字线寻址，以便通过位线访问该单元。为了访问单元进行读或写操作，字线由第一较高电压提供，位线由第二较低电压提供。在写操作期间，写电路由第一较高电压驱动，同时位线仍处于较低电压。还描述了SRAM单元，SRAM阵列加上用于执行该方法的写入电路。

3. 发明授权

US07532869B2 Automatic power level control circuit for a transceiver device 有权
标题翻译：收发器设备的自动功率电平控制电路
公开(公告)号：US07532869B2
公开(公告)日：2009-05-12
申请号：US10327170
申请日：2002-12-20
申请人： Sebastian Ehrenreich , Lutz Dathe , Hendrik Roller
发明人： Sebastian Ehrenreich , Lutz Dathe , Hendrik Roller
IPC分类号： H01Q11/12 , H04B1/04
CPC分类号： H03G3/001 , H03G3/3042
摘要： An automatic power level control circuit provides output power control of a transmitter device as used in wireless LAN applications in that an output signal is detected and a corresponding control voltage of a DAC in the base band section is corresponding adjusted. Preferably, the measurement of the output power is carried out during a first transmit cycle and the DAC is adjusted after completion of the first transmit cycle and prior to the begin of a subsequent transmit cycle. Thus, a reliable output level control is obtained with a minimum number of radio frequency components, wherein the control loop shows an enhanced stability due to the time-discrete control operation.
摘要翻译：自动功率电平控制电路提供在无线局域网应用中使用的发射机设备的输出功率控制，因为检测到输出信号，并且调整基带部分中的DAC的对应控制电压。优选地，在第一发射周期期间执行输出功率的测量，并且在完成第一发射周期之后并且在随后的发射周期开始之前调整DAC。因此，利用最小数量的射频分量获得可靠的输出电平控制，其中由于时间离散控制操作，控制环路显示出增强的稳定性。

4. 发明申请

US20080137455A1 Storage Cell Design Evaluation Circuit Including a Wordline Timing and Cell Access Detection Circuit 失效
标题翻译：包括字线定时和单元访问检测电路的存储单元设计评估电路
公开(公告)号：US20080137455A1
公开(公告)日：2008-06-12
申请号：US11609598
申请日：2006-12-12
申请人： Sebastian Ehrenreich , Jente B Kuang , Chun-Tao Li , Hung Cai Ngo
发明人： Sebastian Ehrenreich , Jente B Kuang , Chun-Tao Li , Hung Cai Ngo
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/02 , G11C29/025 , G11C29/50012
摘要： A method for storage cell design evaluation provides accurate information about state changes in static storage cells. A wordline select pulse is propagated along the wordline select path of the test row to an output driver circuit, in order to test the clock and/or address timing of the row, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. An access detection cell holds the input of the output driver circuit until a simulated access operation activated by the wordline select pulse is complete. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.
摘要翻译：用于存储单元设计评估的方法提供关于静态存储单元中的状态变化的准确信息。字线选择脉冲沿着测试行的字线选择路径传播到输出驱动器电路，以便测试该行的时钟和/或地址时序，使得访问时序，读取稳定性和可写性与字线强度的变化 /访问电压可以确定。访问检测单元保持输出驱动器电路的输入，直到由字线选择脉冲激活的模拟访问操作完成。多个测试行可以在列之间级联，以提供长延迟线或环形振荡器，以提高测量分辨率。

5. 发明申请

US20080068902A1 Wordline Booster Design Structure and Method of Operating a Wordline Booster Circuit 有权
标题翻译： Wordline Booster设计结构和操作字线加速电路的方法
公开(公告)号：US20080068902A1
公开(公告)日：2008-03-20
申请号：US11847759
申请日：2007-08-30
申请人： Sebastian Ehrenreich , Juergen Pille , Otto Torreiter
发明人： Sebastian Ehrenreich , Juergen Pille , Otto Torreiter
IPC分类号： G11C7/00
CPC分类号： G11C5/145 , G11C8/08 , G11C11/413
摘要： The invention relates to a wordline booster circuit, especially an SRAM-wordline booster circuit, comprising a driving element (20) for shifting a voltage level of a charge storage element (50) for storing a charge necessary to generate a boosted voltage (Vb), a feedback element (30) for controlling the switching state of a charging element (40), wherein the charging element (40) is actively switchable between a turned-off state during a first time interval and a turned-on state during a second time interval, and an output port (14) for supplying the boost voltage to at least one wordline-driver circuit (100) of a memory device (200). The invention relates also to an operation method for such a wordline booster circuit as well as a memory array implementation on an integrated circuit, especially an SRAM memory array, with a wordline booster circuit.
摘要翻译：本发明涉及一种字线升压电路，特别是一种SRAM字线升压电路，它包括用于移动电荷存储元件（50）的电压电平的驱动元件（20），用于存储产生升压电压（Vb）所需的电荷，，用于控制充电元件（40）的开关状态的反馈元件（30），其中所述充电元件（40）可在第一时间间隔期间的关断状态和第二时间间隔期间的接通状态之间主动切换以及用于将升压电压提供给存储装置（200）的至少一个字线驱动电路（100）的输出端口（14）。本发明还涉及这种字线升压电路的操作方法以及具有字线升压电路的集成电路，特别是SRAM存储器阵列上的存储器阵列实现。

6. 发明申请

US20100309734A1 METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND DATA PROCESSING DEVICE FOR MONITORING MEMORY CIRCUITS AND CORRESPONDING INTEGRATED CIRCUIT 失效
标题翻译：方法，系统，计算机程序产品和用于监视存储器电路和相关集成电路的数据处理设备
公开(公告)号：US20100309734A1
公开(公告)日：2010-12-09
申请号：US12784164
申请日：2010-05-20
申请人： Sebastian Ehrenreich , Tilman Gloekler , Willm Hinrichs , Jens Kuenzer
发明人： Sebastian Ehrenreich , Tilman Gloekler , Willm Hinrichs , Jens Kuenzer
IPC分类号： G11C7/06
CPC分类号： G11C29/24 , G11C16/349 , G11C29/021 , G11C29/028 , G11C2029/0409 , G11C2029/1202
摘要： An improved method monitors memory circuits, especially those used in integrated circuits. The method provides: writing random data in at least one monitor cell, which is implemented as a regular memory cell with an artificially deteriorated stability in order to provoke early fails when compared to fails in a regular memory cell; reading the random data out of the at least one monitor cell; comparing the output data of the read operation against an expected value to detect a value mismatch; and reporting the value mismatch to an error structure if the value mismatch is detected.
摘要翻译：改进的方法监视存储器电路，特别是集成电路中使用的那些电路。该方法提供：在至少一个监视器单元中写入随机数据，其被实现为具有人为劣化的稳定性的常规存储器单元，以便在与常规存储器单元中的故障相比时引发早期失败; 从所述至少一个监视器单元读取所述随机数据; 将读取操作的输出数据与期望值进行比较以检测值不匹配; 并且如果检测到不匹配值，则将值不匹配报告给错误结构。

7. 发明申请

US20070165447A1 Asymmetrical Random Access Memory Cell, A Memory Comprising Asymmetrical Memory Cells And A Method To Operate Such A Memory 有权
标题翻译：非对称随机存取存储器单元，包含不对称存储单元的存储器和一种操作这样的存储器的方法
公开(公告)号：US20070165447A1
公开(公告)日：2007-07-19
申请号：US11623443
申请日：2007-01-16
申请人： Otto Wagner , Sebastian Ehrenreich , Torsten Mahnke , Anthony Gus Aipperspach
发明人： Otto Wagner , Sebastian Ehrenreich , Torsten Mahnke , Anthony Gus Aipperspach
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： Asymmetrical random access memory cell (1) comprising cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (blt, blc) of a pair of complementary bit-lines, which are connected via a pass-transistor (21, 31), wherein the random access memory cell is asymmetrical by means of the cross coupled inverters (2, 3) which have asymmetrically physical behaviours whereby different switching thresholds of the inverters are present, and that the pass-transistors (21, 31) are driven by separate controlled wordlines (wl, wwl). Furthermore the invention relates to a random access memory comprising a plurality of such asymmetrical random access memory cells and to a method to operate such a random access memory.
摘要翻译：非对称随机存取存储单元（1）包括交叉耦合的反相器（2,3），它们通过一对互补位线的分开的位线（blt，blc）在其节点（22,32）处被驱动，所述位线连接通过通过晶体管（21,31），其中随机存取存储单元通过具有不对称物理行为的交叉耦合反相器（2,3）不对称，从而存在逆变器的不同切换阈值，并且通过 - 晶体管（21,31）由单独的受控字线（w1，wwl）驱动。此外，本发明涉及包括多个这样的非对称随机存取存储器单元的随机存取存储器和一种操作这样的随机存取存储器的方法。

8. 发明申请

US20070165343A1 Circuit Arrangement and Method to Reduce Leakage Power and to Increase the Performance of a Circuit 审中-公开
标题翻译：电路布置和降低漏电功率和提高电路性能的方法
公开(公告)号：US20070165343A1
公开(公告)日：2007-07-19
申请号：US11553037
申请日：2006-10-26
申请人： Harry Barowski , Sebastian Ehrenreich , Tobias Gemmeke , Jens Leenstra
发明人： Harry Barowski , Sebastian Ehrenreich , Tobias Gemmeke , Jens Leenstra
IPC分类号： H02H9/08
CPC分类号： H03K19/0016 , G06F1/32
摘要： A Circuit arrangement to reduce leakage power and to increase the performance of a circuit comprising three electric potentials is described, wherein a diode is arranged between the third and the second or first electric potential to obtain a potential drop of the third electric potential and parallel to said diode a switch is arranged between the third and the second or between the third and the first electric potential to change the potential drop of the third electric potential opposite to the first or the second electric potential about the voltage drop of said diode wherein said switch comprises a transistor having a broad transistor channel. Furthermore a method to reduce leakage power and to increase the performance of a circuit by using said circuit arrangement is described.
摘要翻译：描述了一种降低泄漏功率并增加包括三个电势的电路的性能的电路装置，其中二极管被布置在第三和第二或第一电位之间以获得第三电位的电位降并平行于所述二极管的开关被布置在第三和第二之间或者在第三和第一电位之间，以改变与围绕所述二极管的电压降的第一或第二电位相反的第三电位的电势降，其中所述开关包括具有宽晶体管沟道的晶体管。此外，描述了通过使用所述电路装置来减少漏电功率和提高电路性能的方法。

9. 发明申请

US20060179396A1 Redundancy in signal distribution trees 有权
标题翻译：信号分配树的冗余
公开(公告)号：US20060179396A1
公开(公告)日：2006-08-10
申请号：US11350149
申请日：2006-02-08
申请人： Sebastian Ehrenreich , Juergen Koehl , Juergen Pille
发明人： Sebastian Ehrenreich , Juergen Koehl , Juergen Pille
IPC分类号： H03M13/00
CPC分类号： G06F1/10 , H03K5/15013 , H03K19/007
摘要： A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (11) is driven by a preceding amplifier (2), which is characterized in that the amplifiers are logic gates (3), which combines the signals of a preferred input (31) connected to a preceding logic gate in the signal path with a signal of a secondary input (32) connected to an adjacent tree (12) path of a neighboring and/or preceding sub tree.
摘要翻译：一种信号分配树结构，用于将多个信号树分支中的信号分配到多个信号宿，其中后续子树（11）中的信号由前一放大器（2）驱动，其特征在于放大器是逻辑门（3），其将连接到信号路径中的先前逻辑门的优选输入（31）的信号与连接到邻近的相邻树（12）路径的次级输入（32）的信号组合，以及 /或前一个子树。

10. 发明申请

US20100237700A1 Signal Repowering Chip For 3-Dimensional Integrated Circuit 失效
标题翻译： 3维集成电路信号重新加工芯片
公开(公告)号：US20100237700A1
公开(公告)日：2010-09-23
申请号：US12754054
申请日：2010-04-05
申请人： Markus Buehler , Sebastian Ehrenreich , Juergen Koehl
发明人： Markus Buehler , Sebastian Ehrenreich , Juergen Koehl
IPC分类号： H05K1/02 , H01L27/06 , H01L21/66
CPC分类号： G01R31/2889 , G01R31/318513 , H01L2924/0002 , Y10T307/492 , H01L2924/00
摘要： A signal repowering chip comprises an input; at least one inverter connected in series to the input; and at least one switch connected to a test enable signal, the at least one switch configured to allow a signal connected to the input to propagate through the at least one inverter in the event that the test enable signal is on. A 3-dimensional integrated circuit comprises a first chip, the first chip comprising a default voltage level and a plurality of wiring layers; and a second chip, the second chip comprising at least one repeater, the repeater being connected to the default voltage level.
摘要翻译：一个信号重启芯片包括一个输入端; 至少一个反相器串联连接到输入端; 以及连接到测试使能信号的至少一个开关，所述至少一个开关被配置为在测试使能信号为导通的情况下允许连接到所述输入的信号传播通过所述至少一个逆变器。 3维集成电路包括第一芯片，第一芯片包括默认电压电平和多个布线层; 和第二芯片，所述第二芯片包括至少一个中继器，所述中继器连接到所述默认电压电平。

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