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1. 发明授权

US08513663B2 Signal repowering chip for 3-dimensional integrated circuit 失效
标题翻译：三维集成电路信号重新加工芯片
公开(公告)号：US08513663B2
公开(公告)日：2013-08-20
申请号：US12754054
申请日：2010-04-05
申请人： Markus Buehler , Sebastian Ehrenreich , Juergen Koehl
发明人： Markus Buehler , Sebastian Ehrenreich , Juergen Koehl
IPC分类号： H01L23/58 , H01L29/10
CPC分类号： G01R31/2889 , G01R31/318513 , H01L2924/0002 , Y10T307/492 , H01L2924/00
摘要： A signal repowering chip comprises an input; at least one inverter connected in series to the input; and at least one switch connected to a test enable signal, the at least one switch configured to allow a signal connected to the input to propagate through the at least one inverter in the event that the test enable signal is on. A 3-dimensional integrated circuit comprises a first chip, the first chip comprising a default voltage level and a plurality of wiring layers; and a second chip, the second chip comprising at least one repeater, the repeater being connected to the default voltage level.
摘要翻译：一个信号重启芯片包括一个输入端; 至少一个反相器串联连接到输入端; 以及连接到测试使能信号的至少一个开关，所述至少一个开关被配置为在测试使能信号为导通的情况下允许连接到所述输入的信号传播通过所述至少一个逆变器。 3维集成电路包括第一芯片，第一芯片包括默认电压电平和多个布线层; 和第二芯片，所述第二芯片包括至少一个中继器，所述中继器连接到所述默认电压电平。

2. 发明申请

US20100237700A1 Signal Repowering Chip For 3-Dimensional Integrated Circuit 失效
标题翻译： 3维集成电路信号重新加工芯片
公开(公告)号：US20100237700A1
公开(公告)日：2010-09-23
申请号：US12754054
申请日：2010-04-05
申请人： Markus Buehler , Sebastian Ehrenreich , Juergen Koehl
发明人： Markus Buehler , Sebastian Ehrenreich , Juergen Koehl
IPC分类号： H05K1/02 , H01L27/06 , H01L21/66
CPC分类号： G01R31/2889 , G01R31/318513 , H01L2924/0002 , Y10T307/492 , H01L2924/00
摘要： A signal repowering chip comprises an input; at least one inverter connected in series to the input; and at least one switch connected to a test enable signal, the at least one switch configured to allow a signal connected to the input to propagate through the at least one inverter in the event that the test enable signal is on. A 3-dimensional integrated circuit comprises a first chip, the first chip comprising a default voltage level and a plurality of wiring layers; and a second chip, the second chip comprising at least one repeater, the repeater being connected to the default voltage level.
摘要翻译：一个信号重启芯片包括一个输入端; 至少一个反相器串联连接到输入端; 以及连接到测试使能信号的至少一个开关，所述至少一个开关被配置为在测试使能信号为导通的情况下允许连接到所述输入的信号传播通过所述至少一个逆变器。 3维集成电路包括第一芯片，第一芯片包括默认电压电平和多个布线层; 和第二芯片，所述第二芯片包括至少一个中继器，所述中继器连接到所述默认电压电平。

3. 发明授权

US07755408B2 Redundancy in signal distribution trees 有权
标题翻译：信号分配树的冗余
公开(公告)号：US07755408B2
公开(公告)日：2010-07-13
申请号：US11868637
申请日：2007-10-08
申请人： Sebastian Ehrenreich , Juergen Koehl , Juergen Pille
发明人： Sebastian Ehrenreich , Juergen Koehl , Juergen Pille
IPC分类号： G06F1/04 , H03K1/04
CPC分类号： G06F1/10 , H03K5/15013 , H03K19/007
摘要： A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (11) is driven by a preceding amplifier (2), which is characterized in that the amplifiers are logic gates (3), which combines the signals of a preferred input (31) connected to a preceding logic gate in the signal path with a signal of a secondary input (32) connected to an adjacent tree (12) path of a neighboring and/our preceding sub tree.
摘要翻译：一种信号分配树结构，用于将多个信号树分支中的信号分配到多个信号宿，其中后续子树（11）中的信号由前一放大器（2）驱动，其特征在于放大器是逻辑门（3），其将连接到信号路径中的先前逻辑门的优选输入（31）的信号与连接到邻近的相邻树（12）路径的次级输入（32）的信号组合，以及 /我们以前的子树。

4. 发明授权

US07336115B2 Redundancy in signal distribution trees 有权
标题翻译：信号分配树的冗余
公开(公告)号：US07336115B2
公开(公告)日：2008-02-26
申请号：US11350149
申请日：2006-02-08
申请人： Sebastian Ehrenreich , Juergen Koehl , Juergen Pille
发明人： Sebastian Ehrenreich , Juergen Koehl , Juergen Pille
IPC分类号： G06F1/04 , H03K1/04
CPC分类号： G06F1/10 , H03K5/15013 , H03K19/007
摘要： A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (11) is driven by a preceding amplifier (2), which is characterized in that the amplifiers are logic gates (3), which combines the signals of a preferred input (31) connected to a preceding logic gate in the signal path with a signal of a secondary input (32) connected to an adjacent tree (12) path of a neighboring and/or preceding sub tree.
摘要翻译：一种信号分配树结构，用于将多个信号树分支中的信号分配到多个信号宿，其中后续子树（11）中的信号由前一放大器（2）驱动，其特征在于放大器是逻辑门（3），其将连接到信号路径中的先前逻辑门的优选输入（31）的信号与连接到邻近的相邻树（12）路径的次级输入（32）的信号组合，以及 /或前一个子树。

5. 发明申请

US20080256413A1 Redundancy in Signal Distribution Trees 有权
标题翻译：信号分配树的冗余
公开(公告)号：US20080256413A1
公开(公告)日：2008-10-16
申请号：US11868637
申请日：2007-10-08
申请人： Sebastian Ehrenreich , Juergen Koehl , Juergen Pille
发明人： Sebastian Ehrenreich , Juergen Koehl , Juergen Pille
IPC分类号： H03M13/00
CPC分类号： G06F1/10 , H03K5/15013 , H03K19/007
摘要： A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (11) is driven by a preceding amplifier (2), which is characterized in that the amplifiers are logic gates (3), Which combines the signals of a preferred input (31) connected to a preceding logic gate in the signal path with a signal, of a secondary input (32) connected to an adjacent tree (12) path of a neighboring and/our preceding sub tree.
摘要翻译：一种信号分配树结构，用于将多个信号树分支中的信号分配到多个信号宿，其中后续子树（11）中的信号由前一放大器（2）驱动，其特征在于放大器是逻辑门（3），其将连接到信号路径中的先前逻辑门的优选输入（31）的信号与连接到相邻的邻近树（12）路径的次级输入（32）的信号组合和/我们的前一个子树。

6. 发明申请

US20060179396A1 Redundancy in signal distribution trees 有权
标题翻译：信号分配树的冗余
公开(公告)号：US20060179396A1
公开(公告)日：2006-08-10
申请号：US11350149
申请日：2006-02-08
申请人： Sebastian Ehrenreich , Juergen Koehl , Juergen Pille
发明人： Sebastian Ehrenreich , Juergen Koehl , Juergen Pille
IPC分类号： H03M13/00
CPC分类号： G06F1/10 , H03K5/15013 , H03K19/007
摘要： A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (11) is driven by a preceding amplifier (2), which is characterized in that the amplifiers are logic gates (3), which combines the signals of a preferred input (31) connected to a preceding logic gate in the signal path with a signal of a secondary input (32) connected to an adjacent tree (12) path of a neighboring and/or preceding sub tree.
摘要翻译：一种信号分配树结构，用于将多个信号树分支中的信号分配到多个信号宿，其中后续子树（11）中的信号由前一放大器（2）驱动，其特征在于放大器是逻辑门（3），其将连接到信号路径中的先前逻辑门的优选输入（31）的信号与连接到邻近的相邻树（12）路径的次级输入（32）的信号组合，以及 /或前一个子树。

7. 发明授权

US08234594B2 Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same 有权
标题翻译：冗余微环结构用于集成电路物理设计过程及其形成方法
公开(公告)号：US08234594B2
公开(公告)日：2012-07-31
申请号：US11552225
申请日：2006-10-24
申请人： Brent A. Anderson , Jeanne P. Bickford , Markus Buehler , Jason D. Hibbeler , Juergen Koehl , Edward J. Nowak
发明人： Brent A. Anderson , Jeanne P. Bickford , Markus Buehler , Jason D. Hibbeler , Juergen Koehl , Edward J. Nowak
IPC分类号： G06F17/50 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located at a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is approximately axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is approximately axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.
摘要翻译：一种集成电路，包括第一级布线轨道的第一线，第二级布线轨道的第二线，第三级布线轨道的第三线和位于距离第二线的第一距离的第四线在第二级线路上。第一通孔在第二导线的第一位置连接第一和第二导线。第二通孔在第一位置处连接第二和第三导线，第二通孔大致轴向对准第一通孔。第三通过在第四线的第二位置连接第三和第四导线。在第二位置连接第一和第四导线的第四通孔，第四通孔与第三通孔大致轴向对齐。第二，第三和第四通孔以及第三和第四导线形成第一和第二导线之间的路径，该路径对于第一通孔是冗余的。

8. 发明授权

US07984394B2 Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same 有权
标题翻译：用于集成电路物理设计过程中使用的冗余微环结构的设计结构及其形成方法
公开(公告)号：US07984394B2
公开(公告)日：2011-07-19
申请号：US11955580
申请日：2007-12-13
申请人： Brent A. Anderson , Jeanne P. Bickford , Markus Buehler , Jason D. Hibbeler , Juergen Koehl , Edward J. Nowak
发明人： Brent A. Anderson , Jeanne P. Bickford , Markus Buehler , Jason D. Hibbeler , Juergen Koehl , Edward J. Nowak
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A design structure for an integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.
摘要翻译：一种用于集成电路的设计结构，该集成电路包括第一级布线轨道的第一线，第二级布线轨道的第二线，第三级布线轨道的第三线，以及位于第一距离处的第四线第二根电线在第二级线路上。第一通孔在第二导线的第一位置连接第一和第二导线。第二通孔在第一位置处连接第二和第三导线，第二通孔基本上与第一通孔轴向对准。第三通过在第四线的第二位置连接第三和第四导线。第四通孔在第二位置处连接第一和第四导线，第四通孔基本上与第三通孔轴向对准。第二，第三和第四通孔以及第三和第四导线形成第一和第二导线之间的路径，该路径对于第一通孔是冗余的。

9. 发明授权

US07386815B2 Test yield estimate for semiconductor products created from a library 有权
标题翻译：从图书馆创建的半导体产品的测试产量估算
公开(公告)号：US07386815B2
公开(公告)日：2008-06-10
申请号：US11163696
申请日：2005-10-27
申请人： Jeanne Bickford , Markus Buehler , Jason D. Hibbeler , Juergen Koehl
发明人： Jeanne Bickford , Markus Buehler , Jason D. Hibbeler , Juergen Koehl
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Disclosed is a method that predicts test yield for a semiconductor product, prior to design layout. This is accomplished by applying a critical area analysis to individual library elements that are used to form a specific product and by estimating the test yield impact of combining these library elements. For example, the method considers the test yield impact of sensitivity to library element to library element shorts and the test yield impact of sensitivity to wiring faults. The disclosed method further allows die size growth to be traded off against the use of library elements with higher test yield in order to provide an optimal design solution. Thus, the method may be used to modify library element selection so as to optimize test yield. Lastly, the method further repeats itself at key design checkpoints to revalidate initial test yield (and cost) assumptions made when the product was quoted to a customer. Thus, the method provides increased accuracy of test yield estimate from initial sizing through design and further allows designs to be modified to improve test yield.
摘要翻译：公开了一种在设计布局之前预测半导体产品的测试产量的方法。这是通过对用于形成特定产品的单个库元素应用关键区域分析，并通过估计组合这些库元素的测试产出影响来实现的。例如，该方法考虑了库元素对库元素短路的灵敏度的测试产量影响以及对接线故障的灵敏度的测试产量影响。所公开的方法进一步允许模具尺寸增长与使用具有较高测试成品率的库元件进行交易，以便提供最佳设计解决方案。因此，该方法可用于修改库元素选择以优化测试产量。最后，该方法在关键设计检查点进一步重复，以重新验证产品被引用给客户时的初始测试收益（和成本）假设。因此，该方法通过设计从初始尺寸提高了测试产量估算的准确度，并进一步允许修改设计以提高测试产量。

10. 发明授权

US07996808B2 Computer readable medium, system and associated method for designing integrated circuits with loop insertions 有权
标题翻译：用循环插入设计集成电路的计算机可读介质，系统和相关方法
公开(公告)号：US07996808B2
公开(公告)日：2011-08-09
申请号：US12146921
申请日：2008-06-26
申请人： Andreas Arp , Jeanne P. Bickford , Markus Buehler , Juergen Koehl , Philipp Salz
发明人： Andreas Arp , Jeanne P. Bickford , Markus Buehler , Juergen Koehl , Philipp Salz
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A computer readable medium, system and associated method is provided for designing an integrated circuit with inserted loops. The method comprises the steps of inserting a loop with tagged wire segments and/or vias in a fully routed and DCR clean integrated circuit; performing a DRC; and fixing DRC violations by removing tagged wire segments and/or vias which contribute to a violation.
摘要翻译：提供了一种用于设计具有插入环路的集成电路的计算机可读介质，系统和相关方法。该方法包括以下步骤：将带有标记的线段和/或过孔的回路插入完全路由和DCR清洁集成电路中; 执行刚果民主共和国并通过删除有助于违规的标记线段和/或过孔来修复DRC违规。

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