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1. 发明申请

US20080273403A1 STORAGE CELL DESIGN EVALUATION CIRCUIT INCLUDING A WORDLINE TIMING AND CELL ACCESS DETECTION CIRCUIT 失效
标题翻译：存储单元设计评估电路，包括WORDLINE时序和细胞检测电路
公开(公告)号：US20080273403A1
公开(公告)日：2008-11-06
申请号：US12125011
申请日：2008-05-21
申请人： Sebastian Ehrenreich , Jente B. Kuang , Chun-Tao Li , Hung Cai Ngo
发明人： Sebastian Ehrenreich , Jente B. Kuang , Chun-Tao Li , Hung Cai Ngo
IPC分类号： G11C7/00 , G11C8/08
CPC分类号： G11C29/50 , G11C11/41 , G11C29/02 , G11C29/025 , G11C29/50012
摘要： A storage cell design evaluation circuit including a wordline timing and cell access detection circuit provides accurate information about state changes in static storage cells. A storage cell test row includes the access detection circuit, which provides the same loading during an access operation as the other cells in the array. The access detection circuit provides an output that may be probed without affecting the timing, read stability or writeability of the cell. The test row can test the clock and/or address timing of the row and may include a separate power supply rail for the row wordline driver, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.
摘要翻译：包括字线定时和单元访问检测电路的存储单元设计评估电路提供关于静态存储单元中的状态变化的精确信息。存储单元测试行包括访问检测电路，其在与阵列中的其他单元的访问操作期间提供相同的负载。访问检测电路提供可以探测的输出，而不影响单元的定时，读取稳定性或可写性。测试行可以测试行的时钟和/或地址时序，并且可以包括用于行字线驱动器的单独的电源轨，从而可以确定访问时序，读取稳定性和可写入性与字线强度/访问电压的变化。多个测试行可以在列之间级联，以提供长延迟线或环形振荡器，以提高测量分辨率。

2. 发明申请

US20080137455A1 Storage Cell Design Evaluation Circuit Including a Wordline Timing and Cell Access Detection Circuit 失效
标题翻译：包括字线定时和单元访问检测电路的存储单元设计评估电路
公开(公告)号：US20080137455A1
公开(公告)日：2008-06-12
申请号：US11609598
申请日：2006-12-12
申请人： Sebastian Ehrenreich , Jente B Kuang , Chun-Tao Li , Hung Cai Ngo
发明人： Sebastian Ehrenreich , Jente B Kuang , Chun-Tao Li , Hung Cai Ngo
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/02 , G11C29/025 , G11C29/50012
摘要： A method for storage cell design evaluation provides accurate information about state changes in static storage cells. A wordline select pulse is propagated along the wordline select path of the test row to an output driver circuit, in order to test the clock and/or address timing of the row, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. An access detection cell holds the input of the output driver circuit until a simulated access operation activated by the wordline select pulse is complete. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.
摘要翻译：用于存储单元设计评估的方法提供关于静态存储单元中的状态变化的准确信息。字线选择脉冲沿着测试行的字线选择路径传播到输出驱动器电路，以便测试该行的时钟和/或地址时序，使得访问时序，读取稳定性和可写性与字线强度的变化 /访问电压可以确定。访问检测单元保持输出驱动器电路的输入，直到由字线选择脉冲激活的模拟访问操作完成。多个测试行可以在列之间级联，以提供长延迟线或环形振荡器，以提高测量分辨率。

3. 发明授权

US07414904B2 Method for evaluating storage cell design using a wordline timing and cell access detection circuit 失效
标题翻译：使用字线定时和单元访问检测电路评估存储单元设计的方法
公开(公告)号：US07414904B2
公开(公告)日：2008-08-19
申请号：US11609598
申请日：2006-12-12
申请人： Sebastian Ehrenreich , Jente B Kuang , Chun-Tao Li , Hung Cai Ngo
发明人： Sebastian Ehrenreich , Jente B Kuang , Chun-Tao Li , Hung Cai Ngo
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/02 , G11C29/025 , G11C29/50012
摘要： A method for storage cell design evaluation provides accurate information about state changes in static storage cells. A wordline select pulse is propagated along the wordline select path of the test row to an output driver circuit, in order to test the clock and/or address timing of the row, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. An access detection cell holds the input of the output driver circuit until a simulated access operation activated by the wordline select pulse is complete. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.
摘要翻译：用于存储单元设计评估的方法提供关于静态存储单元中的状态变化的准确信息。字线选择脉冲沿着测试行的字线选择路径传播到输出驱动器电路，以便测试该行的时钟和/或地址时序，使得访问时序，读取稳定性和可写性与字线强度的变化 /访问电压可以确定。访问检测单元保持输出驱动器电路的输入，直到由字线选择脉冲激活的模拟访问操作完成。多个测试行可以在列之间级联，以提供长延迟线或环形振荡器，以提高测量分辨率。

4. 发明授权

US07564739B2 Storage cell design evaluation circuit including a wordline timing and cell access detection circuit 失效
标题翻译：存储单元设计评估电路，包括字线定时和单元访问检测电路
公开(公告)号：US07564739B2
公开(公告)日：2009-07-21
申请号：US12125011
申请日：2008-05-21
申请人： Sebastian Ehrenreich , Jente B Kuang , Chun-Tao Li , Hung Kai Ngo
发明人： Sebastian Ehrenreich , Jente B Kuang , Chun-Tao Li , Hung Kai Ngo
IPC分类号： G11C8/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/02 , G11C29/025 , G11C29/50012
摘要： A storage cell design evaluation circuit including a wordline timing and cell access detection circuit provides accurate information about state changes in static storage cells. A storage cell test row includes the access detection circuit, which provides the same loading during an access operation as the other cells in the array. The access detection circuit provides an output that may be probed without affecting the timing, read stability or writeability of the cell. The test row can test the clock and/or address timing of the row and may include a separate power supply rail for the row wordline driver, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.
摘要翻译：包括字线定时和单元访问检测电路的存储单元设计评估电路提供关于静态存储单元中的状态变化的精确信息。存储单元测试行包括访问检测电路，其在与阵列中的其他单元的访问操作期间提供相同的负载。访问检测电路提供可以探测的输出，而不影响单元的定时，读取稳定性或可写性。测试行可以测试行的时钟和/或地址时序，并且可以包括用于行字线驱动器的单独的电源轨，从而可以确定访问时序，读取稳定性和可写入性与字线强度/访问电压的变化。多个测试行可以在列之间级联，以提供长延迟线或环形振荡器，以提高测量分辨率。

5. 发明授权

US07788306B2 On-demand numerical conversion 有权
标题翻译：按需数字转换
公开(公告)号：US07788306B2
公开(公告)日：2010-08-31
申请号：US11457290
申请日：2006-07-13
申请人： Pernell James Dykes , Chun-Tao Li
发明人： Pernell James Dykes , Chun-Tao Li
IPC分类号： G06F5/00
CPC分类号： G06Q90/00
摘要： An apparatus, program product and method provide on-demand numerical conversion of convertible numerical values such as measurements and monetary values. A numerical value that is displayed in a document such as a web page, and that is represented in a native unit, may be converted to a value represented in a local unit for a user viewing the document. That converted numerical value may then be displayed adjacent the original numerical value, and typically along with an indication of the local unit, in response to the user positioning a pointer over the original (unconverted) numerical value, so that the user can quickly comprehend the numerical value in units to which he or she is accustomed.
摘要翻译：装置，程序产品和方法提供可转换数值的按需数值转换，例如测量值和货币值。在诸如网页的文档中显示并以本机单元表示的数值可以被转换为用于查看文档的用户在本地单元中表示的值。然后可以响应于用户将指针定位在原始（未转换的）数值上，使得用户可以快速地理解该转换的数值，并且通常与本地单元的指示一起显示与原始数值相邻的转换数值。他或她习惯的单位的数值。

6. 发明申请

US20080079158A1 METAL FILL REGION OF A SEMICONDUCTOR CHIP 失效
标题翻译：金属填充区半导体芯片
公开(公告)号：US20080079158A1
公开(公告)日：2008-04-03
申请号：US11538118
申请日：2006-10-03
申请人： Steven J. Baumgartner , Chun-Tao Li , Salvatore N. Storino , Mankit Wong
发明人： Steven J. Baumgartner , Chun-Tao Li , Salvatore N. Storino , Mankit Wong
IPC分类号： H01L23/52
CPC分类号： H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a metal fill region of a semiconductor chip including a plurality of layer sets of the semiconductor chip, each set including a first metal fill layer, a second metal fill layer, and an insulation layer included disposed in planes parallel to each other, a plurality of metal fill pieces disposed in each of the metal fill layers, a metal fill piece axis of each of the pieces, wherein each of the axes perpendicularly intersects the planes of said metal fill layers and the insulation layer from any point of reference, and a metal fill pattern configured to position the pieces so that the axis of each piece in the first metal fill layer is linearly displaced of the axis of each piece in the second metal fill layer in at least one direction orthogonal to each of the metal fill axes.
摘要翻译：公开了一种半导体芯片的金属填充区域，其包括半导体芯片的多个层组，每组包括设置在彼此平行的平面中的第一金属填充层，第二金属填充层和绝缘层，设置在每个金属填充层中的多个金属填充片，每个片的金属填充片轴线，其中每个轴与任何参考点垂直地相交于所述金属填充层的平面和绝缘层，以及金属填充图案，被配置为定位所述片，使得所述第一金属填充层中的每个片的轴线在与所述金属填充轴中的每一个垂直的至少一个方向上在所述第二金属填充层中的每个片的轴线线性位移。

7. 发明授权

US07489039B2 Metal fill region of a semiconductor chip 失效
标题翻译：半导体芯片的金属填充区域
公开(公告)号：US07489039B2
公开(公告)日：2009-02-10
申请号：US11538118
申请日：2006-10-03
申请人： Steven J. Baumgartner , Chun-Tao Li , Salvatore N. Storino , Mankit Wong
发明人： Steven J. Baumgartner , Chun-Tao Li , Salvatore N. Storino , Mankit Wong
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a metal fill region of a semiconductor chip including a plurality of layer sets of the semiconductor chip, each set including a first metal fill layer, a second metal fill layer, and an insulation layer included disposed in planes parallel to each other, a plurality of metal fill pieces disposed in each of the metal fill layers, a metal fill piece axis of each of the pieces, wherein each of the axes perpendicularly intersects the planes of said metal fill layers and the insulation layer from any point of reference, and a metal fill pattern configured to position the pieces so that the axis of each piece in the first metal fill layer is linearly displaced of the axis of each piece in the second metal fill layer in at least one direction orthogonal to each of the metal fill axes.
摘要翻译：公开了一种半导体芯片的金属填充区域，其包括半导体芯片的多个层组，每组包括设置在彼此平行的平面中的第一金属填充层，第二金属填充层和绝缘层，设置在每个金属填充层中的多个金属填充片，每个片的金属填充片轴线，其中每个轴与任何参考点垂直地相交于所述金属填充层的平面和绝缘层，以及金属填充图案，被配置为定位所述片，使得所述第一金属填充层中的每个片的轴线在与所述金属填充轴中的每一个垂直的至少一个方向上在所述第二金属填充层中的每个片的轴线线性位移。

8. 发明申请

US20090024975A1 SYSTEMS, METHODS AND COMPUTER PRODUCTS FOR TRAVERSING DESIGN HIERARCHY USING A SCROLL MECHANISM 审中-公开
标题翻译：使用滚动机构跟踪设计分层的系统，方法和计算机产品
公开(公告)号：US20090024975A1
公开(公告)日：2009-01-22
申请号：US11778926
申请日：2007-07-17
申请人： Karl L. Ladin , Chun-Tao Li , Salvatore N. Storino
发明人： Karl L. Ladin , Chun-Tao Li , Salvatore N. Storino
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method and an apparatus are disclosed for the display of hierarchical navigation in the automated design of integrated circuits under test. A user, using a computer, assigns a head pointer assignment and a tail pointer assignment, which form a definition of a viewable scope of at least one hierarchical level of design from a plurality of hierarchical levels of design. These head pointer and tail pointer assignments are stored in a repository of the computer to set the definition of the viewable scope of the at least one hierarchical level of design. After being set, the viewable scope of the at least one hierarchical level of design is displayed on a computer display device, where the viewable scope of the at least one hierarchical level of design can be traversed by moving a scrolling mechanism up and down in the viewable scope of the at least one hierarchical level of design.
摘要翻译：公开了用于在被测集成电路的自动化设计中显示分级导航的方法和装置。使用计算机的用户分配头指针分配和尾指针分配，其从多个分级设计级别形成至少一个层级设计的可见范围的定义。这些头部指针和尾部指针分配存储在计算机的存储库中，以设置至少一个层级设计的可见范围的定义。在设置之后，将至少一个层级设计的可视范围显示在计算机显示设备上，其中可以通过在上下文中移动滚动机构来遍历至少一个层级设计的可视范围至少一个层级设计的可见范围。

9. 发明申请

US20080178133A1 Method and Apparatus for Implementing Enhanced Timing Performance Through Bus Signal Wire Permutation With Repowering Buffers 审中-公开
标题翻译：通过总线信号线排列来实现增强型时序性能的方法和装置
公开(公告)号：US20080178133A1
公开(公告)日：2008-07-24
申请号：US11626417
申请日：2007-01-24
申请人： Jente Benedict Kuang , Chun-Tao Li , Salvatore Nicholas Storino
发明人： Jente Benedict Kuang , Chun-Tao Li , Salvatore Nicholas Storino
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F13/4004 , H03K19/00323
摘要： A method and apparatus implement improved timing performance of a signal bus through wire permutation with repowering buffers. A repowering buffer includes a prebuffer and a postbuffer. A plurality of prebuffers and postbuffers are stored in a design library, each having a set wiring ordered arrangement for selectively providing wire permutation of the signal bus. A wiring order of prebuffer at the beginning of the bus is identical to the wiring order of the postbuffer at the end of bus. The wiring order of the postbuffer driving the beginning of bus wires between adjacent repowering buffers is identical to the wiring order of the prebuffer receiving at the end of the bus wires. A wiring order of the downstream buffer pairs is chosen so that there is at least one pair of wires separated by another wire or wires in the bus.
摘要翻译：一种方法和装置通过重新供电缓冲器通过线排列来实现信号总线的改进的定时性能。重新启动缓冲区包括预缓冲区和缓冲区。多个预缓冲器和后缓冲器存储在设计库中，每个具有设置的布线排列布置，用于选择性地提供信号总线的布线置换。总线开始时的预缓冲器的布线顺序与总线末尾的后缓冲器的布线顺序相同。在相邻的再供电缓冲器之间驱动母线的开始的后缓冲器的布线顺序与在总线末端接收的预缓冲器的布线顺序相同。选择下游缓冲器对的布线顺序，使得在总线中存在由另一条导线或电线分开的至少一对导线。

10. 发明申请

US20080266246A1 TRAVERSING GRAPHICAL LAYERS USING A SCROLLING MECHANISM IN A PHYSICAL DESIGN ENVIRONMENT 审中-公开
标题翻译：在物理设计环境中使用滚动机构处理图形层
公开(公告)号：US20080266246A1
公开(公告)日：2008-10-30
申请号：US11739911
申请日：2007-04-25
申请人： Karl L. Ladin , Chun-Tao Li , Salvatore N. Storino
发明人： Karl L. Ladin , Chun-Tao Li , Salvatore N. Storino
IPC分类号： G06F3/048 , G06F15/00 , G09G5/08
CPC分类号： G06F3/0485
摘要： Z-axis display navigation in the design automation process of physical design, development and manufacturing of integrated circuits includes pre-selecting, using a computer mouse connected to a computer workstation processor, viewable graphical layout layers desired by a design layout debugging operator to view during an integrated circuit (IC) design debugging process. After selecting the desired viewable graphic layout layers, the layout operator uses the mouse to traverse the pre-selected viewable graphical layout layers displayed, by changing the input scrolling pattern of the mouse to scroll forward, backward, diagonally and from side to side in a plurality of directions, where a curser on the layout screen will correspondingly move in the plurality of directions in the pre-selected viewable graphical layout layers on the layout screen corresponding to the movement of the mouse by the operator.
摘要翻译： Z轴显示导航在设计自动化过程中的物理设计，开发和制造集成电路包括预先选择，使用连接到计算机工作站处理器的计算机鼠标，通过设计布局调试操作员所需的可见图形布局层来查看集成电路（IC）设计调试过程。在选择所需的可见图形布局图层之后，布局运算符通过改变鼠标的输入滚动模式来滚动向前，向后，向对角和从一侧到另一侧，使用鼠标遍历预先选择的可视图形布局图层。多个方向，其中布局屏幕上的卷曲器将相应地在布局屏幕上的预选择的可视图形布局层中的多个方向上移动，对应于操作者对鼠标的移动。

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