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1. 发明申请

US20080178133A1 Method and Apparatus for Implementing Enhanced Timing Performance Through Bus Signal Wire Permutation With Repowering Buffers 审中-公开
标题翻译：通过总线信号线排列来实现增强型时序性能的方法和装置
公开(公告)号：US20080178133A1
公开(公告)日：2008-07-24
申请号：US11626417
申请日：2007-01-24
申请人： Jente Benedict Kuang , Chun-Tao Li , Salvatore Nicholas Storino
发明人： Jente Benedict Kuang , Chun-Tao Li , Salvatore Nicholas Storino
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F13/4004 , H03K19/00323
摘要： A method and apparatus implement improved timing performance of a signal bus through wire permutation with repowering buffers. A repowering buffer includes a prebuffer and a postbuffer. A plurality of prebuffers and postbuffers are stored in a design library, each having a set wiring ordered arrangement for selectively providing wire permutation of the signal bus. A wiring order of prebuffer at the beginning of the bus is identical to the wiring order of the postbuffer at the end of bus. The wiring order of the postbuffer driving the beginning of bus wires between adjacent repowering buffers is identical to the wiring order of the prebuffer receiving at the end of the bus wires. A wiring order of the downstream buffer pairs is chosen so that there is at least one pair of wires separated by another wire or wires in the bus.
摘要翻译：一种方法和装置通过重新供电缓冲器通过线排列来实现信号总线的改进的定时性能。重新启动缓冲区包括预缓冲区和缓冲区。多个预缓冲器和后缓冲器存储在设计库中，每个具有设置的布线排列布置，用于选择性地提供信号总线的布线置换。总线开始时的预缓冲器的布线顺序与总线末尾的后缓冲器的布线顺序相同。在相邻的再供电缓冲器之间驱动母线的开始的后缓冲器的布线顺序与在总线末端接收的预缓冲器的布线顺序相同。选择下游缓冲器对的布线顺序，使得在总线中存在由另一条导线或电线分开的至少一对导线。

2. 发明授权

US08405129B2 Structure for high density stable static random access memory 有权
标题翻译：高密度稳定静态随机存取存储器的结构
公开(公告)号：US08405129B2
公开(公告)日：2013-03-26
申请号：US13450004
申请日：2012-04-18
申请人： Ching-Te K. Chuang , Fadi H. Gebara , Keunwoo Kim , Jente Benedict Kuang , Hung C. Ngo
发明人： Ching-Te K. Chuang , Fadi H. Gebara , Keunwoo Kim , Jente Benedict Kuang , Hung C. Ngo
IPC分类号： H01L27/105
CPC分类号： H01L27/11 , H01L27/0207 , H01L27/1108 , H01L27/1203 , H01L29/78648 , Y10S257/905
摘要： A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit includes a plurality of bit line structures, a plurality of word line structures intersecting said plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at said plurality of cell locations, each of said cells being selectively coupled to a corresponding bit line structure under control of a corresponding word line structure, each of said cells comprising a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor, wherein said at least first n-type field effect transistor is formed with a relatively thick buried oxide layer sized to reduce capacitance of said bit line structures, and said at least first p-type field effect transistor is formed with a relatively thin buried oxide layer.
摘要翻译：一种有形地体现在用于设计，制造或测试集成电路的机器可读介质中的设计结构包括多个位线结构，与所述多个位线结构相交以形成多个单元位置的多个字线结构，以及位于所述多个单元位置处的多个单元，每个所述单元在对应的字线结构的控制下选择性地耦合到对应的位线结构，每个所述单元包括具有至少第一n- 型场效应晶体管和至少第一p型场效应晶体管，其中所述至少第一n型场效应晶体管形成有尺寸适于减小所述位线结构的电容的相对厚的掩埋氧化物层，并且至少所述第一p型场效应晶体管形成有较薄的掩埋氧化物层。

3. 发明申请

US20090302929A1 Methods and Apparatus for Varying a Supply Voltage or Reference Voltage Using Independent Control of Diode Voltage in Asymmetrical Double-Gate Devices 有权
标题翻译：使用非对称双栅极器件中二极管电压的独立控制改变电源电压或参考电压的方法和装置
公开(公告)号：US20090302929A1
公开(公告)日：2009-12-10
申请号：US12511658
申请日：2009-07-29
申请人： Ching-Te Kent Chuang , Keunwoo Kim , Jente Benedict Kuang , Hung Cai Ngo , Kevin John Nowka
发明人： Ching-Te Kent Chuang , Keunwoo Kim , Jente Benedict Kuang , Hung Cai Ngo , Kevin John Nowka
IPC分类号： H03K3/01
CPC分类号： G11C5/147 , G11C11/412 , G11C11/417
摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.
摘要翻译：提供了用于在集成电路中改变电源电压和参考电压中的一个或多个的方法和装置，使用对不对称双栅极器件中的二极管电压的独立控制。提供由电源电压和参考电压中的一个或多个控制的集成电路。集成电路包括独立控制的非对称双栅极器件，用于调节电源电压和参考电压中的一个或多个。独立控制可以包括例如背栅偏置。独立控制的非对称双栅极器件可以用于包括电压岛，静态RAM在内的许多应用中，并且用于改善处理单元的功率和性能。

4. 发明授权

US06635518B2 SOI FET and method for creating FET body connections with high-quality matching characteristics and no area penalty for partially depleted SOI technologies 有权
公开(公告)号：US06635518B2
公开(公告)日：2003-10-21
申请号：US09825704
申请日：2001-04-04
申请人： Anthony Gus Aipperspach , Jente Benedict Kuang , John Edward Sheets, II , Daniel Lawrence Stasiak
发明人： Anthony Gus Aipperspach , Jente Benedict Kuang , John Edward Sheets, II , Daniel Lawrence Stasiak
IPC分类号： H01L2100
CPC分类号： H01L27/1203
摘要： Methods and apparatus are provided for creating field effect transistor (FET) body connections with high-quality matching characteristics and no area penalty for partially depleted silicon-on-insulator (SOI) circuits. The FET body connections are created for partially depleted silicon-on-insulator (SOI) technologies by forming adjacent FET devices inside a shallow trench shape. The adjacent FET devices share a common diffusion area, such as source or drain. Selectively spacing apart adjacent gate lines form an underpath connecting bodies of the adjacent FET devices. The underpath is defined by forming an undepleted region on top of a buried oxide layer. The adjacent polysilicon gate lines are selectively spaced apart to define a depth of depletion in a shared diffusion region for creating the underpath. Also, adjacent FET devices with connecting bodies can be built by adding an ion implant masking step to the fabrication process. This masking step changes the depletion depth under the shared diffusion area. As a result an underpath body connection is formed. Such methods of building adjacent FET devices with an underpath connecting the two device bodies can be used in combination.

5. 发明授权

US08217427B2 High density stable static random access memory 有权
标题翻译：高密度稳定的静态随机存取存储器
公开(公告)号：US08217427B2
公开(公告)日：2012-07-10
申请号：US11865780
申请日：2007-10-02
申请人： Ching-Te K. Chuang , Fadi H. Gebara , Keunwoo Kim , Jente Benedict Kuang , Hung C. Ngo
发明人： Ching-Te K. Chuang , Fadi H. Gebara , Keunwoo Kim , Jente Benedict Kuang , Hung C. Ngo
IPC分类号： H01L27/11
CPC分类号： H01L27/11 , H01L27/0207 , H01L27/1108 , H01L27/1203 , H01L29/78648 , Y10S257/905
摘要： A memory circuit includes a plurality of bit line structures, a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations; and a plurality of cells located at the plurality of cell locations. Each of the cells is selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures, and each of the cells in turn includes a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor. The at least first n-type field effect transistor is formed with a relatively thick buried oxide layer sized to reduce capacitance of the bit line structures, and the at least first p-type field effect transistor is formed with a relatively thin buried oxide layer.
摘要翻译：存储电路包括多个位线结构，多个字线结构与多个位线结构相交以形成多个单元位置; 以及位于多个单元位置的多个单元。每个单元在对应的一个字线结构的控制下选择性地耦合到位线结构中的相应一个，并且每个单元又包括具有至少第一n型场效应的逻辑存储元件晶体管和至少第一p型场效应晶体管。所述至少第一n型场效应晶体管形成有尺寸适于减小所述位线结构的电容的相对较厚的掩埋氧化物层，并且所述至少第一p型场效应晶体管形成有较薄的掩埋氧化物层。

6. 发明授权

US07193446B2 Dynamic logic circuit incorporating reduced leakage state-retaining devices 失效
标题翻译：动态逻辑电路结合了减少的泄漏状态保持装置
公开(公告)号：US07193446B2
公开(公告)日：2007-03-20
申请号：US10992486
申请日：2004-11-18
申请人： Hung Cai Ngo , Jente Benedict Kuang , Harmander Singh Deogun , AJ Kleinosowski
发明人： Hung Cai Ngo , Jente Benedict Kuang , Harmander Singh Deogun , AJ Kleinosowski
IPC分类号： H03K19/094
CPC分类号： H03K19/0963 , H03K19/0016
摘要： A dynamic logic circuit incorporating reduced leakage state-retaining devices reduces power consumption of processors and other systems incorporating dynamic circuits. A keeper circuit provides a low leakage retention of the state of the output stage of the dynamic circuit so that an output circuit foot device can be disabled except when required for a transition in the output of the dynamic circuit. The keeper circuit includes a transistor having a smaller area than a corresponding transistor in the output circuit, thus reducing leakage through the gate of the output circuit when the keeper circuit is holding the output and the output circuit foot device is disabled. A self-clocked control of the output circuit foot device can be provided via a delayed version of the dynamic logic gate output, or may be provided by an external control circuit that generates a delayed version of the precharge clock or a multi-cycle signal.
摘要翻译：结合减少泄漏状态保持装置的动态逻辑电路降低了处理器和其他结合动态电路的系统的功耗。保持器电路提供动态电路的输出级的状态的低泄漏保持，使得输出电路脚装置可以被禁用，除非在动态电路的输出中需要转换。保持器电路包括具有比输出电路中的对应晶体管更小的面积的晶体管，从而当保持器电路保持输出并且输出电路脚器件被禁用时减小通过输出电路的栅极的泄漏。可以通过延迟版本的动态逻辑门输出来提供输出电路脚装置的自定时控制，或者可以由产生预充电时钟的延迟版本或多周期信号的外部控制电路提供。

7. 发明授权

US06373281B1 Tri-state dynamic body charge modulation for sensing devices in SOI RAM applications 失效
标题翻译：用于SOI RAM应用中感测器件的三态动态电荷调制
公开(公告)号：US06373281B1
公开(公告)日：2002-04-16
申请号：US09767218
申请日：2001-01-22
申请人： Ching-Te Kent Chuang , Jente Benedict Kuang
发明人： Ching-Te Kent Chuang , Jente Benedict Kuang
IPC分类号： H03K1900
CPC分类号： G11C7/065
摘要： A method and apparatus are provided for tri-state dynamic body charge modulation for sensing devices in silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) applications. A sense amplifier includes a silicon-on-insulator (SOI) field effect transistor. A tri-state body charge modulation circuit is coupled to a body of the silicon-on-insulator (SOI) field effect transistor. The body charge modulation circuit provides a high body bias preparatory state; a floating body state and a low body bias stand-by state enabling high performance operation, good matching characteristics, and low stand-by leakage suitable for low-power applications. The tri-state body charge modulation circuit includes a P-channel field effect transistor (PFET) and an N-channel field effect transistor (NFET) connected between a high voltage potential and ground. The junction of the series connected PFET and NFET is coupled to the SOI FET body for providing a charging path to a high power supply voltage rail and a discharging path to ground and a high impedance state.
摘要翻译：提供了一种用于感测绝缘体上硅（SOI）互补金属氧化物半导体（CMOS）应用中的器件的三态动态电荷调制的方法和装置。读出放大器包括绝缘体上硅（SOI）场效应晶体管。三态体电荷调制电路耦合到绝缘体上硅（SOI）场效应晶体管的主体。身体电荷调制电路提供高体偏置准备状态; 浮体状态和低体态偏置待机状态，可实现高性能运行，良好的匹配特性，适用于低功率应用的低待机泄漏。三态体电荷调制电路包括连接在高压电位和地之间的P沟道场效应晶体管（PFET）和N沟道场效应晶体管（NFET）。串联连接的PFET和NFET的结连接到SOI FET体，用于提供到高电源电压轨的充电路径和到地的放电路径和高阻抗状态。

8. 发明申请

US20120205721A1 Design Structure for High Density Stable Static Random Access Memory 有权
标题翻译：高密度稳定静态随机存取存储器的设计结构
公开(公告)号：US20120205721A1
公开(公告)日：2012-08-16
申请号：US13450004
申请日：2012-04-18
申请人： Ching-Te K. Chuang , Fadi H. Gebara , Keunwoo Kim , Jente Benedict Kuang , Hung C. Ngo
发明人： Ching-Te K. Chuang , Fadi H. Gebara , Keunwoo Kim , Jente Benedict Kuang , Hung C. Ngo
IPC分类号： H01L27/105
CPC分类号： H01L27/11 , H01L27/0207 , H01L27/1108 , H01L27/1203 , H01L29/78648 , Y10S257/905
摘要： A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit includes a plurality of bit line structures, a plurality of word line structures intersecting said plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at said plurality of cell locations, each of said cells being selectively coupled to a corresponding bit line structure under control of a corresponding word line structure, each of said cells comprising a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor, wherein said at least first n-type field effect transistor is formed with a relatively thick buried oxide layer sized to reduce capacitance of said bit line structures, and said at least first p-type field effect transistor is formed with a relatively thin buried oxide layer.
摘要翻译：一种有形地体现在用于设计，制造或测试集成电路的机器可读介质中的设计结构包括多个位线结构，与所述多个位线结构相交以形成多个单元位置的多个字线结构，以及位于所述多个单元位置处的多个单元，每个所述单元在对应的字线结构的控制下选择性地耦合到对应的位线结构，每个所述单元包括具有至少第一n- 型场效应晶体管和至少第一p型场效应晶体管，其中所述至少第一n型场效应晶体管形成有尺寸适于减小所述位线结构的电容的相对厚的掩埋氧化物层，并且至少所述第一p型场效应晶体管形成有较薄的掩埋氧化物层。

9. 发明申请

US20090302894A1 DUAL GATE TRANSISTOR KEEPER DYNAMIC LOGIC 有权
标题翻译：双门晶体管保持器动态逻辑
公开(公告)号：US20090302894A1
公开(公告)日：2009-12-10
申请号：US11859351
申请日：2007-09-21
申请人： Ching-Te Chuang , Keunwoo Kim , Jente Benedict Kuang , Kevin John Nowka
发明人： Ching-Te Chuang , Keunwoo Kim , Jente Benedict Kuang , Kevin John Nowka
IPC分类号： H03K19/20 , H03K19/096
CPC分类号： H03K19/0963
摘要： A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation.
摘要翻译：动态逻辑门具有用于在时钟的预充电阶段对动态节点充电的装置。逻辑树在时钟的评估阶段使用设备来评估动态节点。动态节点具有保持器电路，其包括反相器，其输入耦合到动态节点，其输出耦合到双栅极PFET器件的背栅极。双栅极PFET的源极耦合到电源，并且其漏极耦合到形成半锁存器的动态节点。双栅极PFET的前栅极耦合到具有模式输入和逻辑输入的逻辑电路，逻辑输入耦合回到感测动态节点的状态的节点。模式输入可能是缓慢的模式，以保持动态节点状态或时钟延迟，在评估后打开强守护者。

10. 发明授权

US07265589B2 Independent gate control logic circuitry 失效
标题翻译：独立门控逻辑电路
公开(公告)号：US07265589B2
公开(公告)日：2007-09-04
申请号：US11168717
申请日：2005-06-28
申请人： Ching-Te Chuang , Keunwoo Kim , Jente Benedict Kuang , Kevin John Nowka
发明人： Ching-Te Chuang , Keunwoo Kim , Jente Benedict Kuang , Kevin John Nowka
IPC分类号： H03K19/20 , H03K19/094 , H03K19/00 , H03K19/096
CPC分类号： H03K19/0963
摘要： A dynamic logic gate has a dynamic node pre-charged in response to a pre-charge phase of a clock signal and a logic tree with a plurality of logic inputs for evaluating the dynamic node during an evaluate phase of the clock signal in response to a Boolean combination of the logic inputs. The logic tree has a stacked configuration with at least one multi-gate FEAT device for coupling an intermediate node of the logic tree to the dynamic node in response to a first logic input of the plurality of logic inputs or in response to the pre-charge phase of the clock signal. The multi-gate FEAT device has one gate coupled to the first logic input and a second gate coupled to a complement of the clock signal used to pre-charge the dynamic node.
摘要翻译：动态逻辑门具有响应于时钟信号的预充电阶段和具有多个逻辑输入的逻辑树预充电的动态节点，用于在响应于时钟信号的时钟信号的估计阶段期间评估动态节点逻辑输入的布尔组合。逻辑树具有堆叠配置，其具有至少一个多栅极FEAT装置，用于响应于多个逻辑输入的第一逻辑输入或响应于预充电而将逻辑树的中间节点耦合到动态节点时钟信号的相位。多栅极FEAT器件具有耦合到第一逻辑输入的一个栅极和耦合到用于对动态节点预充电的时钟信号的补码的第二栅极。

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