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1. 发明申请

US20080079158A1 METAL FILL REGION OF A SEMICONDUCTOR CHIP 失效
标题翻译：金属填充区半导体芯片
公开(公告)号：US20080079158A1
公开(公告)日：2008-04-03
申请号：US11538118
申请日：2006-10-03
申请人： Steven J. Baumgartner , Chun-Tao Li , Salvatore N. Storino , Mankit Wong
发明人： Steven J. Baumgartner , Chun-Tao Li , Salvatore N. Storino , Mankit Wong
IPC分类号： H01L23/52
CPC分类号： H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a metal fill region of a semiconductor chip including a plurality of layer sets of the semiconductor chip, each set including a first metal fill layer, a second metal fill layer, and an insulation layer included disposed in planes parallel to each other, a plurality of metal fill pieces disposed in each of the metal fill layers, a metal fill piece axis of each of the pieces, wherein each of the axes perpendicularly intersects the planes of said metal fill layers and the insulation layer from any point of reference, and a metal fill pattern configured to position the pieces so that the axis of each piece in the first metal fill layer is linearly displaced of the axis of each piece in the second metal fill layer in at least one direction orthogonal to each of the metal fill axes.
摘要翻译：公开了一种半导体芯片的金属填充区域，其包括半导体芯片的多个层组，每组包括设置在彼此平行的平面中的第一金属填充层，第二金属填充层和绝缘层，设置在每个金属填充层中的多个金属填充片，每个片的金属填充片轴线，其中每个轴与任何参考点垂直地相交于所述金属填充层的平面和绝缘层，以及金属填充图案，被配置为定位所述片，使得所述第一金属填充层中的每个片的轴线在与所述金属填充轴中的每一个垂直的至少一个方向上在所述第二金属填充层中的每个片的轴线线性位移。

2. 发明授权

US07489039B2 Metal fill region of a semiconductor chip 失效
标题翻译：半导体芯片的金属填充区域
公开(公告)号：US07489039B2
公开(公告)日：2009-02-10
申请号：US11538118
申请日：2006-10-03
申请人： Steven J. Baumgartner , Chun-Tao Li , Salvatore N. Storino , Mankit Wong
发明人： Steven J. Baumgartner , Chun-Tao Li , Salvatore N. Storino , Mankit Wong
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a metal fill region of a semiconductor chip including a plurality of layer sets of the semiconductor chip, each set including a first metal fill layer, a second metal fill layer, and an insulation layer included disposed in planes parallel to each other, a plurality of metal fill pieces disposed in each of the metal fill layers, a metal fill piece axis of each of the pieces, wherein each of the axes perpendicularly intersects the planes of said metal fill layers and the insulation layer from any point of reference, and a metal fill pattern configured to position the pieces so that the axis of each piece in the first metal fill layer is linearly displaced of the axis of each piece in the second metal fill layer in at least one direction orthogonal to each of the metal fill axes.
摘要翻译：公开了一种半导体芯片的金属填充区域，其包括半导体芯片的多个层组，每组包括设置在彼此平行的平面中的第一金属填充层，第二金属填充层和绝缘层，设置在每个金属填充层中的多个金属填充片，每个片的金属填充片轴线，其中每个轴与任何参考点垂直地相交于所述金属填充层的平面和绝缘层，以及金属填充图案，被配置为定位所述片，使得所述第一金属填充层中的每个片的轴线在与所述金属填充轴中的每一个垂直的至少一个方向上在所述第二金属填充层中的每个片的轴线线性位移。

3. 发明申请

US20080082300A1 Design Structure for a Metal Fill Region of a Semiconductor Chip 审中-公开
标题翻译：半导体芯片的金属填充区域的设计结构
公开(公告)号：US20080082300A1
公开(公告)日：2008-04-03
申请号：US11868558
申请日：2007-10-08
申请人： Steven J. Baumgartner , Chun-Tao Li , Salvatore N. Storino , Mankit Wong
发明人： Steven J. Baumgartner , Chun-Tao Li , Salvatore N. Storino , Mankit Wong
IPC分类号： G06F17/50
CPC分类号： H01L23/5222 , G06F17/5068 , G06F2217/12 , H01L2924/0002 , Y02P90/265 , H01L2924/00
摘要： A design structure embodied in a machine readable medium used in a design process includes a metal fill region of a semiconductor chip including a plurality of layer sets of the semiconductor chip, each set including a first metal fill layer, a second metal fill layer, and an insulation layer included disposed in planes parallel to each other, a plurality of metal fill pieces disposed in each of the metal fill layers, a metal fill piece axis of each of the pieces, wherein each of the axes perpendicularly intersects the planes of said metal fill layers and the insulation layer from any point of reference, and a metal fill pattern configured to position the pieces so that the axis of each piece in the first metal fill layer is linearly displaced of the axis of each piece in the second metal fill layer in at least one direction orthogonal to each of the metal fill axes.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括半导体芯片的金属填充区域，该半导体芯片包括半导体芯片的多个层组，每组包括第一金属填充层，第二金属填充层和包括设置在彼此平行的平面中的绝缘层，设置在每个金属填充层中的多个金属填充片，每个片的金属填充片轴线，其中每个轴垂直于所述金属的平面相交填充层和绝缘层，以及金属填充图案，其被配置为定位所述片，使得所述第一金属填充层中的每个片的轴线在所述第二金属填充层中的每个片的轴线线性移位在与每个金属填充轴正交的至少一个方向上。

4. 发明申请

US20080072181A1 Ratioed Feedback Body Voltage Bias Generator 有权
标题翻译：比例反馈体电压偏置发生器
公开(公告)号：US20080072181A1
公开(公告)日：2008-03-20
申请号：US11866110
申请日：2007-10-02
申请人： Steven J. Baumgartner , Patrick L. Rosno , Dana M. Woeste
发明人： Steven J. Baumgartner , Patrick L. Rosno , Dana M. Woeste
IPC分类号： G06F17/50
CPC分类号： G05F3/205 , G05F3/262 , G06F17/5045 , G06F17/5063
摘要： A design structure embodied in a machine readable medium used in a design process includes a current mirror circuit that includes a reference current source that generates a reference current, a reference transistor, a mirror transistor and a ratioed body bias feedback unit. The reference transistor has a first node that is coupled to the output of the reference current source, a gate that is coupled to the first node and a second node coupled to a common voltage. The mirror transistor has a gate coupled to the first node. The ratioed body bias feedback unit generates a body bias voltage coupled to the body of the reference transistor and the body of the mirror transistor. The ratioed body bias feedback unit is configured to adjust the body bias voltage in relationship to the common voltage so that the reference transistor and the mirror transistor each have a threshold voltage within a predefined range.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括电流镜电路，其包括产生参考电流的参考电流源，参考晶体管，反射镜晶体管和比例体偏置反馈单元。参考晶体管具有耦合到参考电流源的输出的第一节点，耦合到第一节点的栅极和耦合到公共电压的第二节点。镜晶体管具有耦合到第一节点的栅极。比例体偏置反馈单元产生耦合到参考晶体管的主体和反射镜晶体管的主体的体偏置电压。比率体偏置反馈单元被配置为相对于公共电压调节体偏置电压，使得参考晶体管和反射镜晶体管各自具有在预定范围内的阈值电压。

5. 发明授权

US07940878B2 Unlock mode in source synchronous receivers 失效
标题翻译：源同步接收器中的解锁模式
公开(公告)号：US07940878B2
公开(公告)日：2011-05-10
申请号：US11678256
申请日：2007-02-23
申请人： Steven J. Baumgartner , Timothy C. Buchholtz , Andrew D. Davies , Thomas W. Liang , Andrew B. Maki , Thomas Pham , Dana M. Woeste , Daniel G. Young
发明人： Steven J. Baumgartner , Timothy C. Buchholtz , Andrew D. Davies , Thomas W. Liang , Andrew B. Maki , Thomas Pham , Dana M. Woeste , Daniel G. Young
IPC分类号： H03D3/24 , H04L7/00
CPC分类号： H03L7/0812 , H04L7/0008
摘要： A phase locked loop generates an output corresponding to a source synchronous input and an input link clock signal. A phase locking feedback system receives the input and an input link clock signal and detects phase deviations between the output and the input. The phase locking feedback system also adjusts an adjusted clock signal based on the phase deviations thereby causing the phase locking feedback system to generate the output so that the output has a steady phase relationship with the input. A first mechanism causes the phase locking feedback system not to track phase deviations between the output and the input upon occurrence of a first predefined event, thereby maintaining the adjusted clock signal at a current state.
摘要翻译：锁相环产生对应于源同步输入和输入链路时钟信号的输出。相位锁定反馈系统接收输入和输入链路时钟信号，并检测输出和输入之间的相位偏差。相位锁定反馈系统还基于相位偏差来调整调整的时钟信号，从而使相位锁定反馈系统产生输出，使得输出与输入具有稳定的相位关系。第一机制使得相位锁定反馈系统在出现第一预定义事件时不跟踪输出和输入之间的相位偏差，从而将经调整的时钟信号保持在当前状态。

6. 发明授权

US07652523B2 Ratioed feedback body voltage bias generator 失效
标题翻译：比例反馈体电压偏置发生器
公开(公告)号：US07652523B2
公开(公告)日：2010-01-26
申请号：US12112356
申请日：2008-04-30
申请人： Steven J. Baumgartner , Patrick L. Rosno , Dana M. Woeste
发明人： Steven J. Baumgartner , Patrick L. Rosno , Dana M. Woeste
IPC分类号： G05F1/575
CPC分类号： G05F3/262 , G05F3/205
摘要： A current mirror circuit includes a reference current source that generates a reference current, a reference transistor, a mirror transistor and a ratioed body bias feedback unit. The reference transistor has a first node that is coupled to the output of the reference current source, a gate that is coupled to the first node and a second node coupled to a common voltage. The mirror transistor has a gate coupled to the first node. The ratioed body bias feedback unit generates a body bias voltage coupled to the body of the reference transistor and the body of the mirror transistor. The ratioed body bias feedback unit is configured to adjust the body bias voltage in relationship to the common voltage so that the reference transistor and the mirror transistor each have a threshold voltage within a predefined range.
摘要翻译：电流镜电路包括产生参考电流的参考电流源，参考晶体管，镜像晶体管和比例体偏置反馈单元。参考晶体管具有耦合到参考电流源的输出的第一节点，耦合到第一节点的栅极和耦合到公共电压的第二节点。镜晶体管具有耦合到第一节点的栅极。比例体偏置反馈单元产生耦合到参考晶体管的主体和反射镜晶体管的主体的体偏置电压。比率体偏置反馈单元被配置为相对于公共电压调节体偏置电压，使得参考晶体管和反射镜晶体管各自具有在预定范围内的阈值电压。

7. 发明授权

US07474144B2 Ratioed feedback body voltage bias generator 有权
标题翻译：比例反馈体电压偏置发生器
公开(公告)号：US07474144B2
公开(公告)日：2009-01-06
申请号：US11533408
申请日：2006-09-20
申请人： Steven J. Baumgartner , Patrick L. Rosno , Dana M. Woeste
发明人： Steven J. Baumgartner , Patrick L. Rosno , Dana M. Woeste
IPC分类号： G05F1/46
CPC分类号： G05F3/262 , G05F3/205
摘要： A current mirror circuit includes a reference current source that generates a reference current, a reference transistor, a mirror transistor and a ratioed body bias feedback unit. The reference transistor has a first node that is coupled to the output of the reference current source, a gate that is coupled to the first node and a second node coupled to a common voltage. The mirror transistor has a gate coupled to the first node. The ratioed body bias feedback unit generates a body bias voltage coupled to the body of the reference transistor and the body of the mirror transistor. The ratioed body bias feedback unit is configured to adjust the body bias voltage in relationship to the common voltage so that the reference transistor and the mirror transistor each have a threshold voltage within a predefined range.
摘要翻译：电流镜电路包括产生参考电流的参考电流源，参考晶体管，镜像晶体管和比例体偏置反馈单元。参考晶体管具有耦合到参考电流源的输出的第一节点，耦合到第一节点的栅极和耦合到公共电压的第二节点。镜晶体管具有耦合到第一节点的栅极。比例体偏置反馈单元产生耦合到参考晶体管的主体和反射镜晶体管的主体的体偏置电压。比率体偏置反馈单元被配置为相对于公共电压调节体偏置电压，使得参考晶体管和反射镜晶体管各自具有在预定范围内的阈值电压。

8. 发明申请

US20080191793A1 Ratioed Feedback Body Voltage Bias Generator 失效
标题翻译：比例反馈体电压偏置发生器
公开(公告)号：US20080191793A1
公开(公告)日：2008-08-14
申请号：US12112356
申请日：2008-04-30
申请人： Steven J. Baumgartner , Patrick L. Rosno , Dana M. Woeste
发明人： Steven J. Baumgartner , Patrick L. Rosno , Dana M. Woeste
IPC分类号： G05F1/10
CPC分类号： G05F3/262 , G05F3/205
摘要： A current mirror circuit includes a reference current source that generates a reference current, a reference transistor, a mirror transistor and a ratioed body bias feedback unit. The reference transistor has a first node that is coupled to the output of the reference current source, a gate that is coupled to the first node and a second node coupled to a common voltage. The mirror transistor has a gate coupled to the first node. The ratioed body bias feedback unit generates a body bias voltage coupled to the body of the reference transistor and the body of the mirror transistor. The ratioed body bias feedback unit is configured to adjust the body bias voltage in relationship to the common voltage so that the reference transistor and the mirror transistor each have a threshold voltage within a predefined range.
摘要翻译：电流镜电路包括产生参考电流的参考电流源，参考晶体管，镜像晶体管和比例体偏置反馈单元。参考晶体管具有耦合到参考电流源的输出的第一节点，耦合到第一节点的栅极和耦合到公共电压的第二节点。镜晶体管具有耦合到第一节点的栅极。比例体偏置反馈单元产生耦合到参考晶体管的主体和反射镜晶体管的主体的体偏置电压。比率体偏置反馈单元被配置为相对于公共电压调节体偏置电压，使得参考晶体管和反射镜晶体管各自具有在预定范围内的阈值电压。

9. 发明授权

US08898504B2 Parallel data communications mechanism having reduced power continuously calibrated lines 有权
标题翻译：并行数据通信机制具有降低功率的连续校准线路
公开(公告)号：US08898504B2
公开(公告)日：2014-11-25
申请号：US13325478
申请日：2011-12-14
申请人： Steven J. Baumgartner , Frank D. Ferraiolo , Susan M. Eickhoff , Michael B. Spear
发明人： Steven J. Baumgartner , Frank D. Ferraiolo , Susan M. Eickhoff , Michael B. Spear
IPC分类号： G06F11/00
CPC分类号： H04L1/22
摘要： A communications link includes multiple continuously calibrated parallel lines, wherein one or more lines are at least partially powered down while being continuously calibrated to reduce power consumption. In one aspect, at least N+1 lines (where N is the logical bus width) are periodically recalibrated, and at least one redundant line is powered down between calibrations. The redundant line could be either a true spare available for use as a replacement, or an extra line which carries functional data while other lines are being calibrated in turn. In another aspect, the logical bus width is variable, but does not exceed NMAX. When N
摘要翻译：通信链路包括多个连续校准的并行线路，其中一个或多个线路被至少部分断电，同时连续校准以减少功率消耗。在一个方面，至少N + 1行（其中N是逻辑总线宽度）被周期性地重新校准，并且至少一个冗余线路在校准之间断电。冗余线路可以是可用作替代的真实备用，也可以是携带功能数据的额外线路，而其他线路依次校准。另一方面，逻辑总线宽度是可变的，但不超过NMAX。当N

10. 发明申请

US20130159761A1 Parallel Data Communications Mechanism Having Reduced Power Continuously Calibrated Lines 有权
标题翻译：并行数据通信机制具有连续校准线路功耗
公开(公告)号：US20130159761A1
公开(公告)日：2013-06-20
申请号：US13325478
申请日：2011-12-14
申请人： Steven J. Baumgartner , Frank D. Ferraiolo , Susan M. Eickhoff , Michael B. Spear
发明人： Steven J. Baumgartner , Frank D. Ferraiolo , Susan M. Eickhoff , Michael B. Spear
IPC分类号： G06F13/36 , G06F11/20
CPC分类号： H04L1/22
摘要： A communications link includes multiple continuously calibrated parallel lines, wherein one or more lines are at least partially powered down while being continuously calibrated to reduce power consumption. In one aspect, at least N+1 lines (where N is the logical bus width) are periodically recalibrated, and at least one redundant line is powered down between calibrations. The redundant line could be either a true spare available for use as a replacement, or an extra line which carries functional data while other lines are being calibrated in turn. In another aspect, the logical bus width is variable, but does not exceed NMAX. When N
摘要翻译：通信链路包括多个连续校准的并行线路，其中一个或多个线路被至少部分断电，同时连续校准以减少功率消耗。在一个方面，至少N + 1行（其中N是逻辑总线宽度）被周期性地重新校准，并且至少一个冗余线路在校准之间断电。冗余线路可以是可用作替代的真实备用，也可以是携带功能数据的额外线路，而其他线路依次被校准。另一方面，逻辑总线宽度是可变的，但不超过NMAX。当N

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