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1. 发明申请

US20060240331A1 Modifying merged sub-resolution assist features of a photolithographic mask 有权
标题翻译：修改光刻掩模的合并分解辅助功能
公开(公告)号：US20060240331A1
公开(公告)日：2006-10-26
申请号：US11114582
申请日：2005-04-26
申请人： Sean O'Brien , Scott Jessen
发明人： Sean O'Brien , Scott Jessen
IPC分类号： G03F1/00 , G06F17/50
CPC分类号： G03F1/36
摘要： Modifying merged sub-resolution assist features includes receiving a mask pattern comprising the merged sub-resolution assist features, where a segmenting sub-resolution assist feature intersects a segmented sub-resolution assist feature at an intersection. Each sub-resolution assist feature is represented by an axis of the sub-resolution assist feature. The length of at least one axis is established, and an axis is modified in accordance with the length. Each axis is converted to a sub-resolution assist feature to yield the modified merged sub-resolution assist features.
摘要翻译：修改合并的子分辨率辅助特征包括接收包括合并的子分辨率辅助特征的掩模图案，其中分割的子分辨率辅助特征与交叉点处的分段的子分辨率辅助特征相交。每个子分辨率辅助特征由子分辨率辅助特征的轴表示。确定至少一个轴的长度，并根据长度修改轴。每个轴被转换为子分辨率辅助功能以产生修改的合并子分辨率辅助特征。

2. 发明申请

US20060110901A1 Minimizing resist poisoning in the manufacture of semiconductor devices 有权
标题翻译：最大限度地减少半导体器件制造中的抗蚀剂中毒
公开(公告)号：US20060110901A1
公开(公告)日：2006-05-25
申请号：US10993791
申请日：2004-11-19
申请人： Zhijian Lu , Thomas Wolf , Scott Jessen
发明人： Zhijian Lu , Thomas Wolf , Scott Jessen
IPC分类号： H01L21/44
CPC分类号： H01L21/76808 , H01L21/31144
摘要： The present invention provides a method for manufacturing an interconnect and a method for manufacturing an integrated circuit including the interconnect. The method of manufacturing an interconnect, among other steps, includes forming a via (160) in a substrate (130) and then forming a base getter material (210) in the via (160). The method further includes forming a photoresist layer (410) over the base getter material (210), the photoresist layer (410) having an opening (420) therein positioned over the via (160), and etching a trench (510) into the substrate (130) using the opening (420) in the photoresist layer (410).
摘要翻译：本发明提供了一种用于制造互连的方法和用于制造包括该互连的集成电路的方法。制造互连的方法以及其它步骤包括在衬底（130）中形成通孔（160），然后在通路（160）中形成基底吸气材料（210）。该方法还包括在基底吸气材料（210）上形成光致抗蚀剂层（410），光致抗蚀剂层（410）在其上具有位于通孔（160）上方的开口（420），并且将沟槽（510）蚀刻到使用光致抗蚀剂层（410）中的开口（420）的衬底（130）。

3. 发明授权

US06893800B2 Substrate topography compensation at mask design: 3D OPC topography anchored 有权
标题翻译：掩模设计中的基底地形补偿：3D OPC地形锚定
公开(公告)号：US06893800B2
公开(公告)日：2005-05-17
申请号：US10254083
申请日：2002-09-24
申请人： Scott Jessen , John Martin McIntosh , Scott M. Nagel
发明人： Scott Jessen , John Martin McIntosh , Scott M. Nagel
IPC分类号： G03F1/00 , G03F1/36 , G03F7/00 , G03F7/207 , H01L21/027 , G06F19/00
CPC分类号： G03F1/36 , G03F1/70 , G03F7/0035 , G03F7/70441
摘要： A semiconductor manufacturing method analyzes topography variations in three dimensions for each photolithographic level and determines critical dimension (CD) bias compensation as inputs to mask layout creation. Accurate predictions of topography variation for a specific mask design are made at the die level using known pattern density and CMP planarization length characteristics for a specific pattern. Exhaustive characterization of the photoresist response to de-focus and mask bias is determined by artificially expanding loss of CD through focus. Mask compensation to an expanded range of focus over all lines and spaces is maintained within the specification. 3D mask density data is obtained to determine the height component at each pixel location in the die. The resulting 3D OPC model is then utilized for mask creation.
摘要翻译：半导体制造方法分析每个光刻级别的三维拓扑变化，并确定临界尺寸（CD）偏置补偿作为掩模布局创建的输入。使用已知图案密度和特定图案的CMP平坦化长度特征，在管芯级别进行特定掩模设计的地形变化的准确预测。光致抗蚀剂对去焦和掩模偏差的反应的详尽表征是通过人工扩大CD通过焦点的损失来确定的。在规格范围内保持对所有线和空间的焦点扩大范围的掩模补偿。获得3D掩模密度数据以确定管芯中每个像素位置的高度分量。然后将所得的3D OPC模型用于掩模创建。

4. 发明授权

US06798043B2 Structure and method for isolating porous low-k dielectric films 失效
标题翻译：隔离多孔低k电介质膜的结构和方法
公开(公告)号：US06798043B2
公开(公告)日：2004-09-28
申请号：US10038352
申请日：2002-01-02
申请人： Kurt G. Steiner , Susan Vitkavage , Steve Lytle , Gerald Gibson , Scott Jessen
发明人： Kurt G. Steiner , Susan Vitkavage , Steve Lytle , Gerald Gibson , Scott Jessen
IPC分类号： H01L2358
CPC分类号： H01L21/76832 , H01L21/02126 , H01L21/02203 , H01L21/02304 , H01L21/02362 , H01L21/312 , H01L21/3146 , H01L21/31633 , H01L21/31695 , H01L21/3185 , H01L21/76801 , H01L21/76808 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A film structure includes low-k dielectric films and N—H base source films such as barrier layer films, etch-stop films and hardmask films. Interposed between the low-k dielectric film and adjacent N—H base film is a TEOS oxide film which suppresses the diffusion of amines or other N—H bases from the N—H base source film to the low-k dielectric film. The film structure may be patterned using DUV lithography and a chemically amplified photoresist since there are no base groups present in the low-k dielectric films to neutralize the acid catalysts in the chemically amplified photoresist.
摘要翻译：膜结构包括低k电介质膜和N-H基源膜，例如阻挡层膜，蚀刻停止膜和硬掩模膜。在低k电介质膜和相邻的N-H基膜之间插入TEOS氧化物膜，其抑制胺或其它N-H碱从N-H基底膜向低k电介质膜的扩散。可以使用DUV光刻和化学放大的光致抗蚀剂来对膜结构进行图案化，因为在低k电介质膜中不存在碱基以中和化学放大光致抗蚀剂中的酸催化剂。

5. 发明授权

US06708574B2 Abnormal photoresist line/space profile detection through signal processing of metrology waveform 有权
标题翻译：通过信号处理计量波形的异常光刻胶线/空间轮廓检测
公开(公告)号：US06708574B2
公开(公告)日：2004-03-23
申请号：US10156242
申请日：2002-05-24
申请人： Erik Cho Houge , Scott Jessen , John Martin McIntosh , Catherine Vartuli , Fred Anthony Stevie
发明人： Erik Cho Houge , Scott Jessen , John Martin McIntosh , Catherine Vartuli , Fred Anthony Stevie
IPC分类号： G01M1900
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor manufacturing automation method for analyzing a patterned feature formed on a semiconductor layer is disclosed. At least one patterned feature is scanned to generate an amplitude modulated waveform signal of the line and neighboring space characteristics. Signal processing is automatically performed on this waveform by an in-line computational source to extract known patterned features based on the profile of the amplitude modulated waveform signal. The extracted waveform segments are subjected to known geometric shapes to determine if the waveform indicates a normal or abnormal patterned feature on a semiconductor layer.
摘要翻译：公开了一种用于分析形成在半导体层上的图案特征的半导体制造自动化方法。扫描至少一个图案化特征以产生线和相邻空间特征的幅度调制波形信号。通过在线计算源自动对该波形执行信号处理，以基于幅度调制波形信号的轮廓来提取已知的图案特征。提取的波形段经历已知的几何形状以确定波形是否指示半导体层上的正常或异常图案化特征。

6. 发明申请

US20070035031A1 Sub-resolution assist feature to improve symmetry for contact hole lithography 有权
标题翻译：辅助分辨率辅助功能可改善接触孔光刻的对称性
公开(公告)号：US20070035031A1
公开(公告)日：2007-02-15
申请号：US11202205
申请日：2005-08-12
申请人： Scott Jessen , Mark Terry , Robert Soper
发明人： Scott Jessen , Mark Terry , Robert Soper
IPC分类号： H01L29/40 , H01L21/66 , G03F1/00
CPC分类号： H01L22/12 , G03F1/36
摘要： A method of making a mask design having optical proximity correction features is provided. The method can include obtaining a target pattern comprising a plurality of target pattern features corresponding to a plurality of features to be imaged on a substrate. The method can also comprise generating a mask design comprising mask features corresponding to the plurality of features to be imaged on the substrate and controlling the aspect ratio of at least one of the features of the plurality of features to be imaged on the substrate by positioning a sub-resolution assist feature proximate to the corresponding mask feature.
摘要翻译：提供了具有光学邻近校正特征的掩模设计的方法。该方法可以包括获得包括对应于要在基底上成像的多个特征的多个目标图案特征的目标图案。该方法还可以包括生成包括掩模特征的掩模设计，掩模特征对应于待成像在基底上的多个特征，并且通过将基底上要成像的多个特征的特征中的至少一个特征控制在基底上，子分辨率辅助功能靠近相应的掩码特征。

7. 发明授权

US06258610B1 Method analyzing a semiconductor surface using line width metrology with auto-correlation operation 有权
标题翻译：使用自相关运算的线宽度量法分析半导体表面的方法
公开(公告)号：US06258610B1
公开(公告)日：2001-07-10
申请号：US09347313
申请日：1999-07-02
申请人： James W. Blatchford , Scott Jessen , Brittin C. Kane , Nace Layadi , John M. McIntosh , Simon J. Molloy
发明人： James W. Blatchford , Scott Jessen , Brittin C. Kane , Nace Layadi , John M. McIntosh , Simon J. Molloy
IPC分类号： G01R3126
CPC分类号： H01L22/12
摘要： A method for analyzing a semiconductor surface having patterned features on the surface is disclosed. At least one patterned feature is scanned to produce a scanned waveform signal having signal segments corresponding to characteristic surface portions of the patterned feature. The signal segments are processed using an auto-correlation function to produce an auto-correlation signal for each characteristic surface portion of the patterned feature. A reference signal having signal segments corresponding to characteristic surface portions of a known patterned feature is provided and each segment of the auto-correlation signal is compared to the respective signal segments of the reference signal.
摘要翻译：公开了一种用于分析表面上具有图案特征的半导体表面的方法。扫描至少一个图案特征以产生具有对应于图案化特征的特征表面部分的信号段的扫描波形信号。使用自相关函数处理信号段，以对图案化特征的每个特征表面部分产生自相关信号。提供具有对应于已知图案特征的特征表面部分的信号段的参考信号，并将自相关信号的每个段与参考信号的相应信号段进行比较。

8. 发明授权

US06225639B1 Method of monitoring a patterned transfer process using line width metrology 有权
标题翻译：使用线宽度量法监测图案转移过程的方法
公开(公告)号：US06225639B1
公开(公告)日：2001-05-01
申请号：US09384459
申请日：1999-08-27
申请人： Thomas E. Adams , Thomas S. Frederick , Scott Jessen , John M. McIntosh , Catherine Vartuli
发明人： Thomas E. Adams , Thomas S. Frederick , Scott Jessen , John M. McIntosh , Catherine Vartuli
IPC分类号： G01N2186
CPC分类号： H01L22/20 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： A patterned transfer process in the manufacture of a semiconductor device is monitored. Patterned features formed on a semiconductor layer to be etched are scanned for generating a first amplitude modulated waveform intensity signal. The first amplitude modulated waveform intensity signal is sampled to extract a first measurement population of critical dimension measurements. The patterned features are etched and then scanned for generating a second amplitude modulated waveform intensity signal. The second amplitude modulated waveform intensity signal is then sampled to extract a second measurement population of critical dimension measurements, which are then cross-correlated to obtain correlation values of the etching process.
摘要翻译：监视半导体器件制造中的图案转印工艺。扫描形成在要蚀刻的半导体层上的图形特征，以产生第一幅度调制波形强度信号。对第一幅度调制波形强度信号进行采样，以提取关键尺寸测量的第一测量群。蚀刻图案特征，然后扫描以产生第二幅度调制波形强度信号。然后对第二幅度调制波形强度信号进行采样，以提取关键尺寸测量的第二测量群，然后交叉相关，以获得蚀刻过程的相关值。

9. 发明申请

US20080020580A1 Minimizing resist poisoning in the manufacture of semiconductor devices 有权
公开(公告)号：US20080020580A1
公开(公告)日：2008-01-24
申请号：US11828217
申请日：2007-07-25
申请人： Zhijian Lu , Thomas Wolf , Scott Jessen
发明人： Zhijian Lu , Thomas Wolf , Scott Jessen
IPC分类号： H01L21/04
CPC分类号： H01L21/76808 , H01L21/31144
摘要： The present invention provides a method for manufacturing an interconnect and a method for manufacturing an integrated circuit including the interconnect. The method of manufacturing an interconnect, among other steps, includes forming a via (160) in a substrate (130) and then forming a base getter material (210) in the via (160). The method further includes forming a photoresist layer (410) over the base getter material (210), the photoresist layer (410) having an opening (420) therein positioned over the via (160), and etching a trench (510) into the substrate (130) using the opening (420) in the photoresist layer (410).

10. 发明申请

US20070028200A1 Method for performing place-and-route of contacts and vias in technologies with forbidden pitch requirements 有权
标题翻译：在具有禁止音高要求的技术中进行接触和通孔的放置和路径的方法
公开(公告)号：US20070028200A1
公开(公告)日：2007-02-01
申请号：US11191078
申请日：2005-07-28
申请人： James Blatchford , Scott Jessen
发明人： James Blatchford , Scott Jessen
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5068 , G03F1/36
摘要： Provide is a method of making a mask layout, an integrated circuit device made by a method, a computer readable medium, and a mask for forming contact holes. The method can comprise patterning a first feature along a first axis, determining a first set of areas adjacent to the first feature, wherein each of the areas in the first set of areas is within a first angle away from the first axis, and wherein each of the areas in the first set of areas is within a first distance away from the first feature, and patterning a second feature in at least one of the first set of areas so as to form a mask layout, wherein each of the first feature and the second feature are one of a virtual feature and a real feature.
摘要翻译：提供是制作掩模布局的方法，由方法制成的集成电路器件，计算机可读介质和用于形成接触孔的掩模。该方法可以包括沿着第一轴图案化第一特征，确定与第一特征相邻的第一组区域，其中第一组区域中的每个区域处于远离第一轴线的第一角度内，并且其中每个区域所述第一组区域中的区域在距离所述第一特征的第一距离内，并且在所述第一组区域中的至少一个中构图第二特征以形成掩模布局，其中所述第一特征和第二个特征是虚拟特征和真实特征之一。

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