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1. 发明申请

US20060251070A1 Methods and apparatus for facilitating coherency management in distributed multi-processor system 有权
标题翻译：用于促进分布式多处理器系统中的一致性管理的方法和装置
公开(公告)号：US20060251070A1
公开(公告)日：2006-11-09
申请号：US11098621
申请日：2005-04-04
申请人： Takeshi Yamazaki , Jeffrey Brown , Scott Clark , Charles Johns
发明人： Takeshi Yamazaki , Jeffrey Brown , Scott Clark , Charles Johns
IPC分类号： H04L12/56
CPC分类号： G06F12/0831 , G06F12/0813 , G06F2212/251 , G06F2212/253
摘要： Methods and apparatus provide for sending a data command from a first of a plurality of devices to a first address concentrator within a first of a plurality of processing systems; selecting one of the other processing systems, the selected processing system having data addressed by the data command stored therein; sending the data command to a first address concentrator of the selected processing system; and broadcasting the data command from the first address concentrator of the selected processing system to a second address concentrator in each of the processing systems.
摘要翻译：方法和装置提供从多个设备中的第一设备向多个处理系统中的第一个内的第一地址集中器发送数据命令; 选择其他处理系统之一，所选择的处理系统具有由其中存储的数据命令寻址的数据; 将所述数据命令发送到所选择的处理系统的第一地址集中器; 以及从所选择的处理系统的第一地址集中器将数据命令广播到每个处理系统中的第二地址集中器。

2. 发明申请

US20060206657A1 Single port/multiple ring implementation of a hybrid crossbar partially non-blocking data switch 审中-公开
标题翻译：单端口/多环实现混合交叉开关部分非阻塞数据交换
公开(公告)号：US20060206657A1
公开(公告)日：2006-09-14
申请号：US11077330
申请日：2005-03-10
申请人： Scott Clark , Charles Johns , David Krolak , Takeshi Yamazaki , Jeffrey Brown
发明人： Scott Clark , Charles Johns , David Krolak , Takeshi Yamazaki , Jeffrey Brown
IPC分类号： G06F13/00
CPC分类号： G06F13/362 , G06F1/3237 , G06F1/3253 , Y02D10/128 , Y02D10/151
摘要： A ring-based crossbar data switch, a method and a computer program are provided for the transfer of data between multiple bus units in a memory system. Each bus unit is connected to a corresponding data ramp. Each data ramp is only directly connected to the adjacent data ramps. This forms at least one data ring that enables the transfer of data from each bus unit to any other bus unit in the memory system. A central arbiter manages the transfer of data between the data ramps and the transfer of data between the data ramp and its corresponding bus unit. A preferred embodiment contains four data rings, wherein two data rings transfer data clockwise and two data rings transfer data counter-clockwise.
摘要翻译：提供了一种基于环的交叉开关数据开关，方法和计算机程序，用于在存储器系统中的多个总线单元之间传送数据。每个总线单元连接到相应的数据斜坡。每个数据斜坡仅直接连接到相邻的数据斜坡。这形成至少一个数据环，其使得能够将数据从每个总线单元传送到存储器系统中的任何其它总线单元。中央仲裁器管理数据斜坡之间的数据传输和数据斜坡与其对应的总线单元之间的数据传输。优选实施例包含四个数据环，其中两个数据环顺时针传送数据，两个数据环逆时针传送数据。

3. 发明申请

US20050125581A1 Method of resource arbitration 失效
标题翻译：资源仲裁方法
公开(公告)号：US20050125581A1
公开(公告)日：2005-06-09
申请号：US10730952
申请日：2003-12-09
申请人： Jeffrey Brown , Scott Clark , Charles Johns , Takeshi Yamazaki
发明人： Jeffrey Brown , Scott Clark , Charles Johns , Takeshi Yamazaki
IPC分类号： G06F13/14 , G06F13/362
CPC分类号： G06F13/3625
摘要： An improved method and apparatus for resource arbitration. Four priority classes, managed high (MH), managed low (ML), opportunistic high (OH) and opportunistic low (OL), are defined. A priority class is assigned to each resource access request. An access request concentrator (ARC) is created for each resource, through which the resource is accessed. An access request is chosen at each ARC using the priority order MH, ML, OH, and OL, in decreasing order of priority. If OH priority class resource access requests are locked out, the priority order is temporarily changed to OH, OL, MH, and ML, in decreasing order of priority. If OL priority class resource access requests are locked out, the priority order is temporarily changed to MH, OL, OH, and ML, in decreasing order of priority.
摘要翻译：一种改进的资源仲裁方法和装置。定义了四个优先级，管理高（MH），管理低（ML），机会高（OH）和机会主义低（OL）。优先级分配给每个资源访问请求。为每个资源创建访问请求集中器（ARC），通过该资源访问资源。在优先级顺序为MH，ML，OH和OL的每个ARC中选择访问请求。如果OH优先级资源访问请求被锁定，优先级顺序将按照优先级的降序暂时更改为OH，OL，MH和ML。如果OL优先级资源访问请求被锁定，优先级顺序将按照优先级的降序临时更改为MH，OL，OH和ML。

4. 发明申请

US20050111478A1 Distributed control load shaping method and apparatus 审中-公开
标题翻译：分布式控制负载整形方法及装置
公开(公告)号：US20050111478A1
公开(公告)日：2005-05-26
申请号：US10718936
申请日：2003-11-20
申请人： Jeffrey Brown , Michael Day , Charles Johns , Thuong Truong , Takeshi Yamazaki
发明人： Jeffrey Brown , Michael Day , Charles Johns , Thuong Truong , Takeshi Yamazaki
IPC分类号： H04L12/56 , H04L12/42
CPC分类号： H04L47/822 , H04L47/13 , H04L47/20 , H04L47/22 , H04L47/2441 , H04L47/39 , H04L47/70 , H04L47/72 , H04L47/781 , H04L47/803 , H04L47/821
摘要： Disclosed is an apparatus for controlling or managing the transmission of data packets over a multiplexed communication path, referred to herein as a bus, on a priority basis up to a given authorized BW (Bandwidth), in a given operational time period, for presently authorized devices or applications. Non-managed (not presently authorized) bus requests are handled in a prior art “best effort” basis.
摘要翻译：公开了一种用于在给定的操作时间段内，在给定的操作时间段内优先地基于多路通信路径（这里称为总线）来控制或管理数据分组的传输的装置，用于当前授权的设备或应用程序。非管理（未授权）总线请求以现有技术“尽力而为”为基础来处理。

5. 发明申请

US20080052472A1 METHODS AND APPARATUS FOR REDUCING COMMAND PROCESSING LATENCY WHILE MAINTAINING COHERENCE 失效
标题翻译：在保持协调的同时减少指令处理的方法和装置
公开(公告)号：US20080052472A1
公开(公告)日：2008-02-28
申请号：US11846697
申请日：2007-08-29
申请人： Jeffrey Brown , Scott Clark , Mark Fredrickson , Charles Johns , David Krolak
发明人： Jeffrey Brown , Scott Clark , Mark Fredrickson , Charles Johns , David Krolak
IPC分类号： G06F12/16
CPC分类号： G06F12/0804 , G06F12/0831
摘要： In a first aspect, a first method of reducing command processing latency while maintaining memory coherence is provided. The first method includes the steps of (1) providing a memory map including memory addresses available to a system; and (2) arranging the memory addresses into a plurality of groups. At least one of the groups does not require the system, in response to a command that requires access to a memory address in the group from a bus unit, to get permission from all remaining bus units included in the system to maintain memory coherence. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种在维持存储器一致性的同时降低命令处理等待时间的方法。第一种方法包括以下步骤：（1）提供包括可用于系统的存储器地址的存储器映射; 和（2）将存储器地址排列成多个组。响应于需要访问来自总线单元的组中的存储器地址的命令，组中的至少一个不需要系统以从包括在系统中的所有剩余总线单元获得许可以维持存储器一致性。提供了许多其他方面。

6. 发明申请

US20070186052A1 Methods and apparatus for reducing command processing latency while maintaining coherence 审中-公开
标题翻译：减少命令处理延迟同时保持一致性的方法和装置
公开(公告)号：US20070186052A1
公开(公告)日：2007-08-09
申请号：US11348969
申请日：2006-02-07
申请人： Jeffrey Brown , Scott Clark , Mark Fredrickson , Charles Johns , David Krolak
发明人： Jeffrey Brown , Scott Clark , Mark Fredrickson , Charles Johns , David Krolak
IPC分类号： G06F13/28
CPC分类号： G06F12/0804 , G06F12/0831
摘要： In a first aspect, a first method of reducing command processing latency while maintaining memory coherence is provided. The first method includes the steps of (1) providing a memory map including memory addresses available to a system; and (2) arranging the memory addresses into a plurality of groups. At least one of the groups does not require the system, in response to a command that requires access to a memory address in the group from a bus unit, to get permission from all remaining bus units included in the system to maintain memory coherence. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种在维持存储器一致性的同时降低命令处理等待时间的方法。第一种方法包括以下步骤：（1）提供包括可用于系统的存储器地址的存储器映射; 和（2）将存储器地址排列成多个组。响应于需要访问来自总线单元的组中的存储器地址的命令，组中的至少一个不需要系统以从包括在系统中的所有剩余总线单元获得许可以维持存储器一致性。提供了许多其他方面。

7. 发明申请

US20070174509A1 SYSTEM FOR ASYNCHRONOUS DMA COMMAND COMPLETION NOTIFICATION 失效
标题翻译：异步DMA命令完成通知系统
公开(公告)号：US20070174509A1
公开(公告)日：2007-07-26
申请号：US11695436
申请日：2007-04-02
申请人： Michael Day , Harm Hofstee , Charles Johns , Peichum Liu , Thuong Truong , Takeshi Yamazaki
发明人： Michael Day , Harm Hofstee , Charles Johns , Peichum Liu , Thuong Truong , Takeshi Yamazaki
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： The present invention provides for a system comprising a DMA queue configured to receive a DMA command comprising a tag, wherein the tag belongs to one of a plurality of tag groups. A counter couples to the DMA queue and is configured to increment a tag group count of the tag group to which the tag belongs upon receipt of the DMA command by the DMA queue and to decrement the tag group count upon execution of the DMA command. A tag group count status register couples to the counter and is configured to store the tag group count for each of the plurality of tag groups. And the tag group count status register is further configured to receive a request for a tag group status and to respond to the request for the tag group status.
摘要翻译：本发明提供一种包括配置成接收包括标签的DMA命令的DMA队列的系统，其中标签属于多个标签组之一。计数器耦合到DMA队列，并配置为在DMA队列接收到DMA命令时增加标签组所属标签组的标签组计数，并在执行DMA命令时递减标签组计数。标签组计数状态寄存器耦合到计数器，并被配置为存储多个标签组中的每一个的标签组计数。并且标签组计数状态寄存器被进一步配置为接收对标签组状态的请求并响应对标签组状态的请求。

8. 发明申请

US20070168538A1 Computer architecture and software cells for broadband networks 有权
公开(公告)号：US20070168538A1
公开(公告)日：2007-07-19
申请号：US11716845
申请日：2007-03-12
申请人： Masakazu Suzuoki , Takeshi Yamazaki , Harm Hofstee , Martin Hopkins , Charles Johns , James Kahle , Shigehiro Asano , Atsushi Kunimatsu
发明人： Masakazu Suzuoki , Takeshi Yamazaki , Harm Hofstee , Martin Hopkins , Charles Johns , James Kahle , Shigehiro Asano , Atsushi Kunimatsu
IPC分类号： G06F15/16
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

9. 发明申请

US20050055505A1 Software-controlled cache set management with software-generated class identifiers 失效
标题翻译：软件控制的缓存集管理与软件生成的类标识符
公开(公告)号：US20050055505A1
公开(公告)日：2005-03-10
申请号：US10655365
申请日：2003-09-04
申请人： Michael Day , Harm Hofstee , Charles Johns , James Kahle , David Shippy , Thuong Truong , Takeshi Yamazaki
发明人： Michael Day , Harm Hofstee , Charles Johns , James Kahle , David Shippy , Thuong Truong , Takeshi Yamazaki
IPC分类号： G06F12/00 , G06F12/12
CPC分类号： G06F12/126
摘要： The present invention provides for selectively overwriting sets of a cache as a function of a replacement management table and a least recently used function. A class identifier is created as a function of an address miss. A replacement management table is employable to read the class identifier to create a tag replacement control indicia. The cache, comprising a plurality of sets, is employable to disable the replacement of at least one of the plurality of sets as a function of the tag replacement control indicia.
摘要翻译：本发明提供了根据替换管理表和最近最少使用的功能来选择性地覆盖高速缓存的集合。根据地址未命中创建类标识符。替换管理表可用于读取类标识符以创建标签替换控制标记。包括多个集合的高速缓存可用于根据标签替换控制标记来禁用对多个集合中的至少一个的替换。

10. 发明申请

US20050055478A1 Proxy direct memory access 有权
标题翻译：代理直接内存访问
公开(公告)号：US20050055478A1
公开(公告)日：2005-03-10
申请号：US10655370
申请日：2003-09-04
申请人： Charles Johns , Peichun Liu , Thuong Truong , Asano Shigehiro , Takeshi Yamazaki
发明人： Charles Johns , Peichun Liu , Thuong Truong , Asano Shigehiro , Takeshi Yamazaki
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A system and method are provided for setting up a direct memory access for a first processor. The system includes the first processor and a local memory. The local memory is coupled to the first processor. A first direct memory access controller (DMAC) is coupled to the first processor and the local memory. A system memory is in communication with the first DMAC. A second processor is in communication with the first DMAC such that the second processor sets up the first DMAC to handle data transfer between the local memory and the system memory. The second processor is interrupted when the first DMAC finishes handling the data transfer.
摘要翻译：提供了一种用于为第一处理器建立直接存储器访问的系统和方法。该系统包括第一处理器和本地存储器。本地存储器耦合到第一处理器。第一直接存储器存取控制器（DMAC）耦合到第一处理器和本地存储器。系统存储器与第一DMAC通信。第二处理器与第一DMAC通信，使得第二处理器设置第一DMAC来处理本地存储器和系统存储器之间的数据传输。当第一个DMAC完成处理数据传输时，第二个处理器中断。

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