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1. 发明申请

US20060059273A1 Envelope packet architecture for broadband engine 有权
标题翻译：宽带引擎的信封包架构
公开(公告)号：US20060059273A1
公开(公告)日：2006-03-16
申请号：US10942422
申请日：2004-09-16
申请人： Michael Carnevale , Scott Clark , David Hill , Charles Johns , Thomas Pokrandt , Jeffrey Ruedinger , Dorothy Thelen
发明人： Michael Carnevale , Scott Clark , David Hill , Charles Johns , Thomas Pokrandt , Jeffrey Ruedinger , Dorothy Thelen
IPC分类号： G06F15/16
CPC分类号： H04L1/188
摘要： The present invention provides for sending an envelope and replying to an envelope. A transmitter is configured to send an envelope. A receiver is coupled to the transmitter, wherein the receiver is configured to receive the envelope and generate a reply envelope. A send buffer is coupled to the transmitter. A receive buffer is coupled to the receiver. A retry timer is coupled to the transmitter, wherein the retry timer is configured to reset upon the receipt of a reply envelope correlated to the transmit envelope. The transmitter is configured to retransmit an envelope if the transmitter does not receive a corresponding reply envelope within a selected time period as determined by the retry timer. This leads to a decrease in the total number of envelopes, transmitted from both the transmitter and the receiver.
摘要翻译：本发明提供发送信封并回复信封。发射机被配置为发送信封。接收机耦合到发射机，其中接收机被配置为接收信封并产生回复信封。发送缓冲器耦合到发送器。接收缓冲器耦合到接收器。重试定时器耦合到发射机，其中重试定时器被配置为在接收到与发射包络相关的应答包络时复位。如果发射机在由重试定时器确定的选定时间段内没有接收到对应的应答包络，则发射机被配置为重发信封。这导致从发射机和接收机两者发送的信封总数的减少。

2. 发明申请

US20070253448A1 Method and Apparatus for Implementing Bandwidth Control in a Communications Link 失效
标题翻译：在通信链路中实现带宽控制的方法和装置
公开(公告)号：US20070253448A1
公开(公告)日：2007-11-01
申请号：US11380727
申请日：2006-04-28
申请人： Scott Clark , Dorothy Thelen
发明人： Scott Clark , Dorothy Thelen
IPC分类号： H04J3/18
CPC分类号： H04L47/10 , H04L47/22 , H04L47/28
摘要： A method and apparatus are provided for implementing bandwidth control in a communication link. A set link configuration for the communications link establishes a number of clock cycles required to transmit a data envelope. A control function aligns a start of a data packet on a fixed cycle boundary for data envelope transmissions. The control function aligns the start of a data packet in the same byte of the 16 byte field. The control function is implemented with a memory management input/output (MMIO) register and a counter, and allows a transmitting side of the communications link to control the pacing of data packet transmission or bandwidth by aligning all data packets on fixed-cycle boundaries.
摘要翻译：提供了一种用于在通信链路中实现带宽控制的方法和装置。用于通信链路的设置链路配置建立了发送数据包络所需的多个时钟周期。控制功能使数据封包传输的固定周期边界上的数据包的起始对齐。控制功能将数据包的开始与16字节字段的相同字节对齐。控制功能由存储器管理输入/输出（MMIO）寄存器和计数器实现，允许通信链路的发送侧通过对齐固定周期边界上的所有数据包来控制数据包传输或带宽的起搏。

3. 发明申请

US20070179733A1 Methods and apparatus for testing a link between chips 失效
标题翻译：测试芯片之间链路的方法和装置
公开(公告)号：US20070179733A1
公开(公告)日：2007-08-02
申请号：US11344902
申请日：2006-02-01
申请人： Scott Clark , Dorothy Thelen
发明人： Scott Clark , Dorothy Thelen
IPC分类号： G01M19/00 , G06F19/00
CPC分类号： G01R31/31717
摘要： In a first aspect, a first method of testing a link between a first chip and a second chip is provided. The first method includes the steps of, while operating in a test mode, (1) transmitting test data of sufficient length to enable exercising of worst case transitions from the first chip to the second chip via the link; and (2) performing cyclic redundancy checking (CRC) on the test data to test the link. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了测试第一芯片和第二芯片之间的链路的第一种方法。第一种方法包括以下步骤：在测试模式下工作时，（1）发送具有足够长度的测试数据，以便能够通过该链路实现从第一芯片到第二芯片的最坏情况转换; 和（2）对测试数据执行循环冗余校验（CRC）以测试链路。提供了许多其他方面。

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