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1. 发明申请

US20070069269A1 Stacked capacitor and method of fabricating same 有权
标题翻译：堆叠电容器及其制造方法
公开(公告)号：US20070069269A1
公开(公告)日：2007-03-29
申请号：US11549248
申请日：2006-10-13
申请人： Scott Balster , Badih El-Kareh , Philipp Steinmann , Christoph Dirnecker
发明人： Scott Balster , Badih El-Kareh , Philipp Steinmann , Christoph Dirnecker
IPC分类号： H01L27/108 , H01L29/94 , H01L29/76 , H01L31/119
CPC分类号： H01L28/40 , H01L27/0629 , H01L27/0805
摘要： The invention relates to a stacked capacitor (10) comprising a silicon base plate (16), a poly-silicon center plate (32) arranged above the base plate (16), a lower gate-oxide dielectric (26) arranged between the base plate (16) and the center plate (32), a cover plate (36) made of a metallic conductor and arranged above the center plate (32), and an upper dielectric (34) arranged between the center plate (32) and the cover plate (36). The cover plate (36) and the base plate (16) are electrically connected to each other and together form a first capacitor electrode. The center plate (32) forms a second capacitor electrode. The invention further relates to an integrated circuit with such a stacked capacitor, as well as to a method for fabrication of a stacked capacitor as part of a CMOS process.
摘要翻译：本发明涉及一种堆叠式电容器（10），包括硅基板（16），布置在基板（16）上方的多晶硅中心板（32），下栅极氧化物电介质（26）板（16）和中心板（32），由中心板（32）上方布置的金属导体制成的盖板（36）和布置在中心板（32）和盖板（36）。盖板（36）和基板（16）彼此电连接并一起形成第一电容器电极。中心板（32）形成第二电容器电极。本发明还涉及具有这种堆叠电容器的集成电路，以及作为CMOS工艺的一部分的用于制造堆叠电容器的方法。

2. 发明授权

US07130182B2 Stacked capacitor and method for fabricating same 有权
标题翻译：堆叠电容器及其制造方法
公开(公告)号：US07130182B2
公开(公告)日：2006-10-31
申请号：US10830629
申请日：2004-04-22
申请人： Scott Balster , Badih El-Kareh , Philipp Steinmann , Christoph Dirnecker
发明人： Scott Balster , Badih El-Kareh , Philipp Steinmann , Christoph Dirnecker
IPC分类号： H01G4/00
CPC分类号： H01L28/40 , H01L27/0629 , H01L27/0805
摘要： The invention relates to a stacked capacitor (10) comprising a silicon base plate (16), a poly-silicon center plate (32) arranged above the base plate (16), a lower gate-oxide dielectric (26) arranged between the base plate (16) and the center plate (32), a cover plate (36) made of a metallic conductor and arranged above the center plate (32), and an upper dielectric (34) arranged between the center plate (32) and the cover plate (36). The cover plate (36) and the base plate (16) are electrically connected to each other and together form a first capacitor electrode. The center plate (32) forms a second capacitor electrode. The invention further relates to an integrated circuit with such a stacked capacitor, as well as to a method for fabrication of a stacked capacitor as part of a CMOS process.
摘要翻译：本发明涉及一种堆叠式电容器（10），包括硅基板（16），布置在基板（16）上方的多晶硅中心板（32），下栅极氧化物电介质（26）板（16）和中心板（32），由中心板（32）上方布置的金属导体制成的盖板（36）和布置在中心板（32）和盖板（36）。盖板（36）和基板（16）彼此电连接并一起形成第一电容器电极。中心板（32）形成第二电容器电极。本发明还涉及具有这种堆叠电容器的集成电路，以及作为CMOS工艺的一部分的用于制造堆叠电容器的方法。

3. 发明申请

US20100136764A1 METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT 有权
标题翻译：制造集成电路的方法
公开(公告)号：US20100136764A1
公开(公告)日：2010-06-03
申请号：US12624442
申请日：2009-11-24
申请人： Christoph Dirnecker , Philipp Steinmann , Badih El-Kareh
发明人： Christoph Dirnecker , Philipp Steinmann , Badih El-Kareh
IPC分类号： H01L21/02
CPC分类号： H01L21/76843 , H01L21/76838 , H01L23/5228 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing an integrated circuit comprises depositing a electrically resistive layer of a material for serving as a thin film resistor (TFR), depositing an electrically insulating layer on the resistor layer, removing the electrically insulating layer from outside an electrically active area of the resistor layer corresponding to a target TFR area, and depositing an electrically conductive layer of an electrically conductive material such that the conductive layer overlaps the target TFR area and the conductive layer electrically contacts the resistor layer outside the target TFR area.
摘要翻译：一种制造集成电路的方法包括沉积用作薄膜电阻器（TFR）的材料的电阻层，在电阻层上沉积电绝缘层，从电离层的电活性区域外部去除电绝缘层对应于目标TFR区域的电阻层，以及沉积导电材料的导电层，使得导电层与靶TFR区域重叠，导电层与目标TFR区域外的电阻层电接触。

4. 发明授权

US08012844B2 Method of manufacturing an integrated circuit 有权
标题翻译：集成电路的制造方法
公开(公告)号：US08012844B2
公开(公告)日：2011-09-06
申请号：US12624442
申请日：2009-11-24
申请人： Christoph Dirnecker , Philipp Steinmann , Badih El-Kareh
发明人： Christoph Dirnecker , Philipp Steinmann , Badih El-Kareh
IPC分类号： H01L21/20
CPC分类号： H01L21/76843 , H01L21/76838 , H01L23/5228 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing an integrated circuit comprises depositing a electrically resistive layer of a material for serving as a thin film resistor (TFR), depositing an electrically insulating layer on the resistor layer, removing the electrically insulating layer from outside an electrically active area of the resistor layer corresponding to a target TFR area, and depositing an electrically conductive layer of an electrically conductive material such that the conductive layer overlaps the target TFR area and the conductive layer electrically contacts the resistor layer outside the target TFR area.
摘要翻译：一种制造集成电路的方法包括沉积用作薄膜电阻器（TFR）的材料的电阻层，在电阻层上沉积电绝缘层，从电离层的电活性区域外部去除电绝缘层对应于目标TFR区域的电阻层，以及沉积导电材料的导电层，使得导电层与靶TFR区域重叠，导电层与目标TFR区域外的电阻层电接触。

5. 发明授权

US07217322B2 Method of fabricating an epitaxial silicon-germanium layer and an integrated semiconductor device comprising an epitaxial arsenic in-situ doped silicon-germanium layer 有权
标题翻译：制造外延硅锗层的方法和包括外延砷原位掺杂硅 - 锗层的集成半导体器件
公开(公告)号：US07217322B2
公开(公告)日：2007-05-15
申请号：US10934188
申请日：2004-09-02
申请人： Jeffrey A. Babcock , Scott Balster , Alfred Haeusler , Angelo Pinto , Manfred Schiekofer , Philipp Steinmann , Badih El-Kareh
发明人： Jeffrey A. Babcock , Scott Balster , Alfred Haeusler , Angelo Pinto , Manfred Schiekofer , Philipp Steinmann , Badih El-Kareh
IPC分类号： C30B25/04
CPC分类号： C23C16/42 , C23C16/56 , H01L21/02532 , H01L21/02576
摘要： A method of fabricating an epitaxial silicon-germanium layer for an integrated semiconductor device comprises the step of depositing an arsenic in-situ doped silicon-germanium layer, wherein arsenic and germanium are introduced subsequently into different regions of said silicon-germanium layer during deposition of said silicon-germanium layer. By separating arsenic from germanium any interaction between arsenic and germanium is avoided during deposition thereby allowing fabricating silicon-germanium layers with reproducible doping profiles.
摘要翻译：制造用于集成半导体器件的外延硅 - 锗层的方法包括沉积砷原位掺杂硅 - 锗层的步骤，其中砷和锗随后在沉积期间被引入所述硅 - 锗层的不同区域所述硅 - 锗层。通过从锗中分离砷，可避免在沉积过程中砷和锗之间的相互作用，从而允许制造具有可重复掺杂分布的硅 - 锗层。

6. 发明授权

US07118981B2 Method of fabricating an integrated silicon-germanium heterobipolar transistor and an integrated silicon-germanium heterobipolar transistor 有权
标题翻译：制造集成硅 - 锗异双极晶体管和集成硅 - 锗异双极晶体管的方法
公开(公告)号：US07118981B2
公开(公告)日：2006-10-10
申请号：US10824745
申请日：2004-04-15
申请人： Alfred Haeusler , Philipp Steinmann , Scott Balster , Badih El-Kareh
发明人： Alfred Haeusler , Philipp Steinmann , Scott Balster , Badih El-Kareh
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/7378
摘要： In a method of fabricating an integrated silicon-germanium heterobipolar transistor a silicon dioxide layer arranged between a silicon-germanium base layer and a silicon emitter layer is formed by means of Rapid Thermal Processing (RTP) to ensure enhanced component properties of the integrated silicon-germanium heterobipolar transistor.
摘要翻译：在制造集成硅 - 锗异质晶体管的方法中，通过快速热处理（RTP）形成布置在硅 - 锗基底层和硅发射极层之间的二氧化硅层，以确保集成硅 - 锗异双极晶体管。

7. 发明授权

US07498639B2 Integrated BiCMOS semiconductor circuit 有权
标题翻译：集成BiCMOS半导体电路
公开(公告)号：US07498639B2
公开(公告)日：2009-03-03
申请号：US11233960
申请日：2005-09-23
申请人： Philipp Steinmann , Scott Balster , Badih El-Kareh , Thomas Scharnagl , Michael Schmitt
发明人： Philipp Steinmann , Scott Balster , Badih El-Kareh , Thomas Scharnagl , Michael Schmitt
IPC分类号： H01L31/112
CPC分类号： H01L27/0623 , H01L21/76229 , H01L21/8249 , H01L27/0207
摘要： An integrated BiCMOS semiconductor circuit has active moat areas in silicon. The active moat areas include electrically active components of the semiconductor circuit, which comprise active window structures for base and/or emitter windows. The integrated BiCMOS semiconductor circuit has zones where silicon is left to form dummy moat areas which do not include electrically active components, and has isolation trenches to separate the active moat areas from each other and from the dummy moat areas. The dummy moat areas comprise dummy window structures having geometrical dimensions and shapes similar to those of the active window structures for the base and/or emitter windows.
摘要翻译：集成的BiCMOS半导体电路在硅中具有积极的护城河区域。活动的护壕区域包括半导体电路的电活性部件，其包括用于基底和/或发射器窗口的有源窗口结构。集成的BiCMOS半导体电路具有区域，其中硅留下以形成不包括电活性部件的虚拟护城河区域，并且具有隔离沟槽以将活动的护壕区域彼此分开并与虚拟的护城河区域分离。虚拟护城河区域包括具有几何尺寸和形状的虚拟窗户结构，其类似于用于基座和/或发射器窗口的活动窗口结构的几何尺寸和形状。

8. 发明授权

US07192838B2 Method of producing complementary SiGe bipolar transistors 有权
标题翻译：制造互补SiGe双极晶体管的方法
公开(公告)号：US07192838B2
公开(公告)日：2007-03-20
申请号：US10928655
申请日：2004-08-26
申请人： Philipp Steinmann , Scott Balster , Badih El-Kareh , Thomas Scharnagl
发明人： Philipp Steinmann , Scott Balster , Badih El-Kareh , Thomas Scharnagl
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L21/82285 , H01L29/7378
摘要： Method of producing complementary SiGe bipolar transistors. In a method of producing complementary SiGe bipolar transistors, interface oxide layers (38, 58) for NPN and PNP emitters (44, 64), are separately formed and emitter polysilicon (40, 60) is separately patterned, allowing these layers to be optimized for the respective conductivity type.
摘要翻译：制造互补SiGe双极晶体管的方法。在制造互补SiGe双极晶体管的方法中，分别形成用于NPN和PNP发射极（44,64）的界面氧化物层（38,58），发射极多晶硅（40,60）被分开构图，允许这些层被优化对于各自的导电类型。

9. 发明申请

US20050014341A1 Method of fabricating complementary bipolar transistors with SiGe base regions 有权
标题翻译：用SiGe基极区制造互补双极晶体管的方法
公开(公告)号：US20050014341A1
公开(公告)日：2005-01-20
申请号：US10822078
申请日：2004-04-08
申请人： Badih El-Kareh , Scott Balster , Philipp Steinmann , Thomas Scharnagl , Manfred Schiekofer , Carl Willis
发明人： Badih El-Kareh , Scott Balster , Philipp Steinmann , Thomas Scharnagl , Manfred Schiekofer , Carl Willis
IPC分类号： H01L21/331 , H01L21/8228
CPC分类号： H01L29/66242 , H01L21/82285
摘要： In a method of fabricating complementary bipolar transistors with SiGe base regions the base regions of the NPN and PNP transistors are formed one after the other over two collector regions 20, 14 by epitaxial deposition of crystalline silicon-germanium layers 32a, 36a. With this method the germanium profile of the SiGe layers can be freely selected for both NPN and PNP transistors in thus enabling complementary transistor performance to be optimized individually. The SiGe layers 32a, 36a can be doped with an n-type or p-type dopant during or after deposition of the silicon-germanium layers 32a, 36a.
摘要翻译：在制造具有SiGe基极区域的互补双极晶体管的方法中，NPN和PNP晶体管的基极区域通过晶体硅 - 锗层32a，36a的外延沉积而在两个集电极区域20,14之间一个接一个地形成。使用这种方法，可以自由地为NPN和PNP晶体管选择SiGe层的锗分布，从而可以单独优化互补晶体管的性能。 SiGe层32a，36a可以在硅 - 锗层32a，36a沉积期间或之后掺杂n型或p型掺杂剂。

10. 发明申请

US20050001236A1 Method of fabricating an integrated silicon-germanium heterobipolar transistor and an integrated silicon-germanium heterobipolar transistor 有权
标题翻译：制造集成硅 - 锗异双极晶体管和集成硅 - 锗异双极晶体管的方法
公开(公告)号：US20050001236A1
公开(公告)日：2005-01-06
申请号：US10824745
申请日：2004-04-15
申请人： Alfred Haeusler , Philipp Steinmann , Scott Balster , Badih El-Kareh
发明人： Alfred Haeusler , Philipp Steinmann , Scott Balster , Badih El-Kareh
IPC分类号： H01L21/331 , H01L21/8222 , H01L29/737 , H01L31/0328
CPC分类号： H01L29/7378
摘要： In a method of fabricating an integrated silicon-germanium heterobipolar transistor a silicon dioxide layer arranged between a silicon-germanium base layer and a silicon emitter layer is formed by means of Rapid Thermal Processing (RTP) to ensure enhanced component properties of the integrated silicon-germanium heterobipolar transistor.
摘要翻译：在制造集成硅 - 锗异质晶体管的方法中，通过快速热处理（RTP）形成布置在硅 - 锗基底层和硅发射极层之间的二氧化硅层，以确保集成硅 - 锗异双极晶体管。

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