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1. 发明授权

US07498639B2 Integrated BiCMOS semiconductor circuit 有权
标题翻译：集成BiCMOS半导体电路
公开(公告)号：US07498639B2
公开(公告)日：2009-03-03
申请号：US11233960
申请日：2005-09-23
申请人： Philipp Steinmann , Scott Balster , Badih El-Kareh , Thomas Scharnagl , Michael Schmitt
发明人： Philipp Steinmann , Scott Balster , Badih El-Kareh , Thomas Scharnagl , Michael Schmitt
IPC分类号： H01L31/112
CPC分类号： H01L27/0623 , H01L21/76229 , H01L21/8249 , H01L27/0207
摘要： An integrated BiCMOS semiconductor circuit has active moat areas in silicon. The active moat areas include electrically active components of the semiconductor circuit, which comprise active window structures for base and/or emitter windows. The integrated BiCMOS semiconductor circuit has zones where silicon is left to form dummy moat areas which do not include electrically active components, and has isolation trenches to separate the active moat areas from each other and from the dummy moat areas. The dummy moat areas comprise dummy window structures having geometrical dimensions and shapes similar to those of the active window structures for the base and/or emitter windows.
摘要翻译：集成的BiCMOS半导体电路在硅中具有积极的护城河区域。活动的护壕区域包括半导体电路的电活性部件，其包括用于基底和/或发射器窗口的有源窗口结构。集成的BiCMOS半导体电路具有区域，其中硅留下以形成不包括电活性部件的虚拟护城河区域，并且具有隔离沟槽以将活动的护壕区域彼此分开并与虚拟的护城河区域分离。虚拟护城河区域包括具有几何尺寸和形状的虚拟窗户结构，其类似于用于基座和/或发射器窗口的活动窗口结构的几何尺寸和形状。

2. 发明申请

US20060073672A1 Integrated BiCMOS semiconductor circuit 有权
公开(公告)号：US20060073672A1
公开(公告)日：2006-04-06
申请号：US11233960
申请日：2005-09-23
申请人： Philipp Steinmann , Scott Balster , Badih El-Kareh , Thomas Scharnagl , Michael Schmitt
发明人： Philipp Steinmann , Scott Balster , Badih El-Kareh , Thomas Scharnagl , Michael Schmitt
IPC分类号： H01L21/76
CPC分类号： H01L27/0623 , H01L21/76229 , H01L21/8249 , H01L27/0207
摘要： An integrated BiCMOS semiconductor circuit has active moat areas in silicon. The active moat areas include electrically active components of the semiconductor circuit, which comprise active window structures for base and/or emitter windows. The integrated BiCMOS semiconductor circuit has zones where silicon is left to form dummy moat areas which do not include electrically active components, and has isolation trenches to separate the active moat areas from each other and from the dummy moat areas. The dummy moat areas comprise dummy window structures having geometrical dimensions and shapes similar to those of the active window structures for the base and/or emitter windows.

3. 发明授权

US07192838B2 Method of producing complementary SiGe bipolar transistors 有权
标题翻译：制造互补SiGe双极晶体管的方法
公开(公告)号：US07192838B2
公开(公告)日：2007-03-20
申请号：US10928655
申请日：2004-08-26
申请人： Philipp Steinmann , Scott Balster , Badih El-Kareh , Thomas Scharnagl
发明人： Philipp Steinmann , Scott Balster , Badih El-Kareh , Thomas Scharnagl
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L21/82285 , H01L29/7378
摘要： Method of producing complementary SiGe bipolar transistors. In a method of producing complementary SiGe bipolar transistors, interface oxide layers (38, 58) for NPN and PNP emitters (44, 64), are separately formed and emitter polysilicon (40, 60) is separately patterned, allowing these layers to be optimized for the respective conductivity type.
摘要翻译：制造互补SiGe双极晶体管的方法。在制造互补SiGe双极晶体管的方法中，分别形成用于NPN和PNP发射极（44,64）的界面氧化物层（38,58），发射极多晶硅（40,60）被分开构图，允许这些层被优化对于各自的导电类型。

4. 发明申请

US20050014341A1 Method of fabricating complementary bipolar transistors with SiGe base regions 有权
标题翻译：用SiGe基极区制造互补双极晶体管的方法
公开(公告)号：US20050014341A1
公开(公告)日：2005-01-20
申请号：US10822078
申请日：2004-04-08
申请人： Badih El-Kareh , Scott Balster , Philipp Steinmann , Thomas Scharnagl , Manfred Schiekofer , Carl Willis
发明人： Badih El-Kareh , Scott Balster , Philipp Steinmann , Thomas Scharnagl , Manfred Schiekofer , Carl Willis
IPC分类号： H01L21/331 , H01L21/8228
CPC分类号： H01L29/66242 , H01L21/82285
摘要： In a method of fabricating complementary bipolar transistors with SiGe base regions the base regions of the NPN and PNP transistors are formed one after the other over two collector regions 20, 14 by epitaxial deposition of crystalline silicon-germanium layers 32a, 36a. With this method the germanium profile of the SiGe layers can be freely selected for both NPN and PNP transistors in thus enabling complementary transistor performance to be optimized individually. The SiGe layers 32a, 36a can be doped with an n-type or p-type dopant during or after deposition of the silicon-germanium layers 32a, 36a.
摘要翻译：在制造具有SiGe基极区域的互补双极晶体管的方法中，NPN和PNP晶体管的基极区域通过晶体硅 - 锗层32a，36a的外延沉积而在两个集电极区域20,14之间一个接一个地形成。使用这种方法，可以自由地为NPN和PNP晶体管选择SiGe层的锗分布，从而可以单独优化互补晶体管的性能。 SiGe层32a，36a可以在硅 - 锗层32a，36a沉积期间或之后掺杂n型或p型掺杂剂。

5. 发明授权

US07144789B2 Method of fabricating complementary bipolar transistors with SiGe base regions 有权
标题翻译：用SiGe基极区制造互补双极晶体管的方法
公开(公告)号：US07144789B2
公开(公告)日：2006-12-05
申请号：US10822078
申请日：2004-04-08
申请人： Badih El-Kareh , Scott Balster , Philipp Steinmann , Thomas Scharnagl , Manfred Schiekofer , Carl Willis
发明人： Badih El-Kareh , Scott Balster , Philipp Steinmann , Thomas Scharnagl , Manfred Schiekofer , Carl Willis
IPC分类号： H01L21/8222
CPC分类号： H01L29/66242 , H01L21/82285
摘要： In a method of fabricating complementary bipolar transistors with SiGe base regions the base regions of the NPN and PNP transistors are formed one after the other over two collector regions 20, 14 by epitaxial deposition of crystalline silicon-germanium layers 32a, 36a. With this method the germanium profile of the SiGe layers can be freely selected for both NPN and PNP transistors in thus enabling complementary transistor performance to be optimized individually. The SiGe layers 32a, 36a can be doped with an n-type or p-type dopant during or after deposition of the silicon-germanium layers 32a, 36a.
摘要翻译：在制造具有SiGe基极区域的互补双极晶体管的方法中，NPN和PNP晶体管的基极区域通过外延沉积晶体硅 - 锗层32a，36a而一个接一个地在两个集电极区域20,14之间形成。使用这种方法，可以自由地为NPN和PNP晶体管选择SiGe层的锗分布，从而可以单独优化互补晶体管的性能。 SiGe层32a，36a可以在硅 - 锗层32a，36a沉积期间或之后掺杂n型或p型掺杂剂。

6. 发明申请

US20050054170A1 Method of producing complementary sige bipolar transistors 有权
标题翻译：制造互补型双极晶体管的方法
公开(公告)号：US20050054170A1
公开(公告)日：2005-03-10
申请号：US10928655
申请日：2004-08-26
申请人： Philipp Steinmann , Scott Balster , Badih El-Kareh , Thomas Scharnagl
发明人： Philipp Steinmann , Scott Balster , Badih El-Kareh , Thomas Scharnagl
IPC分类号： H01L21/331 , H01L21/8228 , H01L29/737 , H01L21/44 , H01L21/8222
CPC分类号： H01L29/66242 , H01L21/82285 , H01L29/7378
摘要： Method of producing complementary SiGe bipolar transistors. In a method of producing complementary SiGe bipolar transistors, interface oxide layers (38, 58) for NPN and PNP emitters (44, 64), are separately formed and emitter polysilicon (40, 60) is separately patterned, allowing these layers to be optimized for the respective conductivity type.
摘要翻译：制造互补SiGe双极晶体管的方法。在制造互补SiGe双极晶体管的方法中，分别形成用于NPN和PNP发射极（44,64）的界面氧化物层（38,58），发射极多晶硅（40,60）被分开构图，允许这些层被优化对于各自的导电类型。

7. 发明授权

US08932942B2 Method of forming an electrical contact between a support wafer and the surface of a top silicon layer of a silicon-on-insulator wafer and an electrical device including such an electrical contact 有权
标题翻译：在支撑晶片和绝缘体上硅晶片的顶部硅层的表面之间形成电接触的方法以及包括这种电接触
公开(公告)号：US08932942B2
公开(公告)日：2015-01-13
申请号：US12729682
申请日：2010-03-23
申请人： Philipp Steinmann , Manfred Schiekofer , Michael Kraus , Thomas Scharnagl , Wolfgang Schwartz
发明人： Philipp Steinmann , Manfred Schiekofer , Michael Kraus , Thomas Scharnagl , Wolfgang Schwartz
IPC分类号： H01L29/06 , H01L21/74 , H01L21/02 , H01L21/84
CPC分类号： H01L21/743 , H01L21/02532 , H01L21/02639 , H01L21/84
摘要： Method of forming an electrical contact between a support wafer and a surface of a top silicon layer of a silicon-on-insulator wafer. The method comprises etching a cavity into the top silicon layer and the insulator layer. A selective epitaxial step is performed for growing an epitaxial layer of silicon inside the cavity up to the surface of the top silicon layer. An electrical device comprising an electrical contact between a support wafer and a surface of a top silicon layer of a silicon-on-insulator wafer formed according to the inventive method.
摘要翻译：在支撑晶片和绝缘体上硅晶片的顶部硅层的表面之间形成电接触的方法。该方法包括将空腔蚀刻到顶部硅层和绝缘体层中。执行选择性外延步骤，以在空腔内生长直到顶部硅层的表面的硅外延层。一种电气装置，其包括根据本发明方法形成的在支撑晶片和绝缘体上硅晶片的顶部硅层的表面之间的电接触。

8. 发明授权

US08853094B2 Method for manufacturing a semiconductor structure 有权
标题翻译：半导体结构的制造方法
公开(公告)号：US08853094B2
公开(公告)日：2014-10-07
申请号：US13401537
申请日：2012-02-21
申请人： Thomas Scharnagl , Berthold Staufer
发明人： Thomas Scharnagl , Berthold Staufer
IPC分类号： H01L21/302 , H01L27/082 , H01L21/8228 , H01L29/66
CPC分类号： H01L29/66272 , H01L21/8228 , H01L27/082
摘要： A method for manufacturing a semiconductor structure comprising complementary bipolar transistors, wherein for manufacture of a PNP-type structure, an emitter layer having a surface oxide layer is present on top of an NPN-type structure, the emitter layer comprising lateral and vertical surfaces, and wherein for removal of the oxide layer, an ion etching step is applied, wherein for the on etching step a plasma for providing ions is generated in a vacuum chamber by RF coupling and the generated ions are accelerated by an acceleration voltage between the plasma and a wafer comprising the semiconductor structure, and wherein the plasma generation and the ion acceleration are controlled independently from each other.
摘要翻译：一种用于制造包括互补双极晶体管的半导体结构的方法，其中为了制造PNP型结构，具有表面氧化物层的发射极层位于NPN型结构的顶部，发射极层包括横向和垂直表面，并且其中为了去除氧化物层，应用离子蚀刻步骤，其中对于上蚀刻步骤，通过RF耦合在真空室中产生用于提供离子的等离子体，并且所产生的离子通过等离子体和包括半导体结构的晶片，并且其中等离子体产生和离子加速彼此独立地被控制。

9. 发明申请

US20130308768A1 METHOD FOR COMMUNICATION AND COMPONENTS IN A COMMUNICATIONS NETWORK 有权
标题翻译：通信网络中的通信和组件的方法
公开(公告)号：US20130308768A1
公开(公告)日：2013-11-21
申请号：US13982948
申请日：2011-03-02
申请人： Michael Tietsch , Karl Klaghofer , Holger Prange , Thomas Scharnagl
发明人： Michael Tietsch , Karl Klaghofer , Holger Prange , Thomas Scharnagl
IPC分类号： H04M3/42
CPC分类号： H04L63/10 , H04L63/105 , H04L63/107 , H04L63/108 , H04L65/1086 , H04L65/80 , H04L67/32 , H04M3/38 , H04M3/42153 , H04W64/00 , H04W76/50
摘要： With a method for communication in a communication network, a subscriber is assigned an authorization level depending on the respective applicable scenario at the time when the authorization level is assigned for that subscriber in that communication network.
摘要翻译：通过在通信网络中进行通信的方法，根据在该通信网络中为该用户分配了授权级别时的相应适用场景，为用户分配授权级别。

10. 发明授权

US08129248B2 Method of producing bipolar transistor structures in a semiconductor process 有权
标题翻译：在半导体工艺中制造双极晶体管结构的方法
公开(公告)号：US08129248B2
公开(公告)日：2012-03-06
申请号：US12833573
申请日：2010-07-09
申请人： Thomas Scharnagl , Berthold Staufer
发明人： Thomas Scharnagl , Berthold Staufer
IPC分类号： H01L29/70 , H01L21/328
CPC分类号： H01L21/0262 , H01L21/02532 , H01L21/02658 , H01L29/66272
摘要： In the method of producing bipolar transistor structures in a semiconductor process, an advanced epitaxial trisilane process can be used without the risk of poly stringers being formed. A base window is structured in a polycrystalline silicon layer covered with an oxide layer, and a further step is epitaxial growing of a silicon layer in the base window from trisilane. The window structuring is performed in a sequence of anisotropic etch and isotropic ash steps, thereby creating stepped and inwardly sloping window edges. Due to the inwardly sloping side walls of the window, the epitaxially grown silicon layer is formed without inwardly overhanging structures, and the cause of poly stringers forming is thus eliminated.
摘要翻译：在半导体工艺中制造双极晶体管结构的方法中，可以使用先进的外延硅烷工艺，而不会形成多晶硅的形成。基窗构造在被氧化物层覆盖的多晶硅层中，另外的步骤是从硅烷在基窗中外延生长硅层。窗构造以各向异性蚀刻和各向异性灰阶的顺序执行，从而产生阶梯式和向内倾斜的窗口边缘。由于窗口的向内倾斜的侧壁，外延生长的硅层形成为没有向内突出的结构，因此消除了形成多桁条的原因。

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