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1. 发明授权

US08603374B2 Processes for producing a polymer-bonded fiber agglomerate and a fiber-reinforced composite material 有权
标题翻译：用于制备聚合物粘合纤维聚集体和纤维增强复合材料的方法
公开(公告)号：US08603374B2
公开(公告)日：2013-12-10
申请号：US13226893
申请日：2011-09-07
申请人： Peter Domagalski , Alfred Haeusler , Ingrid Kraetschmer , Andreas Kienzle , Dieter Wuestner
发明人： Peter Domagalski , Alfred Haeusler , Ingrid Kraetschmer , Andreas Kienzle , Dieter Wuestner
IPC分类号： B05D3/02 , C01B31/00
CPC分类号： F16D69/023 , C04B35/573 , C04B35/6269 , C04B35/62873 , C04B35/63476 , C04B35/83 , C04B2235/425 , C04B2235/5248 , C04B2235/526 , C04B2235/5264 , C04B2235/604 , C04B2235/616 , C04B2235/96 , C08J5/04 , D04H1/4209 , D04H1/4218 , D04H1/4234 , D04H1/4242 , F16D69/026 , F16D2200/0047 , Y10T428/249924 , Y10T428/2933
摘要： A polymer-bonded fiber agglomerate includes short fibers selected from carbon, ceramic materials, glasses, metals and organic polymers, and a polymeric bonding resin selected from synthetic resins and thermoplastics. The fiber agglomerates have an average length, measured in the fiber direction, of from 3 mm to 50 mm and an average thickness, measured perpendicularly to the fiber direction, of from 0.1 mm to 10 mm. At least 75% of all of the contained fibers have a length which is at least 90% and not more than 110% of the fiber agglomerate average length. A fiber-reinforced composite material having the fiber agglomerate and processes for the production thereof are also provided.
摘要翻译：聚合物粘合的纤维团聚体包括选自碳，陶瓷材料，玻璃，金属和有机聚合物的短纤维，以及选自合成树脂和热塑性塑料的聚合物粘合树脂。纤维聚集体具有从纤维方向测量的平均长度为3mm至50mm，垂直于纤维方向测量的平均厚度为0.1mm至10mm。所有所含纤维的至少75％的长度为纤维聚集体平均长度的至少90％且不超过110％。还提供了具有纤维附聚物的纤维增强复合材料及其生产方法。

2. 发明授权

US08093115B2 Tuning of SOI substrate doping 有权
标题翻译：调整SOI衬底掺杂
公开(公告)号：US08093115B2
公开(公告)日：2012-01-10
申请号：US12886727
申请日：2010-09-21
申请人： Wolfgang Schwartz , Alfred Haeusler , Vladimir Frank Drobny
发明人： Wolfgang Schwartz , Alfred Haeusler , Vladimir Frank Drobny
IPC分类号： H01L21/338 , H01L21/425
CPC分类号： H01L21/84 , H01L21/2652
摘要： A method of manufacturing a semiconductor device, the method comprising: taking an SOI substrate comprising a bulk substrate, a buried insulating layer and an active layer, and implanting the bulk substrate from the side of and through the insulating layer and the active layer so as to generate an area having an increased doping concentration in the bulk substrate at the interface between the bulk substrate and the insulating layer.
摘要翻译：一种制造半导体器件的方法，所述方法包括：获取包含体基板，埋入绝缘层和有源层的SOI衬底，以及从所述绝缘层和所述有源层的侧面和所述有源层的侧面注入所述本体衬底，以便以在体基板和绝缘层之间的界面处产生在体基板中具有增加的掺杂浓度的区域。

3. 发明授权

US07888225B2 Method of manufacturing an electronic device including a PNP bipolar transistor 有权
标题翻译：制造包括PNP双极晶体管的电子器件的方法
公开(公告)号：US07888225B2
公开(公告)日：2011-02-15
申请号：US12390639
申请日：2009-02-23
申请人： Alfred Haeusler
发明人： Alfred Haeusler
IPC分类号： H01L21/331
CPC分类号： H01L29/7311
摘要： A method of manufacturing an electronic device including a PNP bipolar transistor comprises forming a collector in a substrate, depositing a base layer and an emitter layer on the substrate, and growing a nitride interface layer on the base layer as a base current modulation means, such that the nitride interface layer is arranged between the base layer and the emitter layer.
摘要翻译：一种制造包括PNP双极晶体管的电子器件的方法，包括在衬底中形成集电极，在衬底上沉积基极层和发射极层，以及在基极层上生长氮化物界面层作为基极电流调制装置，氮化物界面层设置在基底层和发射极层之间。

4. 发明申请

US20090212393A1 METHOD OF MANUFACTURING AN ELECTRONIC DEVICE INCLUDING A PNP BIPOLAR TRANSISTOR 有权
标题翻译：制造包括PNP双极晶体管的电子器件的方法
公开(公告)号：US20090212393A1
公开(公告)日：2009-08-27
申请号：US12390639
申请日：2009-02-23
申请人： Alfred Haeusler
发明人： Alfred Haeusler
IPC分类号： H01L29/739 , H01L21/331
CPC分类号： H01L29/7311
摘要： A method of manufacturing an electronic device including a PNP bipolar transistor comprises forming a collector in a substrate, depositing a base layer and an emitter layer on the substrate, and growing a nitride interface layer on the base layer as a base current modulation means, such that the nitride interface layer is arranged between the base layer and the emitter layer.
摘要翻译：一种制造包括PNP双极晶体管的电子器件的方法，包括在衬底中形成集电极，在衬底上沉积基极层和发射极层，以及在基极层上生长氮化物界面层作为基极电流调制装置，氮化物界面层设置在基底层和发射极层之间。

5. 发明授权

US07217322B2 Method of fabricating an epitaxial silicon-germanium layer and an integrated semiconductor device comprising an epitaxial arsenic in-situ doped silicon-germanium layer 有权
标题翻译：制造外延硅锗层的方法和包括外延砷原位掺杂硅 - 锗层的集成半导体器件
公开(公告)号：US07217322B2
公开(公告)日：2007-05-15
申请号：US10934188
申请日：2004-09-02
申请人： Jeffrey A. Babcock , Scott Balster , Alfred Haeusler , Angelo Pinto , Manfred Schiekofer , Philipp Steinmann , Badih El-Kareh
发明人： Jeffrey A. Babcock , Scott Balster , Alfred Haeusler , Angelo Pinto , Manfred Schiekofer , Philipp Steinmann , Badih El-Kareh
IPC分类号： C30B25/04
CPC分类号： C23C16/42 , C23C16/56 , H01L21/02532 , H01L21/02576
摘要： A method of fabricating an epitaxial silicon-germanium layer for an integrated semiconductor device comprises the step of depositing an arsenic in-situ doped silicon-germanium layer, wherein arsenic and germanium are introduced subsequently into different regions of said silicon-germanium layer during deposition of said silicon-germanium layer. By separating arsenic from germanium any interaction between arsenic and germanium is avoided during deposition thereby allowing fabricating silicon-germanium layers with reproducible doping profiles.
摘要翻译：制造用于集成半导体器件的外延硅 - 锗层的方法包括沉积砷原位掺杂硅 - 锗层的步骤，其中砷和锗随后在沉积期间被引入所述硅 - 锗层的不同区域所述硅 - 锗层。通过从锗中分离砷，可避免在沉积过程中砷和锗之间的相互作用，从而允许制造具有可重复掺杂分布的硅 - 锗层。

6. 发明申请

US20060197158A1 Advanced CMOS using Super Steep Retrograde Wells 有权
标题翻译：高级CMOS使用超级陡峭逆行井
公开(公告)号：US20060197158A1
公开(公告)日：2006-09-07
申请号：US11380602
申请日：2006-04-27
申请人： Jeffrey Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory Howard
发明人： Jeffrey Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory Howard
IPC分类号： H01L27/12
CPC分类号： H01L29/66659 , H01L21/26506 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/823892 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/36 , H01L29/78612 , H01L29/78654
摘要： The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
摘要翻译：本发明是一种用于在MOS晶体管结构中形成超陡掺杂分布的方法。该方法包括在栅极电介质（50）下面形成含碳层（110），并在MOS晶体管的源极和漏极区域（80）形成。含碳层（110）将防止掺杂剂扩散到栅极电介质层（50）正下方的区域（40）中。

7. 发明授权

US08703568B2 Advanced CMOS using super steep retrograde wells 有权
标题翻译：先进的CMOS使用超级陡逆流井
公开(公告)号：US08703568B2
公开(公告)日：2014-04-22
申请号：US13359125
申请日：2012-01-26
申请人： Jeffrey A. Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory E. Howard
发明人： Jeffrey A. Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory E. Howard
IPC分类号： H01L21/336
CPC分类号： H01L29/66659 , H01L21/26506 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/823892 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/36 , H01L29/78612 , H01L29/78654
摘要： The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
摘要翻译：本发明是一种用于在MOS晶体管结构中形成超陡掺杂分布的方法。该方法包括在栅极电介质（50）下面形成含碳层（110），并在MOS晶体管的源极和漏极区域（80）形成。含碳层（110）将防止掺杂剂扩散到栅极电介质层（50）正下方的区域（40）中。

8. 发明授权

US08648432B2 Fully embedded micromechanical device, system on chip and method for manufacturing the same 有权
标题翻译：全嵌入式微机械装置，片上系统及其制造方法
公开(公告)号：US08648432B2
公开(公告)日：2014-02-11
申请号：US13305536
申请日：2011-11-28
申请人： Alfred Haeusler
发明人： Alfred Haeusler
IPC分类号： H01L29/84 , H01L21/302
CPC分类号： B81C1/00246 , B81C2203/0735
摘要： A fully embedded micromechanical device and a system on chip is manufactured on an SOI-substrate. The micromechanical device comprises a moveable component having a laterally extending upper and lower surface and vertical side surfaces. The upper surface is adjacent to an upper gap which laterally extends over at least a part of the upper surface and results from the removal of a shallow trench insulation material. The lower surface is adjacent to a lower gap which laterally extends over at least a part of the lower surface and results from the removal of the buried silicon oxide layer. The side surfaces of the movable component are adjacent to side gaps which surround at least a part of the vertical side surfaces of the moveable component and result from the removal of a deep trench insulation material.
摘要翻译：在SOI衬底上制造完全嵌入的微机械器件和片上系统。微机械装置包括具有横向延伸的上表面和下表面以及垂直侧表面的可移动部件。上表面与在上表面的至少一部分上横向延伸的上间隙相邻，并且由去除浅沟槽绝缘材料导致。下表面与下部间隙相邻，该下部间隙在下表面的至少一部分上横向延伸，并且由去除掩埋的氧化硅层导致。可移动部件的侧表面邻近包围可移动部件的垂直侧表面的至少一部分的侧间隙，并且是由去除深沟槽绝缘材料导致的。

9. 发明申请

US20120205775A1 METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE 审中-公开
标题翻译：制造电子设备的方法
公开(公告)号：US20120205775A1
公开(公告)日：2012-08-16
申请号：US13372926
申请日：2012-02-14
申请人： Alfred HAEUSLER , Wolfgang SCHWARTZ
发明人： Alfred HAEUSLER , Wolfgang SCHWARTZ
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/8249 , H01L21/76229 , H01L21/76283 , H01L21/823878 , H01L21/84
摘要： The invention relates to a method for manufacturing a semiconductor device. Accordingly, the trench processing sequence is changed and stress absorbing layers are applied. A shallow trench structure is etched. A deep trench structure is etched. A liner oxide is applied in the deep and shallow trench structure. An amorphous polysilicon liner is deposited on top of the liner oxide. A nitride liner is applied on top of the amorphous polysilicon liner, and the deep and shallow trenches are filled with oxide.
摘要翻译：本发明涉及半导体器件的制造方法。因此，改变沟槽处理顺序并施加应力吸收层。蚀刻浅沟槽结构。蚀刻深沟槽结构。在深浅沟槽结构中应用衬里氧化物。无定形多晶硅衬垫沉积在衬垫氧化物的顶部。将氮化物衬垫施加在非晶多晶硅衬垫的顶部，并且深和浅沟槽填充有氧化物。

10. 发明授权

US07118981B2 Method of fabricating an integrated silicon-germanium heterobipolar transistor and an integrated silicon-germanium heterobipolar transistor 有权
标题翻译：制造集成硅 - 锗异双极晶体管和集成硅 - 锗异双极晶体管的方法
公开(公告)号：US07118981B2
公开(公告)日：2006-10-10
申请号：US10824745
申请日：2004-04-15
申请人： Alfred Haeusler , Philipp Steinmann , Scott Balster , Badih El-Kareh
发明人： Alfred Haeusler , Philipp Steinmann , Scott Balster , Badih El-Kareh
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/7378
摘要： In a method of fabricating an integrated silicon-germanium heterobipolar transistor a silicon dioxide layer arranged between a silicon-germanium base layer and a silicon emitter layer is formed by means of Rapid Thermal Processing (RTP) to ensure enhanced component properties of the integrated silicon-germanium heterobipolar transistor.
摘要翻译：在制造集成硅 - 锗异质晶体管的方法中，通过快速热处理（RTP）形成布置在硅 - 锗基底层和硅发射极层之间的二氧化硅层，以确保集成硅 - 锗异双极晶体管。

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