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1. 发明申请

US20070173067A1 OPENING HARD MASK AND SOI SUBSTRATE IN SINGLE PROCESS CHAMBER 失效
标题翻译：在单个过程室中打开硬掩模和SOI衬底
公开(公告)号：US20070173067A1
公开(公告)日：2007-07-26
申请号：US11275707
申请日：2006-01-25
申请人： Scott Allen , Kangguo Cheng , Xi Li , Kevin Winstel
发明人： Scott Allen , Kangguo Cheng , Xi Li , Kevin Winstel
IPC分类号： H01L21/302
CPC分类号： H01L21/3081 , H01L21/31116
摘要： Methods for opening a hard mask and a silicon-on-insulator substrate in a single process chamber are disclosed. In one embodiment, the method includes patterning a photoresist over a stack including an anti-reflective coating (ARC) layer, a silicon dioxide (SiO2) based hard mask layer, a silicon nitride pad layer, a silicon dioxide (SiO2) pad layer and the SOI substrate, wherein the SOI substrate includes a silicon-on-insulator layer and a buried silicon dioxide (SiO2) layer; and in a single process chamber: opening the ARC layer; etching the silicon dioxide (SiO2) based hard mask layer; etching the silicon nitride pad layer; etching the silicon dioxide (SiO2) pad layer; and etching the SOI substrate. Etching all layers in a single chamber reduces the turn-around-time, lowers the process cost, facilitates process control and/or improve a trench profile.
摘要翻译：公开了在单个处理室中打开硬掩模和绝缘体上硅衬底的方法。在一个实施例中，该方法包括在包括抗反射涂层（ARC）层，基于二氧化硅（SiO 2）的硬掩模层，氮化硅垫层，二氧化硅（SiO 2）衬垫层和SOI衬底，其中所述SOI衬底包括绝缘体上硅层和掩埋二氧化硅（SiO 2）层; 并在单个处理室中：打开ARC层; 蚀刻基于二氧化硅（SiO 2）的硬掩模层; 蚀刻氮化硅焊盘层; 蚀刻二氧化硅（SiO 2）垫层; 并蚀刻SOI衬底。在单个室中蚀刻所有层减少了周转时间，降低了工艺成本，便于工艺控制和/或改善沟槽轮廓。

2. 发明授权

US07833872B2 Uniform recess of a material in a trench independent of incoming topography 有权
标题翻译：均匀凹陷的沟槽材料，独立于进入的地形
公开(公告)号：US07833872B2
公开(公告)日：2010-11-16
申请号：US11931112
申请日：2007-10-31
申请人： Kangguo Cheng , Johnathan E. Faltermeier , Xi Li
发明人： Kangguo Cheng , Johnathan E. Faltermeier , Xi Li
IPC分类号： H01L21/20 , H01L21/311
CPC分类号： H01L21/32137 , H01L21/32115 , H01L29/66181
摘要： Columnar elements which extend to varying heights above a major surface of a substrate, e.g., polysilicon studs within trenches in the substrate, are recessed to a uniform depth below the major surface. The columnar elements are etched selectively with respect to a material exposed at the surface in an at least partly lateral direction so that the columnar elements are recessed to a uniform depth below the major surface at walls of the trenches.
摘要翻译：在衬底的主表面上方延伸到不同高度的柱状元件（例如衬底中的沟槽内的多晶硅柱）凹陷到主表面下方的均匀深度。相对于在表面上以至少部分横向方向暴露的材料，柱状元件被选择性地蚀刻，使得柱状元件在沟槽的壁处凹陷到主表面下方的均匀深度。

3. 发明授权

US07749835B2 Trench memory with self-aligned strap formed by self-limiting process 失效
标题翻译：沟槽记忆带自行排列的带子，由自限制过程形成
公开(公告)号：US07749835B2
公开(公告)日：2010-07-06
申请号：US12048263
申请日：2008-03-14
申请人： Xi Li , Kangguo Cheng , Johnathan Faltermeier
发明人： Xi Li , Kangguo Cheng , Johnathan Faltermeier
IPC分类号： H01L21/84 , H01L21/8242
CPC分类号： H01L29/945 , H01L21/32137 , H01L21/76232 , H01L21/84 , H01L27/1087 , H01L29/66181
摘要： A semiconductor structure is described. The structure includes a trench opening formed in a semiconductor substrate having a semiconductor-on-insulator (SOI) layer and a buried insulating (BOX) layer; and a filling material formed in the trench opening, the filling material forming a “V” shape within the trench memory cell, wherein the “V” shape includes a top portion substantially adjacent to a top surface of the BOX layer. A method of fabricating the semiconductor structure is also described. The method includes forming a trench opening in a semiconductor substrate having an SOI layer and a BOX layer; laterally etching the BOX layer such that a portion of the trench opening associated with the BOX layer is substantially greater than a portion of the trench opening associated with the SOI layer; filling the trench opening with a filling material; and recessing the filling material.
摘要翻译：描述半导体结构。该结构包括形成在具有绝缘体上半导体（SOI）层和掩埋绝缘（BOX）层的半导体衬底中的沟槽开口; 以及形成在所述沟槽开口中的填充材料，所述填充材料在所述沟槽存储单元内形成“V”形，其中所述“V”形包括基本上邻近所述BOX层的顶表面的顶部。还描述了制造半导体结构的方法。该方法包括在具有SOI层和BOX层的半导体衬底中形成沟槽开口; 横向蚀刻BOX层，使得与BOX层相关联的沟槽开口的一部分基本上大于与SOI层相关联的沟槽开口的一部分; 用填充材料填充沟槽开口; 并使填充材料凹陷。

4. 发明授权

US07560387B2 Opening hard mask and SOI substrate in single process chamber 失效
标题翻译：在单处理室中打开硬掩模和SOI衬底
公开(公告)号：US07560387B2
公开(公告)日：2009-07-14
申请号：US11275707
申请日：2006-01-25
申请人： Scott D. Allen , Kangguo Cheng , Xi Li , Kevin R. Winstel
发明人： Scott D. Allen , Kangguo Cheng , Xi Li , Kevin R. Winstel
IPC分类号： H01L21/311
CPC分类号： H01L21/3081 , H01L21/31116
摘要： Methods for opening a hard mask and a silicon-on-insulator substrate in a single process chamber are disclosed. In one embodiment, the method includes patterning a photoresist over a stack including an anti-reflective coating (ARC) layer, a silicon dioxide (SiO2) based hard mask layer, a silicon nitride pad layer, a silicon dioxide (SiO2) pad layer and the SOI substrate, wherein the SOI substrate includes a silicon-on-insulator layer and a buried silicon dioxide (SiO2) layer; and in a single process chamber: opening the ARC layer; etching the silicon dioxide (SiO2) based hard mask layer; etching the silicon nitride pad layer; etching the silicon dioxide (SiO2) pad layer; and etching the SOI substrate. Etching all layers in a single chamber reduces the turn-around-time, lowers the process cost, facilitates process control and/or improve a trench profile.
摘要翻译：公开了在单个处理室中打开硬掩模和绝缘体上硅衬底的方法。在一个实施例中，该方法包括在包括抗反射涂层（ARC）层，基于二氧化硅（SiO 2）的硬掩模层，氮化硅衬垫层，二氧化硅（SiO 2）衬垫层和叠层 SOI衬底，其中所述SOI衬底包括绝缘体上硅层和掩埋二氧化硅（SiO 2）层; 并在单个处理室中：打开ARC层; 蚀刻基于二氧化硅（SiO 2）的硬掩模层; 蚀刻氮化硅焊盘层; 蚀刻二氧化硅（SiO 2）垫层; 并蚀刻SOI衬底。在单个室中蚀刻所有层减少了周转时间，降低了工艺成本，便于工艺控制和/或改善沟槽轮廓。

5. 发明申请

US20090108306A1 UNIFORM RECESS OF A MATERIAL IN A TRENCH INDEPENDENT OF INCOMING TOPOGRAPHY 有权
标题翻译：在独立的地理位置上，材料的均匀收敛
公开(公告)号：US20090108306A1
公开(公告)日：2009-04-30
申请号：US11931112
申请日：2007-10-31
申请人： Kangguo Cheng , Johnathan E. Faltermeier , Xi Li
发明人： Kangguo Cheng , Johnathan E. Faltermeier , Xi Li
IPC分类号： H01L29/94 , H01L21/311
CPC分类号： H01L21/32137 , H01L21/32115 , H01L29/66181
摘要： Columnar elements which extend to varying heights above a major surface of a substrate, e.g., polysilicon studs within trenches in the substrate, are recessed to a uniform depth below the major surface. The columnar elements are etched selectively with respect to a material exposed at the surface in an at least partly lateral direction so that the columnar elements are recessed to a uniform depth below the major surface at walls of the trenches.
摘要翻译：在衬底的主表面上方延伸到不同高度的柱状元件（例如衬底中的沟槽内的多晶硅柱）凹陷到主表面下方的均匀深度。相对于在表面上以至少部分横向方向暴露的材料选择性地蚀刻柱状元件，使得柱状元件在沟槽的壁处凹陷到主表面下方的均匀深度。

6. 发明授权

US07494891B2 Trench capacitor with void-free conductor fill 有权
标题翻译：沟槽电容器，无空隙导体填充
公开(公告)号：US07494891B2
公开(公告)日：2009-02-24
申请号：US11533928
申请日：2006-09-21
申请人： Kangguo Cheng , Johnathan E. Faltermeier , Xi Li
发明人： Kangguo Cheng , Johnathan E. Faltermeier , Xi Li
IPC分类号： H01L21/20
CPC分类号： H01L29/945 , H01L29/66181
摘要： A method forms a node dielectric in a bottle shaped trench and then deposits an initial conductor within the lower portion of the bottle shaped trench, such that a void is formed within the initial conductor. Next, the method forms an insulating collar in the upper portion of the bottle shaped trench above the initial conductor. Then, the method simultaneously etches a center portion of the insulating collar and the initial conductor until the void is exposed. This etching process forms a center opening within the insulating collar and the initial conductor. Additional conductor is deposited in the center opening such that the additional conductor is formed at least to the level of the surface of the substrate.
摘要翻译：一种方法在瓶形沟槽中形成节点电介质，然后将初始导体沉积在瓶形沟槽的下部，使得在初始导体内形成空隙。接下来，该方法在初始导体上方的瓶形沟槽的上部形成绝缘套环。然后，该方法同时蚀刻绝缘套环的中心部分和初始导体，直到暴露出空隙。该蚀刻工艺在绝缘环和初始导体内形成中心开口。附加导体沉积在中心开口中，使得附加导体至少形成至基底表面的水平。

7. 发明申请

US20080248625A1 METHODS FOR ENHANCING TRENCH CAPACITANCE AND TRENCH CAPACITOR 审中-公开
公开(公告)号：US20080248625A1
公开(公告)日：2008-10-09
申请号：US12120535
申请日：2008-05-14
申请人： Kangguo Cheng , David M. Dobuzinsky , Xi Li
发明人： Kangguo Cheng , David M. Dobuzinsky , Xi Li
IPC分类号： H01L21/441
CPC分类号： H01L29/945 , H01L28/84 , H01L29/66181
摘要： Methods for enhancing trench capacitance and a trench capacitor so formed are disclosed. In one embodiment a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall; depositing a node dielectric; and filling the trench with a conductor. The rough sidewall enhances trench capacitance without increasing processing complexity or cost.

8. 发明申请

US20080246068A1 TRENCH CAPACITORS AND MEMORY CELLS USING TRENCH CAPACITORS 有权
标题翻译：使用TRENCH电容器的TRENCH电容器和存储器电池
公开(公告)号：US20080246068A1
公开(公告)日：2008-10-09
申请号：US12138536
申请日：2008-06-13
申请人： Kangguo Cheng , Xi Li
发明人： Kangguo Cheng , Xi Li
IPC分类号： H01L29/94
CPC分类号： H01L29/66181 , H01L27/10829 , H01L27/1087
摘要： A trench structure, a method of forming the trench structure, a memory cell using the trench structure and a method of forming a memory cell using the trench structure. The trench structure includes: a substrate; a trench having contiguous upper, middle and lower regions, the trench extending from a top surface of said substrate into said substrate; the upper region of the trench having a vertical sidewall profile; and the middle region of the trench having a tapered sidewall profile.
摘要翻译：沟槽结构，形成沟槽结构的方法，使用沟槽结构的存储单元以及使用沟槽结构形成存储单元的方法。沟槽结构包括：衬底; 具有连续的上，中和下区域的沟槽，所述沟槽从所述衬底的顶表面延伸到所述衬底中; 所述沟槽的上部区域具有垂直侧壁轮廓; 并且沟槽的中间区域具有锥形侧壁轮廓。

9. 发明申请

US20070172965A1 NON-DESTRUCTIVE TRENCH VOLUME DETERMINATION AND TRENCH CAPACITANCE PROJECTION 审中-公开
标题翻译：非破坏性量子体积测定和趋势电容投影
公开(公告)号：US20070172965A1
公开(公告)日：2007-07-26
申请号：US11275663
申请日：2006-01-23
申请人： Kangguo Cheng , Xi Li
发明人： Kangguo Cheng , Xi Li
IPC分类号： H01L21/66 , H01L21/76
CPC分类号： H01L21/76224 , H01L22/12
摘要： Methods of determining trench volume are disclosed. In one embodiment, the method includes providing a semiconductor substrate with at least one trench in a trench area; filling each trench with a filling material; measuring a step height between the trench area and a trench free area; and determining the trench volume based on the step height. The embodiments provide a simple, nondestructive, cost-effective, highly scalable and reliable trench volume measurement. The step height can also be used as part of a method to project trench capacitance where the trench will be used for a trench capacitor.
摘要翻译：公开了确定沟槽体积的方法。在一个实施例中，该方法包括在沟槽区域中提供具有至少一个沟槽的半导体衬底; 用填充材料填充每个沟槽; 测量沟槽区域和无沟槽区域之间的台阶高度; 以及基于所述台阶高度确定所述沟槽体积。这些实施例提供了简单的，非破坏性的，成本有效的，高度可扩展的和可靠的沟槽体积测量。步长也可用作投影沟槽电容的方法的一部分，其中沟槽将用于沟槽电容器。

10. 发明授权

US08008160B2 Method and structure for forming trench DRAM with asymmetric strap 有权
标题翻译：用不对称带形成沟槽DRAM的方法和结构
公开(公告)号：US08008160B2
公开(公告)日：2011-08-30
申请号：US12017154
申请日：2008-01-21
申请人： Kangguo Cheng , Xi Li , Richard Wise
发明人： Kangguo Cheng , Xi Li , Richard Wise
IPC分类号： H01L21/20
CPC分类号： H01L21/26586 , H01L27/10867 , H01L29/7833
摘要： A method of forming a trench device structure having a single-side buried strap is provided. The method includes forming a deep trench in a semiconductor substrate, said deep trench having a first side portion and a second side portion; depositing a node dielectric on said deep trench, wherein said node dielectric covers said first side portion and said second side portion; depositing a first conductive layer over said node dielectric; performing an ion implantation or ion bombardment at an angle into a portion of said node dielectric, thereby removing said portion of said node dielectric from said first side portion of said deep trench; and depositing a second conductive layer over said first conductive layer, wherein said second conductive layer outdiffuses into a portion of said semiconductor substrate. A trench device structure having a single-side buried strap is also provided. The device structure includes a semiconductor substrate having a deep trench therein; and a first conductive layer and a second conductive layer sequentially disposed on said deep trench, wherein said second conductive layer outdiffuses into a portion of said semiconductor substrate.
摘要翻译：提供了一种形成具有单面埋入带的沟槽器件结构的方法。该方法包括在半导体衬底中形成深沟槽，所述深沟槽具有第一侧部分和第二侧部分; 在所述深沟槽上沉积节点电介质，其中所述节点电介质覆盖所述第一侧部分和所述第二侧部分; 在所述节点电介质上沉积第一导电层; 以一定角度进行离子注入或离子轰击到所述节点电介质的一部分中，从而从所述深沟槽的所述第一侧部分移除所述节点电介质的所述部分; 以及在所述第一导电层上沉积第二导电层，其中所述第二导电层超出所述半导体衬底的一部分。还提供了具有单面埋置带的沟槽器件结构。该器件结构包括其中具有深沟槽的半导体衬底; 以及顺序地设置在所述深沟槽上的第一导电层和第二导电层，其中所述第二导电层向外延伸到所述半导体衬底的一部分中。

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