专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07833872B2 Uniform recess of a material in a trench independent of incoming topography 有权
标题翻译：均匀凹陷的沟槽材料，独立于进入的地形
公开(公告)号：US07833872B2
公开(公告)日：2010-11-16
申请号：US11931112
申请日：2007-10-31
申请人： Kangguo Cheng , Johnathan E. Faltermeier , Xi Li
发明人： Kangguo Cheng , Johnathan E. Faltermeier , Xi Li
IPC分类号： H01L21/20 , H01L21/311
CPC分类号： H01L21/32137 , H01L21/32115 , H01L29/66181
摘要： Columnar elements which extend to varying heights above a major surface of a substrate, e.g., polysilicon studs within trenches in the substrate, are recessed to a uniform depth below the major surface. The columnar elements are etched selectively with respect to a material exposed at the surface in an at least partly lateral direction so that the columnar elements are recessed to a uniform depth below the major surface at walls of the trenches.
摘要翻译：在衬底的主表面上方延伸到不同高度的柱状元件（例如衬底中的沟槽内的多晶硅柱）凹陷到主表面下方的均匀深度。相对于在表面上以至少部分横向方向暴露的材料，柱状元件被选择性地蚀刻，使得柱状元件在沟槽的壁处凹陷到主表面下方的均匀深度。

2. 发明申请

US20090108306A1 UNIFORM RECESS OF A MATERIAL IN A TRENCH INDEPENDENT OF INCOMING TOPOGRAPHY 有权
标题翻译：在独立的地理位置上，材料的均匀收敛
公开(公告)号：US20090108306A1
公开(公告)日：2009-04-30
申请号：US11931112
申请日：2007-10-31
申请人： Kangguo Cheng , Johnathan E. Faltermeier , Xi Li
发明人： Kangguo Cheng , Johnathan E. Faltermeier , Xi Li
IPC分类号： H01L29/94 , H01L21/311
CPC分类号： H01L21/32137 , H01L21/32115 , H01L29/66181
摘要： Columnar elements which extend to varying heights above a major surface of a substrate, e.g., polysilicon studs within trenches in the substrate, are recessed to a uniform depth below the major surface. The columnar elements are etched selectively with respect to a material exposed at the surface in an at least partly lateral direction so that the columnar elements are recessed to a uniform depth below the major surface at walls of the trenches.
摘要翻译：在衬底的主表面上方延伸到不同高度的柱状元件（例如衬底中的沟槽内的多晶硅柱）凹陷到主表面下方的均匀深度。相对于在表面上以至少部分横向方向暴露的材料选择性地蚀刻柱状元件，使得柱状元件在沟槽的壁处凹陷到主表面下方的均匀深度。

3. 发明授权

US07494891B2 Trench capacitor with void-free conductor fill 有权
标题翻译：沟槽电容器，无空隙导体填充
公开(公告)号：US07494891B2
公开(公告)日：2009-02-24
申请号：US11533928
申请日：2006-09-21
申请人： Kangguo Cheng , Johnathan E. Faltermeier , Xi Li
发明人： Kangguo Cheng , Johnathan E. Faltermeier , Xi Li
IPC分类号： H01L21/20
CPC分类号： H01L29/945 , H01L29/66181
摘要： A method forms a node dielectric in a bottle shaped trench and then deposits an initial conductor within the lower portion of the bottle shaped trench, such that a void is formed within the initial conductor. Next, the method forms an insulating collar in the upper portion of the bottle shaped trench above the initial conductor. Then, the method simultaneously etches a center portion of the insulating collar and the initial conductor until the void is exposed. This etching process forms a center opening within the insulating collar and the initial conductor. Additional conductor is deposited in the center opening such that the additional conductor is formed at least to the level of the surface of the substrate.
摘要翻译：一种方法在瓶形沟槽中形成节点电介质，然后将初始导体沉积在瓶形沟槽的下部，使得在初始导体内形成空隙。接下来，该方法在初始导体上方的瓶形沟槽的上部形成绝缘套环。然后，该方法同时蚀刻绝缘套环的中心部分和初始导体，直到暴露出空隙。该蚀刻工艺在绝缘环和初始导体内形成中心开口。附加导体沉积在中心开口中，使得附加导体至少形成至基底表面的水平。

4. 发明申请

US20080076230A1 Trench Capacitor with Void-Free Conductor Fill 有权
标题翻译：无空隙导体填充的沟槽电容器
公开(公告)号：US20080076230A1
公开(公告)日：2008-03-27
申请号：US11533928
申请日：2006-09-21
申请人： Kangguo Cheng , Johnathan E. Faltermeier , Xi Li
发明人： Kangguo Cheng , Johnathan E. Faltermeier , Xi Li
IPC分类号： H01L21/20
CPC分类号： H01L29/945 , H01L29/66181
摘要： A method forms a node dielectric in a bottle shaped trench and then deposits an initial conductor within the lower portion of the bottle shaped trench, such that a void is formed within the initial conductor. Next, the method forms an insulating collar in the upper portion of the bottle shaped trench above the initial conductor. Then, the method simultaneously etches a center portion of the insulating collar and the initial conductor until the void is exposed. This etching process forms a center opening within the insulating collar and the initial conductor. Additional conductor is deposited in the center opening such that the additional conductor is formed at least to the level of the surface of the substrate.
摘要翻译：一种方法在瓶形沟槽中形成节点电介质，然后将初始导体沉积在瓶形沟槽的下部，使得在初始导体内形成空隙。接下来，该方法在初始导体上方的瓶形沟槽的上部形成绝缘套环。然后，该方法同时蚀刻绝缘套环的中心部分和初始导体，直到暴露出空隙。该蚀刻工艺在绝缘环和初始导体内形成中心开口。附加导体沉积在中心开口中，使得附加导体至少形成至基底表面的水平。

5. 发明授权

US07923815B2 DRAM having deep trench capacitors with lightly doped buried plates 有权
标题翻译： DRAM具有具有轻掺杂掩埋板的深沟槽电容器
公开(公告)号：US07923815B2
公开(公告)日：2011-04-12
申请号：US11969986
申请日：2008-01-07
申请人： Geng Wang , Kangguo Cheng , Johnathan E. Faltermeier , Paul C. Parries
发明人： Geng Wang , Kangguo Cheng , Johnathan E. Faltermeier , Paul C. Parries
IPC分类号： H01L21/02
CPC分类号： H01L29/66181 , G11C11/404 , H01L27/0805 , H01L27/10861
摘要： By controlling buried plate doping level and bias condition, different capacitances can be obtained from capacitors on the same chip with the same layout and deep trench process. The capacitors may be storage capacitors of DRAM/eDRAM cells. The doping concentration may be less than 3E19cm−3, a voltage difference between the biases of the buried electrodes may be at least 0.5V, and a capacitance of one capacitor may be at least 1.2 times, such as 2.0 times the capacitance of another capacitor.
摘要翻译：通过控制掩埋板掺杂水平和偏置条件，可以在相同芯片上的电容器中获得不同的电容，具有相同的布局和深沟槽工艺。电容器可以是DRAM / eDRAM单元的存储电容器。掺杂浓度可以小于3E19cm-3，掩埋电极的偏压之间的电压差可以至少为0.5V，并且一个电容器的电容可以是至少1.2倍，例如另一个电容器的电容的2.0倍。

6. 发明申请

US20100207245A1 HIGHLY SCALABLE TRENCH CAPACITOR 有权
标题翻译：高可伸缩电容器
公开(公告)号：US20100207245A1
公开(公告)日：2010-08-19
申请号：US12689501
申请日：2010-01-19
申请人： Kangguo Cheng , Anne Marie Ebert , Johnathan E. Faltermeier
发明人： Kangguo Cheng , Anne Marie Ebert , Johnathan E. Faltermeier
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/40 , H01L21/7682 , H01L21/76831 , H01L27/10861 , H01L29/66181
摘要： An improved trench structure, and method for its fabrication are disclosed. Embodiments of the present invention provide a trench in which the collar portion has an air gap instead of a solid oxide collar. The air gap provides a lower dielectric constant. Embodiments of the present invention can therefore be used to make higher-performance devices (due to reduced parasitic leakage), or smaller devices, due to the ability to use a thinner collar to achieve the same performance as a thicker collar comprised only of oxide (with no air gap). Alternatively, a design choice can be made to achieve a combination of improved performance and reduced size, depending on the application.
摘要翻译：公开了一种改进的沟槽结构及其制造方法。本发明的实施例提供了一种沟槽，其中套环部分具有气隙而不是固体氧化物套环。气隙提供较低的介电常数。因此，本发明的实施例可以用于制造更高性能的装置（由于减小的寄生泄漏）或更小的装置，这是由于能够使用更薄的套环来获得与仅由氧化物构成的更厚的套圈相同的性能没有气隙）。或者，根据应用，可以进行设计选择以实现改进的性能和减小的尺寸的组合。

7. 发明授权

US08288218B2 Device structure, layout and fabrication method for uniaxially strained transistors 有权
标题翻译：单轴应变晶体管的器件结构，布局和制造方法
公开(公告)号：US08288218B2
公开(公告)日：2012-10-16
申请号：US12689346
申请日：2010-01-19
申请人： Stephen W. Bedell , Huiming Bu , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz , Devendra K. Sadana , Chun-Chen Yeh
发明人： Stephen W. Bedell , Huiming Bu , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz , Devendra K. Sadana , Chun-Chen Yeh
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L27/0207 , H01L29/6656 , H01L29/66628 , H01L29/78 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices.
摘要翻译：一种用于制造半导体器件的半导体器件和方法包括提供具有第一应变轴的应变半导体层，在应变半导体层的表面内形成有源区，其中有源区具有沿应变轴的纵向轴线并形成栅极结构在活跃地区。在应变半导体层的表面上方和与栅极结构相邻的有源区上形成升高的源/漏区，以形成晶体管器件。

8. 发明申请

US20110108920A1 HIGH-K/METAL GATE CMOS FINFET WITH IMPROVED PFET THRESHOLD VOLTAGE 有权
标题翻译：具有改进的PFET阈值电压的高K /金属栅极CMOS FINFET
公开(公告)号：US20110108920A1
公开(公告)日：2011-05-12
申请号：US12614906
申请日：2009-11-09
申请人： VEERARAGHAVAN S. BASKER , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz
发明人： VEERARAGHAVAN S. BASKER , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz
IPC分类号： H01L29/49 , H01L21/84
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/1054 , H01L29/66795
摘要： A device and method for fabrication of fin devices for an integrated circuit includes forming fin structures in a semiconductor material of a semiconductor device wherein the semiconductor material is exposed on sidewalls of the fin structures. A donor material is epitaxially deposited on the exposed sidewalls of the fin structures. A condensation process is applied to move the donor material through the sidewalls into the semiconductor material such that accommodation of the donor material causes a strain in the semiconductor material of the fin structures. The donor material is removed, and a field effect transistor is formed from the fin structure.
摘要翻译：用于制造用于集成电路的鳍片器件的器件和方法包括在半导体器件的半导体材料中形成鳍结构，其中半导体材料暴露在鳍结构的侧壁上。施主材料外延地沉积在鳍结构的暴露的侧壁上。施加冷凝过程以将供体材料通过侧壁移动到半导体材料中，使得供体材料的调节在翅片结构的半导体材料中引起应变。施主材料被去除，并且从翅片结构形成场效应晶体管。

9. 发明申请

US20070267671A1 TRENCH CAPACITOR HAVING LATERAL EXTENSIONS IN ONLY ONE DIRECTION AND RELATED METHODS 审中-公开
标题翻译：具有仅一个方向的横向延伸的TRENCH电容器及相关方法
公开(公告)号：US20070267671A1
公开(公告)日：2007-11-22
申请号：US11383861
申请日：2006-05-17
申请人： Kangguo Cheng , Lisa F. Edge , Johnathan E. Faltermeier , Paul C. Parries , William C. Wille
发明人： Kangguo Cheng , Lisa F. Edge , Johnathan E. Faltermeier , Paul C. Parries , William C. Wille
IPC分类号： H01L29/94
CPC分类号： H01L29/945 , H01L29/66181
摘要： A trench capacitor and related methods are disclosed including a trench having lateral extensions extending in only one direction from the trench filled with a capacitor material. In one embodiment, the trench capacitor includes a trench within a substrate, and at least one lateral extension extending from the trench in only one direction, wherein the trench and each lateral extension are filled with a capacitor material. The lateral extensions increase surface area for the trench capacitor, but do not take up as much space as conventional structures.
摘要翻译：公开了一种沟槽电容器和相关方法，其包括具有从填充有电容器材料的沟槽的仅一个方向延伸的侧向延伸的沟槽。在一个实施例中，沟槽电容器包括在衬底内的沟槽，以及至少一个沿着一个方向从沟槽延伸的横向延伸部，其中沟槽和每个横向延伸部充满电容器材料。横向延伸增加了沟槽电容器的表面积，但不占用与常规结构相同的空间。

10. 发明授权

US07084449B2 Microelectronic element having trench capacitors with different capacitance values 失效
标题翻译：具有不同电容值的沟槽电容器的微电子元件
公开(公告)号：US07084449B2
公开(公告)日：2006-08-01
申请号：US10710146
申请日：2004-06-22
申请人： Kangguo Cheng , Johnathan E. Faltermeier , David R. Hanson , Carl J. Radens
发明人： Kangguo Cheng , Johnathan E. Faltermeier , David R. Hanson , Carl J. Radens
IPC分类号： H01L27/108 , H01L29/00
CPC分类号： H01L29/66181 , H01L27/1087 , H01L27/10894 , H01L29/945
摘要： A microelectronic element is provided having a major surface, the microelectronic element including a first capacitor formed on a sidewall of a first trench, the first trench being elongated in a downwardly extending direction from the major surface. The microelectronic element further includes a second capacitor formed on a sidewall of a second trench, the second trench being elongated in a downwardly extending direction from the major surface, wherein a top of the first capacitor is disposed at a first depth from the major surface, and a top of the second capacitor is disposed at a second depth from the major surface.
摘要翻译：提供具有主表面的微电子元件，微电子元件包括形成在第一沟槽的侧壁上的第一电容器，第一沟槽从主表面沿向下延伸的方向伸长。微电子元件还包括形成在第二沟槽的侧壁上的第二电容器，第二沟槽从主表面沿向下延伸的方向伸长，其中第一电容器的顶部设置在距离主表面的第一深度处，并且第二电容器的顶部设置在距离主表面的第二深度处。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式