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1. 发明授权

US07560387B2 Opening hard mask and SOI substrate in single process chamber 失效
标题翻译：在单处理室中打开硬掩模和SOI衬底
公开(公告)号：US07560387B2
公开(公告)日：2009-07-14
申请号：US11275707
申请日：2006-01-25
申请人： Scott D. Allen , Kangguo Cheng , Xi Li , Kevin R. Winstel
发明人： Scott D. Allen , Kangguo Cheng , Xi Li , Kevin R. Winstel
IPC分类号： H01L21/311
CPC分类号： H01L21/3081 , H01L21/31116
摘要： Methods for opening a hard mask and a silicon-on-insulator substrate in a single process chamber are disclosed. In one embodiment, the method includes patterning a photoresist over a stack including an anti-reflective coating (ARC) layer, a silicon dioxide (SiO2) based hard mask layer, a silicon nitride pad layer, a silicon dioxide (SiO2) pad layer and the SOI substrate, wherein the SOI substrate includes a silicon-on-insulator layer and a buried silicon dioxide (SiO2) layer; and in a single process chamber: opening the ARC layer; etching the silicon dioxide (SiO2) based hard mask layer; etching the silicon nitride pad layer; etching the silicon dioxide (SiO2) pad layer; and etching the SOI substrate. Etching all layers in a single chamber reduces the turn-around-time, lowers the process cost, facilitates process control and/or improve a trench profile.
摘要翻译：公开了在单个处理室中打开硬掩模和绝缘体上硅衬底的方法。在一个实施例中，该方法包括在包括抗反射涂层（ARC）层，基于二氧化硅（SiO 2）的硬掩模层，氮化硅衬垫层，二氧化硅（SiO 2）衬垫层和叠层 SOI衬底，其中所述SOI衬底包括绝缘体上硅层和掩埋二氧化硅（SiO 2）层; 并在单个处理室中：打开ARC层; 蚀刻基于二氧化硅（SiO 2）的硬掩模层; 蚀刻氮化硅焊盘层; 蚀刻二氧化硅（SiO 2）垫层; 并蚀刻SOI衬底。在单个室中蚀刻所有层减少了周转时间，降低了工艺成本，便于工艺控制和/或改善沟槽轮廓。

2. 发明授权

US08198169B2 Deep trench capacitor in a SOI substrate having a laterally protruding buried strap 有权
标题翻译： SOI衬底中的深沟槽电容器具有横向突出的埋入带
公开(公告)号：US08198169B2
公开(公告)日：2012-06-12
申请号：US12974451
申请日：2010-12-21
申请人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
发明人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
IPC分类号： H01L21/425
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/1087
摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.
摘要翻译：深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。节点电介质和沟槽填充材料沉积到深沟槽中。掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。

3. 发明授权

US07888723B2 Deep trench capacitor in a SOI substrate having a laterally protruding buried strap 有权
标题翻译： SOI衬底中的深沟槽电容器具有横向突出的埋入带
公开(公告)号：US07888723B2
公开(公告)日：2011-02-15
申请号：US12016312
申请日：2008-01-18
申请人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
发明人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
IPC分类号： H01L29/94
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/1087
摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.
摘要翻译：深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。节点电介质和沟槽填充材料沉积到深沟槽中。掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。

4. 发明授权

US07575970B2 Deep trench capacitor through SOI substrate and methods of forming 有权
标题翻译：深沟槽电容器通过SOI衬底和成型方法
公开(公告)号：US07575970B2
公开(公告)日：2009-08-18
申请号：US11470809
申请日：2006-09-07
申请人： Herbert L. Ho , Kangguo Cheng , Yoichi Otani , Kevin R. Winstel
发明人： Herbert L. Ho , Kangguo Cheng , Yoichi Otani , Kevin R. Winstel
IPC分类号： H01L21/8242
CPC分类号： H01L29/66181 , H01L29/945
摘要： Methods of forming a deep trench capacitor through an SOI substrate, and a capacitor are disclosed. In one embodiment, a method includes forming a trench opening into the SOI substrate to the silicon substrate; depositing a sidewall spacer in the trench opening; etching to form the deep trench into the silicon substrate; forming a first electrode by implanting a dopant into the silicon substrate, whereby the sidewall spacer protects the BOX layer and the silicon layer; removing the sidewall spacer; depositing a node dielectric within the deep trench; and forming a second electrode by depositing a conductor in the deep trench. Implanting creates a substantially uniform depth doped region except at a portion adjacent to a lowermost portion of the deep trench, which may be substantially bulbous. The BOX layer is protected from undercutting by the sidewall spacer, and the implantation removes the need for out-diffusing dopant from silica glass.
摘要翻译：公开了通过SOI衬底形成深沟槽电容器的方法和电容器。在一个实施例中，一种方法包括在SOI衬底中形成到硅衬底的沟槽开口; 在沟槽开口中沉积侧壁间隔物; 蚀刻以形成深沟槽进入硅衬底; 通过将掺杂剂注入硅衬底中形成第一电极，由此侧壁间隔件保护BOX层和硅层; 去除侧壁间隔物; 在深沟槽内沉积节点电介质; 以及通过在所述深沟槽中沉积导体而形成第二电极。植入可产生基本上均匀的深度掺杂区域，除了与深沟槽的最下部分相邻的部分，其可以是基本上是球状的。保护BOX层免受侧壁间隔物的底切，并且注入消除了对来自石英玻璃的扩散掺杂剂的需要。

5. 发明申请

US20080064178A1 DEEP TRENCH CAPACITOR THROUGH SOI SUBSTRATE AND METHODS OF FORMING 有权
标题翻译：通过SOI衬底的深度电容器和形成方法
公开(公告)号：US20080064178A1
公开(公告)日：2008-03-13
申请号：US11470809
申请日：2006-09-07
申请人： Herbert L. Ho , Kangguo Cheng , Yoichi Otani , Kevin R. Winstel
发明人： Herbert L. Ho , Kangguo Cheng , Yoichi Otani , Kevin R. Winstel
IPC分类号： H01L21/20
CPC分类号： H01L29/66181 , H01L29/945
摘要： Methods of forming a deep trench capacitor through an SOI substrate, and a capacitor are disclosed. In one embodiment, a method includes forming a trench opening into the SOI substrate to the silicon substrate; depositing a sidewall spacer in the trench opening; etching to form the deep trench into the silicon substrate; forming a first electrode by implanting a dopant into the silicon substrate, whereby the sidewall spacer protects the BOX layer and the silicon layer; removing the sidewall spacer; depositing a node dielectric within the deep trench; and forming a second electrode by depositing a conductor in the deep trench. Implanting creates a substantially uniform depth doped region except at a portion adjacent to a lowermost portion of the deep trench, which may be substantially bulbous. The BOX layer is protected from undercutting by the sidewall spacer, and the implantation removes the need for out-diffusing dopant from silica glass.
摘要翻译：公开了通过SOI衬底形成深沟槽电容器的方法和电容器。在一个实施例中，一种方法包括在SOI衬底中形成到硅衬底的沟槽开口; 在沟槽开口中沉积侧壁间隔物; 蚀刻以形成深沟槽进入硅衬底; 通过将掺杂剂注入硅衬底中形成第一电极，由此侧壁间隔件保护BOX层和硅层; 去除侧壁间隔物; 在深沟槽内沉积节点电介质; 以及通过在所述深沟槽中沉积导体而形成第二电极。植入可产生基本上均匀的深度掺杂区域，除了与深沟槽的最下部分相邻的部分，其可以是基本上是球状的。保护BOX层免受侧壁间隔物的底切，并且注入消除了对来自石英玻璃的扩散掺杂剂的需要。

6. 发明申请

US20110092043A1 DEEP TRENCH CAPACITOR IN A SOI SUBSTRATE HAVING A LATERALLY PROTRUDING BURIED STRAP 有权
标题翻译：在具有横向延伸的带状纹的SOI衬底中的深度TRENCH电容器
公开(公告)号：US20110092043A1
公开(公告)日：2011-04-21
申请号：US12974451
申请日：2010-12-21
申请人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
发明人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
IPC分类号： H01L21/02
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/1087
摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.
摘要翻译：深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。节点电介质和沟槽填充材料沉积到深沟槽中。掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。

7. 发明申请

US20090184356A1 DEEP TRENCH CAPACITOR IN A SOI SUBSTRATE HAVING A LATERALLY PROTRUDING BURIED STRAP 有权
标题翻译：在具有横向延伸的带状纹的SOI衬底中的深度TRENCH电容器
公开(公告)号：US20090184356A1
公开(公告)日：2009-07-23
申请号：US12016312
申请日：2008-01-18
申请人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
发明人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
IPC分类号： H01L29/94 , H01L21/20
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/1087
摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.
摘要翻译：深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。节点电介质和沟槽填充材料沉积到深沟槽中。掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。

8. 发明授权

US08008160B2 Method and structure for forming trench DRAM with asymmetric strap 有权
标题翻译：用不对称带形成沟槽DRAM的方法和结构
公开(公告)号：US08008160B2
公开(公告)日：2011-08-30
申请号：US12017154
申请日：2008-01-21
申请人： Kangguo Cheng , Xi Li , Richard Wise
发明人： Kangguo Cheng , Xi Li , Richard Wise
IPC分类号： H01L21/20
CPC分类号： H01L21/26586 , H01L27/10867 , H01L29/7833
摘要： A method of forming a trench device structure having a single-side buried strap is provided. The method includes forming a deep trench in a semiconductor substrate, said deep trench having a first side portion and a second side portion; depositing a node dielectric on said deep trench, wherein said node dielectric covers said first side portion and said second side portion; depositing a first conductive layer over said node dielectric; performing an ion implantation or ion bombardment at an angle into a portion of said node dielectric, thereby removing said portion of said node dielectric from said first side portion of said deep trench; and depositing a second conductive layer over said first conductive layer, wherein said second conductive layer outdiffuses into a portion of said semiconductor substrate. A trench device structure having a single-side buried strap is also provided. The device structure includes a semiconductor substrate having a deep trench therein; and a first conductive layer and a second conductive layer sequentially disposed on said deep trench, wherein said second conductive layer outdiffuses into a portion of said semiconductor substrate.
摘要翻译：提供了一种形成具有单面埋入带的沟槽器件结构的方法。该方法包括在半导体衬底中形成深沟槽，所述深沟槽具有第一侧部分和第二侧部分; 在所述深沟槽上沉积节点电介质，其中所述节点电介质覆盖所述第一侧部分和所述第二侧部分; 在所述节点电介质上沉积第一导电层; 以一定角度进行离子注入或离子轰击到所述节点电介质的一部分中，从而从所述深沟槽的所述第一侧部分移除所述节点电介质的所述部分; 以及在所述第一导电层上沉积第二导电层，其中所述第二导电层超出所述半导体衬底的一部分。还提供了具有单面埋置带的沟槽器件结构。该器件结构包括其中具有深沟槽的半导体衬底; 以及顺序地设置在所述深沟槽上的第一导电层和第二导电层，其中所述第二导电层向外延伸到所述半导体衬底的一部分中。

9. 发明授权

US07892928B2 Method of forming asymmetric spacers and methods of fabricating semiconductor device using asymmetric spacers 有权
标题翻译：形成不对称间隔物的方法和使用不对称间隔物制造半导体器件的方法
公开(公告)号：US07892928B2
公开(公告)日：2011-02-22
申请号：US11690258
申请日：2007-03-23
申请人： Kangguo Cheng , Xi Li , Richard Stephen Wise
发明人： Kangguo Cheng , Xi Li , Richard Stephen Wise
IPC分类号： H01L21/336
CPC分类号： H01L21/67069 , H01J37/32733 , H01J2237/20207 , H01L21/3086 , H01L21/31116 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/66659 , H01L29/66772 , H01L29/7835 , H01L29/7848 , H01L29/78654
摘要： A method of fabricating asymmetrical spacers, structures fabricated using asymmetrical spacers and an apparatus for fabricating asymmetrical spacers. The method includes: forming on a substrate, a structure having a top surface and opposite first and second sidewalls and having a longitudinal axis parallel to the sidewalls; forming a conformal layer on the top surface of the substrate, the top surface of the structure and the sidewalls of the structure; tilting the substrate about a longitudinal axis relative to a flux of reactive ions, the flux of reactive ions striking the conformal layer at acute angle; and exposing the conformal layer to the flux of reactive ions until the conformal layer is removed from the top surface of the structure and the top surface of the substrate leaving a first spacer on the first sidewall and a second spacer on the second sidewall, the first spacer thinner than the second spacer.
摘要翻译：制造不对称间隔物的方法，使用不对称间隔物制造的结构和用于制造不对称间隔物的装置。该方法包括：在基底上形成具有顶表面和相对的第一和第二侧壁并具有平行于侧壁的纵向轴线的结构; 在所述基底的顶表面，所述结构的顶表面和所述结构的侧壁上形成共形层; 相对于反应离子通量使基板围绕纵向轴线倾斜，反应离子的流量以锐角撞击共形层; 以及将所述保形层暴露于所述反应性离子的通量，直到所述保形层从所述结构的顶表面去除并且所述衬底的顶表面在所述第一侧壁上离开第一间隔物，并在所述第二侧壁上留下第二间隔物，所述第一间隔物比第二间隔物薄。

10. 发明申请

US20090017584A1 PROCESS FOR FINFET SPACER FORMATION 有权
标题翻译： FINFET间隙形成工艺
公开(公告)号：US20090017584A1
公开(公告)日：2009-01-15
申请号：US11776710
申请日：2007-07-12
申请人： Kangguo Cheng , Xi Li , Richard S. Wise
发明人： Kangguo Cheng , Xi Li , Richard S. Wise
IPC分类号： H01L29/786
CPC分类号： H01L29/66795 , H01L29/785
摘要： A process for finFET spacer formation generally includes depositing, in order, a conformnal liner material, a conformal spacer material, and a conformal capping material onto the finFET structure; tilt implanting dopant ions into portions of the capping layer about the gate structure; selectively removing undoped capping material about the source and drain regions; selectively removing exposed portions of the spacer material; selectively removing exposed portions of the capping material; anisotropically removing a portion of the spacer material so as to expose a top surface of the gate material and isolate the spacer material to sidewalls of the gate structure; and removing the oxide liner from the fin to form the spacer on the finFET structure.
摘要翻译：用于finFET间隔物形成的方法通常包括依次将共形衬垫材料，共形隔离材料和保形封盖材料沉积到finFET结构上; 倾斜地将掺杂剂离子注入围绕栅极结构的覆盖层的部分; 围绕源极和漏极区域选择性地去除未掺杂的封盖材料; 选择性地去除间隔物材料的暴露部分; 选择性地去除封盖材料的暴露部分; 各向异性地去除间隔物材料的一部分，以露出栅极材料的顶表面并将间隔物材料隔离到栅极结构的侧壁; 以及从翅片上去除氧化物衬垫以在finFET结构上形成间隔物。

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