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1. 发明授权

US07185309B1 Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip 有权
标题翻译：专用于可编程存储器架构和芯片上互连网络的方法和装置
公开(公告)号：US07185309B1
公开(公告)日：2007-02-27
申请号：US10769591
申请日：2004-01-30
申请人： Chidamber R. Kulkarni , Gordon J. Brebner , Eric R. Keller , Philip B. James-Roxby
发明人： Chidamber R. Kulkarni , Gordon J. Brebner , Eric R. Keller , Philip B. James-Roxby
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, specification data is received that includes attributes of the memory system. A logical description of the memory system is generated in response to the specification data. The logical description defines a memory component and a memory-interconnection component. A physical description of the memory system is generated in response to the logical description. The physical description includes memory circuitry associated with the integrated circuit defined by the memory component. The memory circuitry includes an interconnection topology defined by the memory interconnection component.
摘要翻译：描述了用于实现使用集成电路的消息处理系统的可编程架构。在一个示例中，接收包括存储器系统的属性的规范数据。响应于规范数据生成存储器系统的逻辑描述。逻辑描述定义了存储器组件和存储器互连组件。响应于逻辑描述生成存储器系统的物理描述。物理描述包括与由存储器组件定义的集成电路相关联的存储器电路。存储器电路包括由存储器互连部件定义的互连拓扑。

2. 发明授权

US08065130B1 Method for message processing on a programmable logic device 有权
标题翻译：在可编程逻辑器件上进行消息处理的方法
公开(公告)号：US08065130B1
公开(公告)日：2011-11-22
申请号：US12465247
申请日：2009-05-13
申请人： Gordon J. Brebner , Philip B. James-Roxby , Eric R. Keller , Chidamber R. Kulkarni
发明人： Gordon J. Brebner , Philip B. James-Roxby , Eric R. Keller , Chidamber R. Kulkarni
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , H04L45/60
摘要： Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, configurable logic of an integrated circuit is configured to have a plurality of thread circuits and a memory. Messages are received to the integrated circuit for storage in the memory. The memory is accessed with the plurality of threads to concurrently process a plurality of the messages.
摘要翻译：描述了用于实现使用集成电路的消息处理系统的可编程架构。在一个示例中，集成电路的可配置逻辑被配置为具有多个线程电路和存储器。消息被接收到集成电路以存储在存储器中。利用多个线程来访问存储器以同时处理多个消息。

3. 发明授权

US07784014B1 Generation of a specification of a network packet processor 有权
标题翻译：生成网络包处理器的规范
公开(公告)号：US07784014B1
公开(公告)日：2010-08-24
申请号：US11799897
申请日：2007-05-03
申请人： Gordon J. Brebner , Christopher E. Neely , Philip B. James-Roxby , Eric R. Keller , Chidamber R. Kulkarni , Michael A. Baxter , Henry E. Styles , Graham F. Schelle
发明人： Gordon J. Brebner , Christopher E. Neely , Philip B. James-Roxby , Eric R. Keller , Chidamber R. Kulkarni , Michael A. Baxter , Henry E. Styles , Graham F. Schelle
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method is provided for generating a hardware description language (HDL) specification of a network packet processor from a textual language specification of the processing of network packets by the processor. The processor includes a look-ahead stage, an operation stage, an insert/remove stage, and an interleave stage. The textual language specification identifies the ports of the processor. The textual language specification includes formats for the type or types of the incoming and outgoing network packets. Each format includes the fields of the type of network packet. The textual language specification includes a procedure for each input port and for each type of incoming network packet received at the input port. Each procedure includes one or more actions for modifying the fields of a type of network packet as a function of state data and/or the fields of the type of network packet.
摘要翻译：提供了一种从处理器对网络分组的处理的文本语言规范生成网络分组处理器的硬件描述语言（HDL）规范的方法。处理器包括前视级，操作级，插入/移除级和交错级。文本语言规范识别处理器的端口。文本语言规范包括进出网络数据包的类型或类型的格式。每个格式包括网络包类型的字段。文本语言规范包括每个输入端口和在输入端口接收的每种类型的传入网络分组的过程。每个过程包括用于根据状态数据和/或网络分组类型的字段修改网络分组类型的字段的一个或多个动作。

4. 发明授权

US07552042B1 Method for message processing on a programmable logic device 有权
标题翻译：在可编程逻辑器件上进行消息处理的方法
公开(公告)号：US07552042B1
公开(公告)日：2009-06-23
申请号：US10769592
申请日：2004-01-30
申请人： Gordon J. Brebner , Philip B. James-Roxby , Eric R. Keller , Chidamber R. Kulkarni
发明人： Gordon J. Brebner , Philip B. James-Roxby , Eric R. Keller , Chidamber R. Kulkarni
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , H04L45/60
摘要： Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, configurable logic of an integrated circuit is configured to have a plurality of thread circuits and a memory. Messages are received to the integrated circuit for storage in the memory. The memory is accessed with the plurality of threads to concurrently process a plurality of the messages.
摘要翻译：描述了用于实现使用集成电路的消息处理系统的可编程架构。在一个示例中，集成电路的可配置逻辑被配置为具有多个线程电路和存储器。消息被接收到集成电路以存储在存储器中。利用多个线程来访问存储器以同时处理多个消息。

5. 发明授权

US07770179B1 Method and apparatus for multithreading on a programmable logic device 有权
标题翻译：用于可编程逻辑器件上多线程的方法和装置
公开(公告)号：US07770179B1
公开(公告)日：2010-08-03
申请号：US10769330
申请日：2004-01-30
申请人： Philip B. James-Roxby , Gordon J. Brebner , Eric R. Keller , Chidamber R. Kulkarni
发明人： Philip B. James-Roxby , Gordon J. Brebner , Eric R. Keller , Chidamber R. Kulkarni
IPC分类号： G06F9/46 , G06F17/50
CPC分类号： G06F17/5054
摘要： Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, configurable logic of the integrated circuit is configured to have a plurality of thread circuits and an interconnection topology amongst the plurality of thread circuits. Messages are concurrently processed using the plurality of thread circuits. Operation of at least one thread circuit of the plurality of thread circuits is controlled in accordance with control data received via the interconnection topology from at least one other thread circuit of the plurality of thread circuits.
摘要翻译：描述了用于实现使用集成电路的消息处理系统的可编程架构。在一个示例中，集成电路的可配置逻辑被配置为在多个线程电路之间具有多个线程电路和互连拓扑。使用多个线程电路同时处理消息。根据从多个线程电路的至少一个其它线程电路经由互连拓扑接收的控制数据来控制多个线程电路中的至少一个线程电路的操作。

6. 发明授权

US07574680B1 Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip 有权
标题翻译：专用于可编程存储器架构和芯片上互连网络的方法和装置
公开(公告)号：US07574680B1
公开(公告)日：2009-08-11
申请号：US11699097
申请日：2007-01-29
申请人： Chidamber R. Kulkarni , Gordon J. Brebner , Eric R. Keller , Philip B. James-Roxby
发明人： Chidamber R. Kulkarni , Gordon J. Brebner , Eric R. Keller , Philip B. James-Roxby
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, specification data is received that includes attributes of the memory system. A logical description of the memory system is generated in response to the specification data. The logical description defines a memory component and a memory-interconnection component. A physical description of the memory system is generated in response to the logical description. The physical description includes memory circuitry associated with the integrated circuit defined by the memory component. The memory circuitry includes an interconnection topology defined by the memory interconnection component.
摘要翻译：描述了用于实现使用集成电路的消息处理系统的可编程架构。在一个示例中，接收包括存储器系统的属性的规范数据。响应于规范数据生成存储器系统的逻辑描述。逻辑描述定义了存储器组件和存储器互连组件。响应于逻辑描述生成存储器系统的物理描述。物理描述包括与由存储器组件定义的集成电路相关联的存储器电路。存储器电路包括由存储器互连部件定义的互连拓扑。

7. 发明授权

US07228520B1 Method and apparatus for a programmable interface of a soft platform on a programmable logic device 有权
标题翻译：用于可编程逻辑器件上的软平台的可编程接口的方法和装置
公开(公告)号：US07228520B1
公开(公告)日：2007-06-05
申请号：US10769331
申请日：2004-01-30
申请人： Eric R. Keller , Gordon J. Brebner , Philip B. James-Roxby , Chidamber R. Kulkarni
发明人： Eric R. Keller , Gordon J. Brebner , Philip B. James-Roxby , Chidamber R. Kulkarni
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, first attributes are defined for a plurality of threads within the integrated circuit. Second attributes are defined for a memory associated with the integrated circuit. Third attributes are defined for an interconnection topology associated with at least one of the memory and the plurality of threads. Fourth attributes are defined for an interface to at least one of the memory and the plurality of threads.
摘要翻译：描述了用于实现使用集成电路的消息处理系统的可编程架构。在一个示例中，为集成电路内的多个线程定义第一属性。为与集成电路相关联的存储器定义第二属性。为与存储器和多个线程中的至少一个相关联的互连拓扑定义第三属性。为与至少一个存储器和多个线程的接口定义第四属性。

8. 发明授权

US08032874B1 Generation of executable threads having source code specifications that describe network packets 有权
标题翻译：生成具有描述网络数据包的源代码规范的可执行线程
公开(公告)号：US08032874B1
公开(公告)日：2011-10-04
申请号：US11336163
申请日：2006-01-20
申请人： Eric R. Keller , Philip B. James-Roxby
发明人： Eric R. Keller , Philip B. James-Roxby
IPC分类号： G06F9/45 , G06F15/76
CPC分类号： G06F8/4434
摘要： From source code specification of each of a plurality of threads, those variables of a data structure referenced by the thread are determined. For each thread, a respective adaptation of the source code specification of the data structure is generated. Each adaptation includes only variables of the data structure that are referenced in the respective thread. The source code specifications of the threads are compiled into respective object code segments using the respective adaptations of the data structures. Each object code segment requires memory space for the data structure for only those variables included in the respective adaptation. The source code specification of the data structure describes a network packet, and the respective object code segments are configured to operate on the respective portions of the network packet stored in separate memories while executing on respective processors.
摘要翻译：根据多个线程中的每一个的源代码规范，确定线程引用的数据结构的那些变量。对于每个线程，生成数据结构的源代码规范的各自的适配。每个自适应仅包括在相应线程中引用的数据结构的变量。使用数据结构的相应修改，将线程的源代码规范编译成各自的对象代码段。每个目标代码段仅需要用于数据结构的存储器空间，用于仅包括在各自适配中的那些变量。数据结构的源代码规范描述了网络分组，并且相应的目标代码段被配置为在各个处理器上执行时在存储在单独存储器中的网络分组的各个部分上进行操作。

9. 发明授权

US07990867B1 Pipeline for processing network packets 有权
标题翻译：用于处理网络数据包的流水线
公开(公告)号：US07990867B1
公开(公告)日：2011-08-02
申请号：US11799860
申请日：2007-05-03
申请人： Eric R. Keller , Philip B. James-Roxby
发明人： Eric R. Keller , Philip B. James-Roxby
IPC分类号： G01R31/08
CPC分类号： H04L69/161
摘要： A pipeline is provided for processing network packets. The pipeline includes a look-ahead stage, an operation stage, an insert/remove stage, and an interleave stage. The look-ahead stage synchronizes two or more fields of a network packet. The operation stage modifies one or more of the fields of the network packet. The operation stage may modify state data and the fields of the network packet as a function of the state data and the fields. The insert/remove stage performs data insertion and removal at one or more fields of the network packet. The interleave stage ensures that the modified network packet follows rules for interleaving network packets. The look-ahead, operation, insert/remove, and interleave stages are generated from a textual language specification of the processing of the network packets by the pipeline.
摘要翻译：提供流水线来处理网络数据包。流水线包括一个预览阶段，一个操作阶段，一个插入/去除阶段和一个交错阶段。先行阶段同步网络数据包的两个或多个字段。操作阶段修改网络包的一个或多个字段。操作阶段可以根据状态数据和字段来修改状态数据和网络包的字段。插入/删除阶段在网络数据包的一个或多个字段执行数据插入和删除。交织阶段确保修改的网络分组遵循用于交织网络分组的规则。通过流水线对网络数据包的处理的文本语言规范生成前瞻，操作，插入/删除和交错阶段。

10. 发明授权

US07227378B2 Reconfiguration of a programmable logic device using internal control 有权
标题翻译：使用内部控制重新配置可编程逻辑器件
公开(公告)号：US07227378B2
公开(公告)日：2007-06-05
申请号：US11100971
申请日：2005-04-07
申请人： Brandon J. Blodget , Scott P. McMillan , Philip B. James-Roxby , Prasanna Sundararajan , Eric R. Keller , Derek R. Curd , Punit S. Kalra , Richard J. LeBlanc , Vincent P. Eck
发明人： Brandon J. Blodget , Scott P. McMillan , Philip B. James-Roxby , Prasanna Sundararajan , Eric R. Keller , Derek R. Curd , Punit S. Kalra , Richard J. LeBlanc , Vincent P. Eck
IPC分类号： G06F7/38
CPC分类号： H03K19/17752 , G06F15/7867 , H03K19/17732 , H03K19/17756
摘要： A method of partially reconfiguring an IC having programmable modules that includes the steps of reading a frame of configuration information from the configuration memory array; modifying at least part of the configuration information, thereby creating a modified frame of configuration information; and overwriting the existing frame of configuration information in the configuration memory array with the modified frame, thereby partially reconfiguring the IC.
摘要翻译：一种部分重新配置具有可编程模块的IC的方法，包括从配置存储器阵列读取配置信息的帧的步骤; 修改所述配置信息的至少一部分，从而创建修改的配置信息帧; 并用修改的帧覆盖配置存储器阵列中的配置信息的现有帧，由此部分地重新配置IC。

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