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1. 发明授权

US06604201B1 Network unit with power saving mode inhibit based on interconnection relationship to neighboring nodes which is stored on the unit 有权
标题翻译：具有省电模式的网络单元基于与存储在单元上的相邻节点的互连关系而禁止
公开(公告)号：US06604201B1
公开(公告)日：2003-08-05
申请号：US09428277
申请日：1999-10-27
申请人： Satoshi Takahashi , Hiroyuki Yamauchi , Hironori Akamatsu , Tadahiro Yoshida , Yutaka Terada , Yukio Arima , Takashi Hirata , Yoshihide Komatsu
发明人： Satoshi Takahashi , Hiroyuki Yamauchi , Hironori Akamatsu , Tadahiro Yoshida , Yutaka Terada , Yukio Arima , Takashi Hirata , Yoshihide Komatsu
IPC分类号： G06F132
CPC分类号： H04L12/12 , Y02D50/20 , Y02D50/40
摘要： A power-saving network unit, which is connected to a network made up of a plurality of power-saving network units, includes: network monitoring means; network information memory; power-saving mode setting means; peripheral I/O interface; and digital processor. The network monitoring means monitors a topology of the network, or the interconnection relationship among the power-saving network units. Every time the network has been modified, the network monitoring means stores the modified network topology on the network information memory. The power-saving mode setting means receives the network information stored on the network information memory. If the power-saving network unit is a master or relay node in the network, then the power-saving mode setting means locks the peripheral I/O interface and digital processor of the power-saving network unit to the normal operation mode and prohibits these sections from entering the power-saving mode.
摘要翻译：连接到由多个省电网络单元组成的网络的节电网单元包括：网络监控装置; 网络信息记忆; 省电模式设定手段; 外设I / O接口; 和数字处理器。网络监控装置监控网络的拓扑结构，或节能网络单元之间的互连关系。每当网络被修改时，网络监控装置将修改的网络拓扑存储在网络信息存储器上。省电模式设置装置接收存储在网络信息存储器上的网络信息。如果省电网络单元是网络中的主节点或中继节点，则省电模式设置装置将节电网络单元的外围I / O接口和数字处理器锁定到正常操作模式，并禁止这些部分进入省电模式。

2. 发明授权

US06498519B1 Voltage control circuit network device and method of detecting voltage 有权
标题翻译：电压控制电路网络装置及电压检测方法
公开(公告)号：US06498519B1
公开(公告)日：2002-12-24
申请号：US09498339
申请日：2000-02-04
申请人： Yutaka Terada , Hiroyuki Yamauchi , Hironori Akamatsu , Tadahiro Yoshida , Satoshi Takahashi , Takashi Hirata , Yukio Arima , Yoshihide Komatsu
发明人： Yutaka Terada , Hiroyuki Yamauchi , Hironori Akamatsu , Tadahiro Yoshida , Satoshi Takahashi , Takashi Hirata , Yukio Arima , Yoshihide Komatsu
IPC分类号： H03K5153
CPC分类号： G01R19/16547
摘要： A voltage control circuit for implementing, e.g., the CPS function in which a high-accuracy comparison is performed between a high external voltage and a reference voltage. A diode-connected transistor converts the external voltage to a voltage lower than the external voltage in conjunction with an external voltage dropping resistor. A comparator compares the converted voltage with a specified comparison voltage. The size of the transistor is determined such that the ratio of an increment of the converted voltage to an increment of the external voltage is sufficiently high in a comparison region in which the external voltage is close to the reference voltage. A clamping circuit clamps the converted voltage with a specified limit voltage such that the converted voltage does not exceed the withstand voltage of the circuit.
摘要翻译：一种用于实现例如在高外部电压和参考电压之间进行高精度比较的CPS功能的电压控制电路。二极管连接的晶体管将外部电压转换为低于外部电压的电压，并结合外部降压电阻。比较器将转换的电压与指定的比较电压进行比较。确定晶体管的尺寸，使得在外部电压接近参考电压的比较区域中，转换电压的增量与外部电压的增量的比率足够高。钳位电路以转换后的电压将指定的极限电压钳位，使转换后的电压不超过电路的耐压。

3. 发明授权

US06297675B1 Semiconductor integrated circuit and semiconductor integrated circuit system having serially interconnectable data buses 有权
标题翻译：具有串行可互连数据总线的半导体集成电路和半导体集成电路系统
公开(公告)号：US06297675B1
公开(公告)日：2001-10-02
申请号：US09478530
申请日：2000-01-06
申请人： Hironori Akamatsu , Yutaka Terada , Takashi Hirata , Yukio Arima , Satoshi Takahashi , Tadahiro Yoshida , Yoshihide Komatsu , Hiroyuki Yamauchi
发明人： Hironori Akamatsu , Yutaka Terada , Takashi Hirata , Yukio Arima , Satoshi Takahashi , Tadahiro Yoshida , Yoshihide Komatsu , Hiroyuki Yamauchi
IPC分类号： H03B100
CPC分类号： H03K19/018514 , Y10T307/549
摘要： A data line pair and a strobe line pair are provided between first and second chips to exchange data therebetween. The first chip includes an output circuit and a controller for controlling the output circuit. The second chip includes an input circuit. For example, the output circuit supplies a direct current from a power supply to one of the data lines. Then, the input circuit feeds back the received current to the output circuit through a pair of terminal resistors and the other data line. Subsequently, the output circuit supplies the fed back direct current to one of the strobe lines. In response, the input circuit feeds back the received current again to the output circuit through another pair of terminal resistors and the other strobe line. And then the fed back current is drained to the ground. Thus, compared to driving the data and strobe line pairs separately with the same amount of current supplied, the current dissipation can be halved. In this manner, the present invention is applicable to reduction of current dissipation when data should be transmitted at high speeds through multiple data bus pairs that are driven with a current supplied.
摘要翻译：在第一和第二芯片之间提供数据线对和选通线对，以在它们之间交换数据。第一芯片包括输出电路和用于控制输出电路的控制器。第二芯片包括输入电路。例如，输出电路将电流从电源提供给数据线之一。然后，输入电路通过一对端子电阻和另一条数据线将接收的电流反馈到输出电路。随后，输出电路将反馈的直流电流提供给选通线之一。作为响应，输入电路通过另一对端子电阻器和另一个选通线路将接收到的电流再次反馈到输出电路。然后将反馈电流排到地面。因此，与以相同的电流量驱动数据和选通线对相比，电流消耗可以减半。以这种方式，本发明可应用于当通过以所提供的电流驱动的多个数据总线对以高速传输数据时，减少电流消耗。

4. 发明授权

US06633588B1 Data transferring device 有权
标题翻译：数据传输设备
公开(公告)号：US06633588B1
公开(公告)日：2003-10-14
申请号：US09410764
申请日：1999-10-01
申请人： Tadahiro Yoshida , Hiroyuki Yamauchi , Hironori Akamatsu , Satoshi Takahashi , Yutaka Terada , Yukio Arima , Takashi Hirata , Yoshihide Komatsu
发明人： Tadahiro Yoshida , Hiroyuki Yamauchi , Hironori Akamatsu , Satoshi Takahashi , Yutaka Terada , Yukio Arima , Takashi Hirata , Yoshihide Komatsu
IPC分类号： G06F1516
CPC分类号： G06F13/4265 , Y02D10/14 , Y02D10/151
摘要： First and second nodes are coupled together by a bus. The first node includes a detecting circuit for detecting the maximum data transfer capability of a connected node, at least two receiving circuits for receiving data from the bus, and a controlling circuit for selecting, based on an output signal from the detecting circuit and for optimizing the configuration of a receiving unit so as to bring the other of the receiving circuits to a stop. The second node includes a transmitting circuit for transmitting data to the bus and a notifying circuit for notifying the first node of its own maximum transfer capability.
摘要翻译：第一和第二节点通过总线耦合在一起。第一节点包括用于检测连接节点的最大数据传输能力的检测电路，用于从总线接收数据的至少两个接收电路，以及用于基于来自检测电路的输出信号进行优化的控制电路接收单元的配置，以使另一个接收电路停止。第二节点包括用于向总线发送数据的发送电路和用于通知第一节点自己的最大传输能力的通知电路。

5. 发明授权

US06631486B1 Semiconductor integrated circuit and method for testing the same 有权
标题翻译：半导体集成电路及其测试方法
公开(公告)号：US06631486B1
公开(公告)日：2003-10-07
申请号：US09405015
申请日：1999-09-27
申请人： Yoshihide Komatsu , Tadahiro Yoshida , Yukio Arima
发明人： Yoshihide Komatsu , Tadahiro Yoshida , Yukio Arima
IPC分类号： G01R3128
CPC分类号： G01R31/31905 , G01R31/31926
摘要： A test enable signal Data_En is output from a data generator 11 in a tester 10 to a device under a test (DUT) 20. In the DUT 20, a first logic circuit 21 converts a signal pattern with an ordinary transfer rate, which has been stored on a register 28, into a high-transfer-rate signal pattern SpeedData_Tx with a high rate. And a transmitter 22 transmits the high-transfer-rate signal. During a test, the high-transfer-rate signal transmitted is received by, a receiver 23 with a switch 24 turned ON. Then, the high-transfer-rate signal received is output to a second logic circuit 26, which converts the high-transfer-rate signal into a low-transfer-rate signal Data_Rx with an ordinary rate. Finally, the low-transfer-rate signal is output to the tester 10 and compared to an expected value thereof by a comparator 12. In this manner, a semiconductor device operating at a high speed can be tested using a tester operating at a lower speed.
摘要翻译：测试使能信号Data_En从测试器10中的数据发生器11输出到被测设备（DUT）20。在DUT 20中，第一逻辑电路21以一般传输速率转换信号模式存储在寄存器28中，以高速率转换成高传输速率信号模式SpeedData_Tx。并且发射机22发送高传输速率信号。在测试期间，传输的高传输速率信号由开关24接通的接收机23接收。然后，所接收的高传输速率信号被输出到第二逻辑电路26，第二逻辑电路26将高传输速率信号以普通速率转换成低传输速率信号Data_Rx。最后，将低传输速率信号输出到测试器10，并通过比较器12与其期望值进行比较。以这种方式，可以使用以较低速度操作的测试仪来测试以高速工作的半导体器件。

6. 发明申请

US20110164693A1 INTERFACE CIRCUIT 审中-公开
标题翻译：接口电路
公开(公告)号：US20110164693A1
公开(公告)日：2011-07-07
申请号：US13047337
申请日：2011-03-14
申请人： Yoshihide KOMATSU , Tsuyoshi Ebuchi , Yukio Arima , Toru Iwata
发明人： Yoshihide KOMATSU , Tsuyoshi Ebuchi , Yukio Arima , Toru Iwata
IPC分类号： H04L27/00
CPC分类号： H04L7/0008 , G06F1/12 , H04L5/1469 , H04L5/16 , H04L25/0272 , H04L25/0298
摘要： An interface circuit including an LSI (10) in a host device (1), and an LSI (20) in a sub device (2), respectively. The LSI (10) generates a first transmission clock signal (TC1) and a first reception clock signal (RC1) separately in accordance with a first reference clock signal (RFC1). The LSI (10) also generates a second reference clock signal (RFC2) for a sub device (2). The reference clock signal (RFC2) is converted into a differential clock signal, and then transmitted to the sub device (2). An LSI (20) of the sub device (2) generates a second transmission clock signal (TC2) and a second reception clock signal (RC2) separately in accordance with a third reference clock signal (RFC3) converted from the differential clock signal.
摘要翻译：一种在主机（1）中包括LSI（10）的接口电路和分装置（2）中的LSI（20）。 LSI（10）根据第一参考时钟信号（RFC1）分别产生第一传输时钟信号（TC1）和第一接收时钟信号（RC1）。 LSI（10）还为子设备（2）生成第二参考时钟信号（RFC2）。参考时钟信号（RFC2）被转换为差分时钟信号，然后发送到子设备（2）。子装置（2）的LSI（20）根据从差分时钟信号转换的第三参考时钟信号（RFC3）分别产生第二传输时钟信号（TC2）和第二接收时钟信号（RC2）。

7. 发明授权

US07898305B2 PLL circuit 有权
标题翻译： PLL电路
公开(公告)号：US07898305B2
公开(公告)日：2011-03-01
申请号：US12651061
申请日：2009-12-31
申请人： Tatsuo Okamoto , Yukio Arima , Tsuyoshi Ebuchi , Kyoko Hirata
发明人： Tatsuo Okamoto , Yukio Arima , Tsuyoshi Ebuchi , Kyoko Hirata
IPC分类号： H03L7/00
CPC分类号： H03L7/10 , H03L7/085 , H03L7/099 , H03L7/0995 , H03L7/1976
摘要： A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).
摘要翻译： PLL包括电流控制振荡器（18），用于基于基于参考时钟信号和反馈时钟信号之间的相位差产生的电流信号，电流源（28）和初始化开关（18）来产生输出时钟信号（26），用于基于所述初始化信号执行打开/关闭操作，所述初始化开关串联插入到所述电流控制振荡器（18）和所述电流源（28）的输入端子。

8. 发明授权

US07746132B2 PLL circuit 有权
标题翻译： PLL电路
公开(公告)号：US07746132B2
公开(公告)日：2010-06-29
申请号：US12066000
申请日：2006-07-27
申请人： Tatsuo Okamoto , Yukio Arima , Tsuyoshi Ebuchi , Kyoko Hirata
发明人： Tatsuo Okamoto , Yukio Arima , Tsuyoshi Ebuchi , Kyoko Hirata
IPC分类号： H03L7/06
CPC分类号： H03L7/10 , H03L7/085 , H03L7/099 , H03L7/0995 , H03L7/1976
摘要： A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).
摘要翻译： PLL包括电流控制振荡器（18），用于基于基于参考时钟信号和反馈时钟信号之间的相位差产生的电流信号，电流源（28）和初始化开关（18）来产生输出时钟信号（26），用于基于所述初始化信号执行打开/关闭操作，所述初始化开关串联插入到所述电流控制振荡器（18）和所述电流源（28）的输入端子。

9. 发明申请

US20050135505A1 Frequency modulation circuit 有权
标题翻译：频率调制电路
公开(公告)号：US20050135505A1
公开(公告)日：2005-06-23
申请号：US11000224
申请日：2004-12-01
申请人： Tsuyoshi Ebuchi , Takefumi Yoshikawa , Yukio Arima
发明人： Tsuyoshi Ebuchi , Takefumi Yoshikawa , Yukio Arima
IPC分类号： H03C3/00 , H03K7/06 , H03L7/093 , H04B15/02 , H04B3/46
CPC分类号： H04B15/02 , H03K7/06 , H04B2215/067
摘要： The frequency modulation circuit includes: a phase shift section for receiving a multiphase clock signal composed of a plurality of clock signals having a predetermined phase difference therebetween and shifting the phase of the multiphase clock signal; a clock selection section for selecting a clock signal constituting the multiphase clock signal output from the phase shift section; and a modulation control section for controlling the phase shift section and the clock selection section so that a clock signal having a frequency different from the frequency of the multiphase clock signal input into the phase shift section is output from the clock selection section.
摘要翻译：频率调制电路包括：相移部，用于接收由多个时钟信号组成的多相时钟信号，所述多个时钟信号具有预定的相位差，并移位多相时钟信号的相位; 时钟选择部分，用于选择构成从相移部分输出的多相时钟信号的时钟信号; 以及调制控制部分，用于控制相移部分和时钟选择部分，使得从时钟选择部分输出具有与输入到相移部分的多相时钟信号的频率不同的频率的时钟信号。

10. 发明授权

US5293326A Ultrasonic inspection and imaging instrument 失效
标题翻译：超声波检查和成像仪器
公开(公告)号：US5293326A
公开(公告)日：1994-03-08
申请号：US719510
申请日：1991-06-24
申请人： Yukio Arima , Hiroaki Yanagimoto , Yuichi Kunitomo , Shouya Makihara , Tetsuyoshi Tominaga
发明人： Yukio Arima , Hiroaki Yanagimoto , Yuichi Kunitomo , Shouya Makihara , Tetsuyoshi Tominaga
IPC分类号： G01N29/06 , G01N29/44 , G01Q10/06 , G01Q30/04 , G01Q80/00 , G01Q90/00 , G01S7/52 , G01N29/00 , G09G5/00
CPC分类号： G01S7/52074 , G01N29/0609 , G01N29/0645 , B82Y35/00 , G01N2291/02854
摘要： An ultrasonic inspection and imaging instrument is characterized by storing reduced image examples (images by means of reduced image display data obtained by scaling down picture display data) of an ultrasonic measurement picture beforehand, together with measurement conditions at the time the measurement picture is obtained prior to a scale-down imaging process. When the measurement is started or the measurement conditions are otherwise changed, the measurement conditions are set as those obtained from the measurement picture prior to the scale-down processing with one of the reduced image examples thus selected as an index while a list of image examples is indicated on a display and read from a memory unit for ultrasonic measuring purposes. When a reduced image example or what is similar to the example desired by an operator is selected, proper measurement conditions are automatically set in the ultrasonic inspection and imaging instrument. When the operator wants to change or switch the measurement picture, moreover, he/she is able to make ultrasonic measurement on confirming what the subsequent image is like or what an image is desired to be selected by means of the reduced image example beforehand.
摘要翻译：超声波检查和成像仪器的特征在于预先存储超声波测量图像的缩小图像示例（通过缩小图像显示数据获得的缩小图像显示数据的图像）以及在获得测量图像时的测量条件到缩小成像过程。当测量开始或测量条件另外改变时，测量条件被设置为在缩小处理之前从测量图像获得的测量条件，其中一个缩小图像示例被选择为索引，而图像示例列表在显示器上指示并从用于超声波测量目的的存储器单元读取。当选择缩小的图像示例或类似于操作者期望的示例时，在超声波检查和成像仪器中自动设置适当的测量条件。此外，当操作者想要改变或切换测量图像时，他/她能够通过预先通过缩小的图像实例来确认随后的图像是什么样的或希望选择什么图像来进行超声波测量。

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