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1. 发明申请

US20070288694A1 DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING HAVING CONTROLLABLE STORE GATHER WINDOWS 审中-公开
标题翻译：数据处理系统，具有可控储存窗口的数据处理的处理器和方法
公开(公告)号：US20070288694A1
公开(公告)日：2007-12-13
申请号：US11423717
申请日：2006-06-13
申请人： Sanjeev Ghai , Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams
发明人： Sanjeev Ghai , Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F9/3824 , G06F9/3834
摘要： A data processing system includes a processor core and a memory subsystem coupled to the processor core. The memory subsystem includes data storage and a store queue including a plurality of entries for buffering store operations to be performed with reference to the data storage. The memory subsystem further includes a store queue controller that gathers multiple store requests received from the processor core into a single store operation buffered within an entry of the store queue. The store queue controller applies store gathering windows of differing durations to differing ones of the plurality of entries in response to control information received from the processor core.
摘要翻译：数据处理系统包括处理器核心和耦合到处理器核心的存储器子系统。存储器子系统包括数据存储器和存储队列，其包括用于缓冲要参考数据存储器执行的存储操作的多个条目。存储器子系统还包括存储队列控制器，其将从处理器核心接收的多个存储请求收集到缓冲在存储队列的条目内的单个存储操作中。存储队列控制器响应于从处理器核心接收到的控制信息，将具有不同持续时间的商店收集窗口应用到多个条目中的不同条目。

2. 发明申请

US20130262778A1 DATA CACHE BLOCK DEALLOCATE REQUESTS IN A MULTI-LEVEL CACHE HIERARCHY 有权
标题翻译：数据缓存区块在多级高速缓存中调用请求
公开(公告)号：US20130262778A1
公开(公告)日：2013-10-03
申请号：US13433048
申请日：2012-03-28
申请人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
发明人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/12
CPC分类号： G06F12/0817 , G06F12/0804 , G06F12/121 , G06F12/122 , G06F12/126
摘要： In response to executing a deallocate instruction, a deallocation request specifying a target address of a target cache line is sent from a processor core to a lower level cache. In response, a determination is made if the target address hits in the lower level cache. If so, the target cache line is retained in a data array of the lower level cache, and a replacement order field of the lower level cache is updated such that the target cache line is more likely to be evicted in response to a subsequent cache miss in a congruence class including the target cache line. In response to the subsequent cache miss, the target cache line is cast out to the lower level cache with an indication that the target cache line was a target of a previous deallocation request of the processor core.
摘要翻译：响应于执行取消分配指令，将指定目标高速缓存行的目标地址的解除分配请求从处理器核发送到较低级高速缓存。作为响应，确定目标地址是否在较低级别高速缓存中。如果是这样，则目标高速缓存行被保留在较低级高速缓存的数据阵列中，并且更新较低级高速缓存的替换顺序字段，使得目标高速缓存行更可能响应于后续高速缓存未命中而被驱逐在包含目标缓存行的同余类中。响应于随后的高速缓存未命中，目标高速缓存行被推出到较低级缓存，指示目标高速缓存行是处理器核心的先前释放请求的目标。

3. 发明授权

US08856455B2 Data cache block deallocate requests 有权
标题翻译：数据缓存块取消分配请求
公开(公告)号：US08856455B2
公开(公告)日：2014-10-07
申请号：US13433022
申请日：2012-03-28
申请人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
发明人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F12/0815 , G06F12/0804 , G06F12/0817 , G06F12/0897 , G06F12/126
摘要： A data processing system includes a processor core supported by upper and lower level caches. In response to executing a deallocate instruction in the processor core, a deallocation request is sent from the processor core to the lower level cache, the deallocation request specifying a target address associated with a target cache line. In response to receipt of the deallocation request at the lower level cache, a determination is made if the target address hits in the lower level cache. In response to determining that the target address hits in the lower level cache, the target cache line is retained in a data array of the lower level cache and a replacement order field in a directory of the lower level cache is updated such that the target cache line is more likely to be evicted from the lower level cache in response to a subsequent cache miss.
摘要翻译：数据处理系统包括由上层和下层高速缓存支持的处理器核心。响应于在处理器核心中执行取消分配指令，从处理器核心向下级高速缓存发送解除分配请求，所述释放请求指定与目标高速缓存行相关联的目标地址。响应于在较低级别高速缓存处接收到解除分配请求，确定目标地址是否在较低级别高速缓存中。为了响应于确定目标地址在较低级别高速缓存中的命中，目标高速缓存行被保留在较低级别高速缓存的数据阵列中，并且更新下级高速缓存的目录中的替换顺序字段，使得目标高速缓存线路可能会响应于后续的高速缓存未命中而从较低级别的缓存中逐出。

4. 发明授权

US08874852B2 Data cache block deallocate requests in a multi-level cache hierarchy 有权
标题翻译：数据缓存块在多级缓存层次结构中释放请求
公开(公告)号：US08874852B2
公开(公告)日：2014-10-28
申请号：US13433048
申请日：2012-03-28
申请人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
发明人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/0804 , G06F12/121 , G06F12/122 , G06F12/126
摘要： In response to executing a deallocate instruction, a deallocation request specifying a target address of a target cache line is sent from a processor core to a lower level cache. In response, a determination is made if the target address hits in the lower level cache. If so, the target cache line is retained in a data array of the lower level cache, and a replacement order field of the lower level cache is updated such that the target cache line is more likely to be evicted in response to a subsequent cache miss in a congruence class including the target cache line. In response to the subsequent cache miss, the target cache line is cast out to the lower level cache with an indication that the target cache line was a target of a previous deallocation request of the processor core.
摘要翻译：响应于执行取消分配指令，将指定目标高速缓存行的目标地址的解除分配请求从处理器核发送到较低级高速缓存。作为响应，确定目标地址是否在较低级别高速缓存中。如果是这样，则目标高速缓存行被保留在较低级高速缓存的数据阵列中，并且更新较低级高速缓存的替换顺序字段，使得目标高速缓存行更可能响应于后续高速缓存未命中而被驱逐在包含目标缓存行的同余类中。响应于随后的高速缓存未命中，目标高速缓存行被推出到较低级缓存，指示目标高速缓存行是处理器核心的先前释放请求的目标。

5. 发明申请

US20130262777A1 DATA CACHE BLOCK DEALLOCATE REQUESTS 有权
标题翻译：数据缓存块解析请求
公开(公告)号：US20130262777A1
公开(公告)日：2013-10-03
申请号：US13433022
申请日：2012-03-28
申请人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
发明人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/12
CPC分类号： G06F12/0815 , G06F12/0804 , G06F12/0817 , G06F12/0897 , G06F12/126
摘要： A data processing system includes a processor core supported by upper and lower level caches. In response to executing a deallocate instruction in the processor core, a deallocation request is sent from the processor core to the lower level cache, the deallocation request specifying a target address associated with a target cache line. In response to receipt of the deallocation request at the lower level cache, a determination is made if the target address hits in the lower level cache. In response to determining that the target address hits in the lower level cache, the target cache line is retained in a data array of the lower level cache and a replacement order field in a directory of the lower level cache is updated such that the target cache line is more likely to be evicted from the lower level cache in response to a subsequent cache miss.
摘要翻译：数据处理系统包括由上层和下层高速缓存支持的处理器核心。响应于在处理器核心中执行取消分配指令，从处理器核心向下级高速缓存发送解除分配请求，所述释放请求指定与目标高速缓存行相关联的目标地址。响应于在较低级别高速缓存处接收到解除分配请求，确定目标地址是否在较低级别高速缓存中。为了响应于确定目标地址在较低级别高速缓存中的命中，目标高速缓存行被保留在较低级别高速缓存的数据阵列中，并且更新下级高速缓存的目录中的替换顺序字段，使得目标高速缓存线路可能会响应于后续的高速缓存未命中而从较低级别的缓存中逐出。

6. 发明申请

US20080201533A1 REDUCING NUMBER OF REJECTED SNOOP REQUESTS BY EXTENDING TIME TO RESPOND TO SNOOP REQUEST 有权
标题翻译：通过延长时间减少违反SNOOP要求的数量以应对SNOOP要求
公开(公告)号：US20080201533A1
公开(公告)日：2008-08-21
申请号：US12114790
申请日：2008-05-04
申请人： Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0831
摘要： A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if the stall/reorder unit is not full. The entered snoop request is dispatched to a selector upon entering a bottom latch in the pipeline. The stall/reorder unit is not informed as to whether the dispatched snoop request is accepted by an arbitration mechanism for several clock cycles after the dispatch occurred. A copy of the dispatched snoop request is stored in a top latch in an overrun pipeline of latches in the first unit upon dispatching the snoop request. By maintaining information about the snoop request, the snoop request may be dispatched again to the selector in case the dispatched snoop request was rejected thereby increasing the chance that the snoop request will ultimately be accepted.
摘要翻译：用于减少拒绝的窥探请求数量的缓存，系统和方法。如果失速/重新排序单元未满，则在失速/重新排序单元中的锁存器管线中的第一可用锁存器中输入进入的窥探请求。输入的窥探请求在进入管道中的底部闩锁时被调度到选择器。失速/重新排序单元不知道发送后发送的几个时钟周期是否由仲裁机制接受发送的窥探请求。调度窥探请求的副本在调度窥探请求时被存储在第一单元中的锁存器的溢出管道中的顶部锁存器中。通过维护关于窥探请求的信息，可以在被发送的窥探请求被拒绝的情况下再次发送到选择器的窥探请求，从而增加窥探请求将最终被接受的机会。

7. 发明授权

US07386682B2 Reducing number of rejected snoop requests by extending time to respond to snoop request 有权
标题翻译：通过延长响应窥探请求的时间来减少被拒绝的窥探请求数
公开(公告)号：US07386682B2
公开(公告)日：2008-06-10
申请号：US11056764
申请日：2005-02-11
申请人： Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if the stall/reorder unit is not full. The entered snoop request is dispatched to a selector upon entering a bottom latch in the pipeline. The stall/reorder unit is not informed as to whether the dispatched snoop request is accepted by an arbitration mechanism for several clock cycles after the dispatch occurred. A copy of the dispatched snoop request is stored in a top latch in an overrun pipeline of latches in the first unit upon dispatching the snoop request. By maintaining information about the snoop request, the snoop request may be dispatched again to the selector in case the dispatched snoop request was rejected thereby increasing the chance that the snoop request will ultimately be accepted.
摘要翻译：用于减少拒绝的窥探请求数量的缓存，系统和方法。如果失速/重新排序单元未满，则在失速/重新排序单元中的锁存器管线中的第一可用锁存器中输入进入的窥探请求。输入的窥探请求在进入管道中的底部闩锁时被调度到选择器。失速/重新排序单元不知道发送后发送的几个时钟周期是否由仲裁机制接受发送的窥探请求。调度窥探请求的副本在调度窥探请求时被存储在第一单元中的锁存器的溢出管道中的顶部锁存器中。通过维护关于窥探请求的信息，可以在被发送的窥探请求被拒绝的情况下再次发送到选择器的窥探请求，从而增加窥探请求将最终被接受的机会。

8. 发明授权

US07523268B2 Reducing number of rejected snoop requests by extending time to respond to snoop request 有权
标题翻译：通过延长响应窥探请求的时间来减少被拒绝的窥探请求数
公开(公告)号：US07523268B2
公开(公告)日：2009-04-21
申请号：US12114790
申请日：2008-05-04
申请人： Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if the stall/reorder unit is not full. The entered snoop request is dispatched to a selector upon entering a bottom latch in the pipeline. The stall/reorder unit is not informed as to whether the dispatched snoop request is accepted by an arbitration mechanism for several clock cycles after the dispatch occurred. A copy of the dispatched snoop request is stored in a top latch in an overrun pipeline of latches in the first unit upon dispatching the snoop request. By maintaining information about the snoop request, the snoop request may be dispatched again to the selector in case the dispatched snoop request was rejected thereby increasing the chance that the snoop request will ultimately be accepted.
摘要翻译：用于减少拒绝的窥探请求数量的缓存，系统和方法。如果失速/重新排序单元未满，则在失速/重新排序单元中的锁存器管线中的第一可用锁存器中输入进入的窥探请求。输入的窥探请求在进入管道中的底部闩锁时被调度到选择器。失速/重新排序单元不知道发送后发送的几个时钟周期是否由仲裁机制接受发送的窥探请求。调度窥探请求的副本在调度窥探请求时被存储在第一单元中的锁存器的溢出管道中的顶部锁存器中。通过维护关于窥探请求的信息，可以在被发送的窥探请求被拒绝的情况下再次发送到选择器的窥探请求，从而增加窥探请求将最终被接受的机会。

9. 发明申请

US20100268884A1 Updating Partial Cache Lines in a Data Processing System 有权
标题翻译：更新数据处理系统中的部分缓存行
公开(公告)号：US20100268884A1
公开(公告)日：2010-10-21
申请号：US12424434
申请日：2009-04-15
申请人： David W. Cummings , Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams , Phillip G. Williams
发明人： David W. Cummings , Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0822 , G06F12/0897 , G06F2212/507
摘要： A processing unit for a data processing system includes a processor core having one or more execution units for processing instructions and a register file for storing data accessed in processing of the instructions. The processing unit also includes a multi-level cache hierarchy coupled to and supporting the processor core. The multi-level cache hierarchy includes at least one upper level of cache memory having a lower access latency and at least one lower level of cache memory having a higher access latency. The lower level of cache memory, responsive to receipt of a memory access request that hits only a partial cache line in the lower level cache memory, sources the partial cache line to the at least one upper level cache memory to service the memory access request. The at least one upper level cache memory services the memory access request without caching the partial cache line.
摘要翻译：用于数据处理系统的处理单元包括具有一个或多个用于处理指令的执行单元的处理器核心和用于存储在指令处理中访问的数据的寄存器文件。处理单元还包括耦合到并支持处理器核的多级高速缓存层级。多级高速缓存层级包括具有较低访问延迟的至少一个高级缓存存储器和具有较高访问延迟的至少一个较低级别的高速缓存存储器。响应于仅接收低级高速缓冲存储器中的部分高速缓存行的存储器访问请求的响应，较低级别的高速缓存存储器将部分高速缓存行源送到至少一个上级高速缓冲存储器以服务存储器访问请求。至少一个上级缓存存储器服务于存储器访问请求，而不缓存部分高速缓存行。

10. 发明授权

US08117390B2 Updating partial cache lines in a data processing system 有权
标题翻译：更新数据处理系统中的部分缓存行
公开(公告)号：US08117390B2
公开(公告)日：2012-02-14
申请号：US12424434
申请日：2009-04-15
申请人： David W. Cummings , Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams , Phillip G. Williams
发明人： David W. Cummings , Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F13/00
CPC分类号： G06F12/0822 , G06F12/0897 , G06F2212/507
摘要： A processing unit for a data processing system includes a processor core having one or more execution units for processing instructions and a register file for storing data accessed in processing of the instructions. The processing unit also includes a multi-level cache hierarchy coupled to and supporting the processor core. The multi-level cache hierarchy includes at least one upper level of cache memory having a lower access latency and at least one lower level of cache memory having a higher access latency. The lower level of cache memory, responsive to receipt of a memory access request that hits only a partial cache line in the lower level cache memory, sources the partial cache line to the at least one upper level cache memory to service the memory access request. The at least one upper level cache memory services the memory access request without caching the partial cache line.
摘要翻译：用于数据处理系统的处理单元包括具有一个或多个用于处理指令的执行单元的处理器核心和用于存储在指令处理中访问的数据的寄存器文件。处理单元还包括耦合到并支持处理器核的多级高速缓存层级。多级高速缓存层级包括具有较低访问延迟的至少一个高级缓存存储器和具有较高访问延迟的至少一个较低级别的高速缓存存储器。响应于仅接收低级高速缓冲存储器中的部分高速缓存行的存储器访问请求的响应，较低级别的高速缓存存储器将部分高速缓存行源送至至少一个上级高速缓冲存储器来服务存储器访问请求。至少一个上级缓存存储器服务于存储器访问请求，而不缓存部分高速缓存行。

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