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1. 发明授权

US08117390B2 Updating partial cache lines in a data processing system 有权
标题翻译：更新数据处理系统中的部分缓存行
公开(公告)号：US08117390B2
公开(公告)日：2012-02-14
申请号：US12424434
申请日：2009-04-15
申请人： David W. Cummings , Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams , Phillip G. Williams
发明人： David W. Cummings , Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F13/00
CPC分类号： G06F12/0822 , G06F12/0897 , G06F2212/507
摘要： A processing unit for a data processing system includes a processor core having one or more execution units for processing instructions and a register file for storing data accessed in processing of the instructions. The processing unit also includes a multi-level cache hierarchy coupled to and supporting the processor core. The multi-level cache hierarchy includes at least one upper level of cache memory having a lower access latency and at least one lower level of cache memory having a higher access latency. The lower level of cache memory, responsive to receipt of a memory access request that hits only a partial cache line in the lower level cache memory, sources the partial cache line to the at least one upper level cache memory to service the memory access request. The at least one upper level cache memory services the memory access request without caching the partial cache line.
摘要翻译：用于数据处理系统的处理单元包括具有一个或多个用于处理指令的执行单元的处理器核心和用于存储在指令处理中访问的数据的寄存器文件。处理单元还包括耦合到并支持处理器核的多级高速缓存层级。多级高速缓存层级包括具有较低访问延迟的至少一个高级缓存存储器和具有较高访问延迟的至少一个较低级别的高速缓存存储器。响应于仅接收低级高速缓冲存储器中的部分高速缓存行的存储器访问请求的响应，较低级别的高速缓存存储器将部分高速缓存行源送至至少一个上级高速缓冲存储器来服务存储器访问请求。至少一个上级缓存存储器服务于存储器访问请求，而不缓存部分高速缓存行。

2. 发明申请

US20100268884A1 Updating Partial Cache Lines in a Data Processing System 有权
标题翻译：更新数据处理系统中的部分缓存行
公开(公告)号：US20100268884A1
公开(公告)日：2010-10-21
申请号：US12424434
申请日：2009-04-15
申请人： David W. Cummings , Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams , Phillip G. Williams
发明人： David W. Cummings , Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0822 , G06F12/0897 , G06F2212/507
摘要： A processing unit for a data processing system includes a processor core having one or more execution units for processing instructions and a register file for storing data accessed in processing of the instructions. The processing unit also includes a multi-level cache hierarchy coupled to and supporting the processor core. The multi-level cache hierarchy includes at least one upper level of cache memory having a lower access latency and at least one lower level of cache memory having a higher access latency. The lower level of cache memory, responsive to receipt of a memory access request that hits only a partial cache line in the lower level cache memory, sources the partial cache line to the at least one upper level cache memory to service the memory access request. The at least one upper level cache memory services the memory access request without caching the partial cache line.
摘要翻译：用于数据处理系统的处理单元包括具有一个或多个用于处理指令的执行单元的处理器核心和用于存储在指令处理中访问的数据的寄存器文件。处理单元还包括耦合到并支持处理器核的多级高速缓存层级。多级高速缓存层级包括具有较低访问延迟的至少一个高级缓存存储器和具有较高访问延迟的至少一个较低级别的高速缓存存储器。响应于仅接收低级高速缓冲存储器中的部分高速缓存行的存储器访问请求的响应，较低级别的高速缓存存储器将部分高速缓存行源送到至少一个上级高速缓冲存储器以服务存储器访问请求。至少一个上级缓存存储器服务于存储器访问请求，而不缓存部分高速缓存行。

3. 发明授权

US08495308B2 Processor, data processing system and method supporting a shared global coherency state 失效
标题翻译：处理器，数据处理系统和支持共享全局一致性状态的方法
公开(公告)号：US08495308B2
公开(公告)日：2013-07-23
申请号：US11539694
申请日：2006-10-09
申请人： Guy L. Guthrie , William J. Starke , Derek E. Williams , Phillip G. Williams
发明人： Guy L. Guthrie , William J. Starke , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0817
摘要： A multiprocessor data processing system includes at least first and second coherency domains, where the first coherency domain includes a system memory and a cache memory. According to a method of data processing, a cache line is buffered in a data array of the cache memory and a state field in a cache directory of the cache memory is set to a coherency state to indicate that the cache line is valid in the data array, that the cache line is held in the cache memory non-exclusively, and that another cache in said second coherency domain may hold a copy of the cache line.
摘要翻译：多处理器数据处理系统至少包括第一和第二相干域，其中第一相干域包括系统存储器和高速缓冲存储器。根据数据处理的方法，将高速缓存行缓冲在高速缓冲存储器的数据阵列中，高速缓冲存储器的高速缓存目录中的状态字段被设置为一致性状态，以指示高速缓存行在数据中是有效的数组，高速缓存存储器行被非排他地保存在高速缓冲存储器中，并且所述第二相干域中的另一个高速缓冲存储器可以保存高速缓存行的副本。

4. 发明授权

US08135910B2 Bandwidth of a cache directory by slicing the cache directory into two smaller cache directories and replicating snooping logic for each sliced cache directory 有权
标题翻译：缓存目录的带宽通过将缓存目录分成两个较小的缓存目录，并为每个切片缓存目录复制侦听逻辑
公开(公告)号：US08135910B2
公开(公告)日：2012-03-13
申请号：US11056721
申请日：2005-02-11
申请人： Guy L. Guthrie , William J. Starke , Derek E. Williams , Phillip G. Williams
发明人： Guy L. Guthrie , William J. Starke , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0851
摘要： A cache, system and method for improving the snoop bandwidth of a cache directory. A cache directory may be sliced into two smaller cache directories each with its own snooping logic. By having two cache directories that can be accessed simultaneously, the bandwidth can be essentially doubled. Furthermore, a “frequency matcher” may shift the cycle speed to a lower speed upon receiving snoop addresses from the interconnect thereby slowing down the rate at which requests are transmitted to the dispatch pipelines. Each dispatch pipeline is coupled to a sliced cache directory and is configured to search the cache directory to determine if data at the received addresses is stored in the cache memory. As a result of slowing down the rate at which requests are transmitted to the dispatch pipelines and accessing the two sliced cache directories simultaneously, the bandwidth or throughput of the cache directory may be improved.
摘要翻译：用于提高缓存目录的窥探带宽的缓存，系统和方法。高速缓存目录可以分成两个较小的缓存目录，每个具有自己的侦听逻辑。通过具有可以同时访问的两个缓存目录，带宽可以基本上加倍。此外，当从互连接收到窥探地址时，“频率匹配器”可以将周期速度转移到较低速度，从而将请求发送到调度管线的速率减慢。每个调度流水线被耦合到一个切片缓存目录，并被配置为搜索该高速缓存目录以确定该接收到的地址上的数据是否被存储在该高速缓冲存储器中。作为将请求发送到调度管线的速度变慢并且同时访问两个分片缓存目录的结果，可以提高缓存目录的带宽或吞吐量。

5. 发明申请

US20100235576A1 Handling Castout Cache Lines In A Victim Cache 失效
标题翻译：在受害者缓存中处理Castout缓存行
公开(公告)号：US20100235576A1
公开(公告)日：2010-09-16
申请号：US12336048
申请日：2008-12-16
申请人： Guy L. Guthrie , Alvan W. Ng , Michael S. Siegel , William J. Starke , Derek E. Williams , Phillip G. Williams
发明人： Guy L. Guthrie , Alvan W. Ng , Michael S. Siegel , William J. Starke , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/127 , G06F12/0811 , G06F12/0862
摘要： A victim cache memory includes a cache array, a cache directory of contents of the cache array, and a cache controller that controls operation of the victim cache memory. The cache controller, responsive to receiving a castout command identifying a victim cache line castout from another cache memory, causes the victim cache line to be held in the cache array. If the other cache memory is a higher level cache in the cache hierarchy of the processor core, the cache controller marks the victim cache line in the cache directory so that it is less likely to be evicted by a replacement policy of the victim cache, and otherwise, marks the victim cache line in the cache directory so that it is more likely to be evicted by the replacement policy of the victim cache.
摘要翻译：受害者缓存存储器包括缓存阵列，高速缓存阵列的内容的高速缓存目录以及控制受害者缓存存储器的操作的高速缓存控制器。高速缓存控制器响应于从另一高速缓冲存储器接收识别受害者高速缓存线路突发的丢弃命令，使受害者高速缓存行保持在高速缓存阵列中。如果其他高速缓冲存储器是处理器核心的高速缓存层级中的较高级缓存，则高速缓存控制器将高速缓存目录中的受害者高速缓存行标记为不太可能被受害缓存的替换策略驱逐，否则，将缓存目录中的受害者缓存行标记为更有可能被受害者缓存的替换策略驱逐。

6. 发明申请

US20100153647A1 Cache-To-Cache Cast-In 失效
标题翻译：缓存到缓存注入
公开(公告)号：US20100153647A1
公开(公告)日：2010-06-17
申请号：US12335975
申请日：2008-12-16
申请人： Guy L. Guthrie , Alvan W. Ng , Michael S. Siegel , William J. Starke , Derek E. Williams , Phillip G. Williams
发明人： Guy L. Guthrie , Alvan W. Ng , Michael S. Siegel , William J. Starke , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0804 , G06F12/0831 , G06F12/0862
摘要： A data processing system includes a first processing unit and a second processing unit coupled by an interconnect fabric. The first processing unit has a first processor core and associated first upper and first lower level caches, and the second processing unit has a second processor core and associated second upper and lower level caches. In response to a data request, a victim cache line is selected for castout from the first lower level cache. The first processing unit issues on the interconnect fabric a lateral castout (LCO) command that identifies the victim cache line to be castout from the first lower level cache and indicates that a lower level cache is an intended destination. In response to a coherence response indicating success of the LCO command, the victim cache line is removed from the first lower level cache and held in the second lower level cache.
摘要翻译：数据处理系统包括由互连结构耦合的第一处理单元和第二处理单元。第一处理单元具有第一处理器核心和相关联的第一上部和第一下层高速缓存，并且第二处理单元具有第二处理器核心和相关联的第二上部和下部高速缓存。响应于数据请求，选择受害者高速缓存行用于从第一较低级别缓存进行舍弃。第一处理单元在互连结构上发出横向聚合（LCO）命令，该命令标识要从第一较低级缓存中抛出的受害缓存行，并且指示较低级缓存是预期目的地。响应于指示LCO命令的成功的一致性响应，从第一低级缓存中删除受害者高速缓存行并保存在第二较低级高速缓存中。

7. 发明授权

US08856455B2 Data cache block deallocate requests 有权
标题翻译：数据缓存块取消分配请求
公开(公告)号：US08856455B2
公开(公告)日：2014-10-07
申请号：US13433022
申请日：2012-03-28
申请人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
发明人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F12/0815 , G06F12/0804 , G06F12/0817 , G06F12/0897 , G06F12/126
摘要： A data processing system includes a processor core supported by upper and lower level caches. In response to executing a deallocate instruction in the processor core, a deallocation request is sent from the processor core to the lower level cache, the deallocation request specifying a target address associated with a target cache line. In response to receipt of the deallocation request at the lower level cache, a determination is made if the target address hits in the lower level cache. In response to determining that the target address hits in the lower level cache, the target cache line is retained in a data array of the lower level cache and a replacement order field in a directory of the lower level cache is updated such that the target cache line is more likely to be evicted from the lower level cache in response to a subsequent cache miss.
摘要翻译：数据处理系统包括由上层和下层高速缓存支持的处理器核心。响应于在处理器核心中执行取消分配指令，从处理器核心向下级高速缓存发送解除分配请求，所述释放请求指定与目标高速缓存行相关联的目标地址。响应于在较低级别高速缓存处接收到解除分配请求，确定目标地址是否在较低级别高速缓存中。为了响应于确定目标地址在较低级别高速缓存中的命中，目标高速缓存行被保留在较低级别高速缓存的数据阵列中，并且更新下级高速缓存的目录中的替换顺序字段，使得目标高速缓存线路可能会响应于后续的高速缓存未命中而从较低级别的缓存中逐出。

8. 发明申请

US20110161588A1 FORMATION OF AN EXCLUSIVE OWNERSHIP COHERENCE STATE IN A LOWER LEVEL CACHE 有权
标题翻译：在较低级别的高速缓存中形成独家所有权的相关状态
公开(公告)号：US20110161588A1
公开(公告)日：2011-06-30
申请号：US12649725
申请日：2009-12-30
申请人： Guy L. Guthrie , William J. Starke , Jeffrey Stuecheli , Derek E. Williams , Phillip G. Williams
发明人： Guy L. Guthrie , William J. Starke , Jeffrey Stuecheli , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0811 , G06F9/3834 , G06F12/0815 , G06F12/0831 , Y02D10/13
摘要： In response to a memory access request of a processor core that targets a target cache line, the lower level cache of a vertical cache hierarchy associated with the processor core supplies a copy of the target cache line to an upper level cache in the vertical cache hierarchy and retains a copy in a shared coherence state. The upper level cache holds the copy of the target cache line in a private shared ownership coherence state indicating that each cached copy of the target memory block is cached within the vertical cache hierarchy associated with the processor core. In response to the upper level cache signaling replacement of the copy of the target cache line in the private shared ownership coherence state, the lower level cache updates its copy of the target cache line to the exclusive ownership coherence state without coherency messaging with other vertical cache hierarchies.
摘要翻译：响应于针对目标高速缓存线的处理器核心的存储器访问请求，与处理器核心相关联的垂直高速缓存层级的较低级缓存将目标高速缓存行的副本提供给垂直高速缓存层级中的高级缓存并保留共享一致状态的副本。高级缓存将目标高速缓存行的副本保存在私有共享所有权一致状态中，指示目标存储器块的每个高速缓存副本被缓存在与处理器核心相关联的垂直高速缓存层级内。响应于在私有共享所有权相干状态下高级缓存信令替换目标高速缓存行的副本，下级缓存将其目标高速缓存行的副本更新为独占所有权相干状态，而不与其他垂直高速缓存的一致性消息传递层次结构。

9. 发明授权

US08874852B2 Data cache block deallocate requests in a multi-level cache hierarchy 有权
标题翻译：数据缓存块在多级缓存层次结构中释放请求
公开(公告)号：US08874852B2
公开(公告)日：2014-10-28
申请号：US13433048
申请日：2012-03-28
申请人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
发明人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/0804 , G06F12/121 , G06F12/122 , G06F12/126
摘要： In response to executing a deallocate instruction, a deallocation request specifying a target address of a target cache line is sent from a processor core to a lower level cache. In response, a determination is made if the target address hits in the lower level cache. If so, the target cache line is retained in a data array of the lower level cache, and a replacement order field of the lower level cache is updated such that the target cache line is more likely to be evicted in response to a subsequent cache miss in a congruence class including the target cache line. In response to the subsequent cache miss, the target cache line is cast out to the lower level cache with an indication that the target cache line was a target of a previous deallocation request of the processor core.
摘要翻译：响应于执行取消分配指令，将指定目标高速缓存行的目标地址的解除分配请求从处理器核发送到较低级高速缓存。作为响应，确定目标地址是否在较低级别高速缓存中。如果是这样，则目标高速缓存行被保留在较低级高速缓存的数据阵列中，并且更新较低级高速缓存的替换顺序字段，使得目标高速缓存行更可能响应于后续高速缓存未命中而被驱逐在包含目标缓存行的同余类中。响应于随后的高速缓存未命中，目标高速缓存行被推出到较低级缓存，指示目标高速缓存行是处理器核心的先前释放请求的目标。

10. 发明申请

US20130262777A1 DATA CACHE BLOCK DEALLOCATE REQUESTS 有权
标题翻译：数据缓存块解析请求
公开(公告)号：US20130262777A1
公开(公告)日：2013-10-03
申请号：US13433022
申请日：2012-03-28
申请人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
发明人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/12
CPC分类号： G06F12/0815 , G06F12/0804 , G06F12/0817 , G06F12/0897 , G06F12/126
摘要： A data processing system includes a processor core supported by upper and lower level caches. In response to executing a deallocate instruction in the processor core, a deallocation request is sent from the processor core to the lower level cache, the deallocation request specifying a target address associated with a target cache line. In response to receipt of the deallocation request at the lower level cache, a determination is made if the target address hits in the lower level cache. In response to determining that the target address hits in the lower level cache, the target cache line is retained in a data array of the lower level cache and a replacement order field in a directory of the lower level cache is updated such that the target cache line is more likely to be evicted from the lower level cache in response to a subsequent cache miss.
摘要翻译：数据处理系统包括由上层和下层高速缓存支持的处理器核心。响应于在处理器核心中执行取消分配指令，从处理器核心向下级高速缓存发送解除分配请求，所述释放请求指定与目标高速缓存行相关联的目标地址。响应于在较低级别高速缓存处接收到解除分配请求，确定目标地址是否在较低级别高速缓存中。为了响应于确定目标地址在较低级别高速缓存中的命中，目标高速缓存行被保留在较低级别高速缓存的数据阵列中，并且更新下级高速缓存的目录中的替换顺序字段，使得目标高速缓存线路可能会响应于后续的高速缓存未命中而从较低级别的缓存中逐出。

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