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1. 发明申请

US20130262778A1 DATA CACHE BLOCK DEALLOCATE REQUESTS IN A MULTI-LEVEL CACHE HIERARCHY 有权
标题翻译：数据缓存区块在多级高速缓存中调用请求
公开(公告)号：US20130262778A1
公开(公告)日：2013-10-03
申请号：US13433048
申请日：2012-03-28
申请人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
发明人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/12
CPC分类号： G06F12/0817 , G06F12/0804 , G06F12/121 , G06F12/122 , G06F12/126
摘要： In response to executing a deallocate instruction, a deallocation request specifying a target address of a target cache line is sent from a processor core to a lower level cache. In response, a determination is made if the target address hits in the lower level cache. If so, the target cache line is retained in a data array of the lower level cache, and a replacement order field of the lower level cache is updated such that the target cache line is more likely to be evicted in response to a subsequent cache miss in a congruence class including the target cache line. In response to the subsequent cache miss, the target cache line is cast out to the lower level cache with an indication that the target cache line was a target of a previous deallocation request of the processor core.
摘要翻译：响应于执行取消分配指令，将指定目标高速缓存行的目标地址的解除分配请求从处理器核发送到较低级高速缓存。作为响应，确定目标地址是否在较低级别高速缓存中。如果是这样，则目标高速缓存行被保留在较低级高速缓存的数据阵列中，并且更新较低级高速缓存的替换顺序字段，使得目标高速缓存行更可能响应于后续高速缓存未命中而被驱逐在包含目标缓存行的同余类中。响应于随后的高速缓存未命中，目标高速缓存行被推出到较低级缓存，指示目标高速缓存行是处理器核心的先前释放请求的目标。

2. 发明申请

US20070288694A1 DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING HAVING CONTROLLABLE STORE GATHER WINDOWS 审中-公开
标题翻译：数据处理系统，具有可控储存窗口的数据处理的处理器和方法
公开(公告)号：US20070288694A1
公开(公告)日：2007-12-13
申请号：US11423717
申请日：2006-06-13
申请人： Sanjeev Ghai , Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams
发明人： Sanjeev Ghai , Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F9/3824 , G06F9/3834
摘要： A data processing system includes a processor core and a memory subsystem coupled to the processor core. The memory subsystem includes data storage and a store queue including a plurality of entries for buffering store operations to be performed with reference to the data storage. The memory subsystem further includes a store queue controller that gathers multiple store requests received from the processor core into a single store operation buffered within an entry of the store queue. The store queue controller applies store gathering windows of differing durations to differing ones of the plurality of entries in response to control information received from the processor core.
摘要翻译：数据处理系统包括处理器核心和耦合到处理器核心的存储器子系统。存储器子系统包括数据存储器和存储队列，其包括用于缓冲要参考数据存储器执行的存储操作的多个条目。存储器子系统还包括存储队列控制器，其将从处理器核心接收的多个存储请求收集到缓冲在存储队列的条目内的单个存储操作中。存储队列控制器响应于从处理器核心接收到的控制信息，将具有不同持续时间的商店收集窗口应用到多个条目中的不同条目。

3. 发明授权

US07130967B2 Method and system for supplier-based memory speculation in a memory subsystem of a data processing system 失效
标题翻译：数据处理系统存储子系统中供应商内存推测的方法和系统
公开(公告)号：US07130967B2
公开(公告)日：2006-10-31
申请号：US10733948
申请日：2003-12-10
申请人： Ravi Kumar Arimilli , Sanjeev Ghai , Warren Edward Maule
发明人： Ravi Kumar Arimilli , Sanjeev Ghai , Warren Edward Maule
IPC分类号： G06F12/00
CPC分类号： G06F9/383 , G06F9/3832 , G06F9/3851 , G06F12/0215
摘要： A data processing system includes one or more processing cores, a system memory having multiple rows of data storage, and a memory controller that controls access to the system memory and performs supplier-based memory speculation. The memory controller includes a memory speculation table that stores historical information regarding prior memory accesses. In response to a memory access request, the memory controller directs an access to a selected row in the system memory to service the memory access request. The memory controller speculatively directs that the selected row will continue to be energized following the access based upon the historical information in the memory speculation table, so that access latency of an immediately subsequent memory access is reduced.
摘要翻译：数据处理系统包括一个或多个处理核心，具有多行数据存储的系统存储器，以及控制对系统存储器的访问并执行基于供应商的存储器推测的存储器控制器。存储器控制器包括存储有关先前存储器访问的历史信息的存储器推测表。响应于存储器访问请求，存储器控制器引导对系统存储器中的所选行的访问以服务存储器访问请求。存储器控制器推测地指示在基于存储器推测表中的历史信息的访问之后，所选择的行将继续被通电，使得紧随其后的存储器访问的访问等待时间减少。

4. 发明申请

US20050132147A1 Method and system for supplier-based memory speculation in a memory subsystem of a data processing system 失效
标题翻译：数据处理系统存储子系统中供应商内存推测的方法和系统
公开(公告)号：US20050132147A1
公开(公告)日：2005-06-16
申请号：US10733948
申请日：2003-12-10
申请人： Ravi Arimilli , Sanjeev Ghai , Warren Maule
发明人： Ravi Arimilli , Sanjeev Ghai , Warren Maule
IPC分类号： G06F12/08 , G06F9/38 , G06F12/00 , G06F12/02 , G06F12/06
CPC分类号： G06F9/383 , G06F9/3832 , G06F9/3851 , G06F12/0215
摘要： A data processing system includes one or more processing cores, a system memory having multiple rows of data storage, and a memory controller that controls access to the system memory and performs supplier-based memory speculation. The memory controller includes a memory speculation table that stores historical information regarding prior memory accesses. In response to a memory access request, the memory controller directs an access to a selected row in the system memory to service the memory access request. The memory controller speculatively directs that the selected row will continue to be energized following the access based upon the historical information in the memory speculation table, so that access latency of an immediately subsequent memory access is reduced.
摘要翻译：数据处理系统包括一个或多个处理核心，具有多行数据存储的系统存储器，以及控制对系统存储器的访问并执行基于供应商的存储器推测的存储器控制器。存储器控制器包括存储有关先前存储器访问的历史信息的存储器推测表。响应于存储器访问请求，存储器控制器引导对系统存储器中的所选行的访问以服务存储器访问请求。存储器控制器推测地指示在基于存储器推测表中的历史信息的访问之后，所选择的行将继续被通电，使得紧随其后的存储器访问的访问等待时间减少。

5. 发明授权

US06546469B2 Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers 失效
公开(公告)号：US06546469B2
公开(公告)日：2003-04-08
申请号：US09749328
申请日：2001-03-12
申请人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai , Guy Lynn Guthrie , Jody B. Joyner
发明人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai , Guy Lynn Guthrie , Jody B. Joyner
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A multiprocessor computer system in which snoop operations of the caches are synchronized to allow the issuance of a cache operation during a cycle which is selected based on the particular manner in which the caches have been synchronized. Each cache controller is aware of when these synchronized snoop tenures occur, and can target these cycles for certain types of requests that are sensitive to snooper retries, such as kill-type operations. The synchronization may set up a priority scheme for systems with multiple interconnect buses, or may synchronize the refresh cycles of the DRAM memory of the snooper's directory. In another aspect of the invention, windows are created during which a directory will not receive write operations (i.e., the directory is reserved for only read-type operations). The invention may be implemented in a cache hierarchy which provides memory arranged in banks, the banks being similarly synchronized. The invention is not limited to any particular type of instruction, and the synchronization functionality may be hardware or software programmable.

6. 发明授权

US06442653B1 Data processing system, cache, and method that utilize a coherency state to indicate the latency of cached data 失效
标题翻译：利用一致性状态来指示缓存数据的延迟的数据处理系统，缓存和方法
公开(公告)号：US06442653B1
公开(公告)日：2002-08-27
申请号：US09339403
申请日：1999-06-24
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai
IPC分类号： G06F1200
CPC分类号： G06F12/0815 , G06F12/127 , G06F2212/2542
摘要： A data processing system includes a processing unit, a distributed memory including a local memory and a remote memory having differing access latencies, and a cache coupled to the processing unit and to the distributed memory. The cache includes data storage and a plurality of latency indicators that each indicate an access latency to the distributed memory for associated data stored in the data storage. As a result, transactions related to cached data can be efficiently routed and addressed and efficient victim selection and deallocation policies can be implemented in the cache.
摘要翻译：数据处理系统包括处理单元，包括本地存储器的分布式存储器和具有不同访问延迟的远程存储器，以及耦合到处理单元和分布式存储器的高速缓存。高速缓存包括数据存储器和多个等待时间指示器，每个等待时间指示器指示分配的存储器对存储在数据存储器中的相关数据的访问等待时间。因此，可以有效地路由和寻址与缓存数据相关的事务，并且可以在缓存中实现有效的牺牲者选择和释放策略。

7. 发明授权

US06397303B1 Data processing system, cache, and method of cache management including an O state for memory-consistent cache lines 失效
标题翻译：数据处理系统，缓存和缓存管理方法，包括用于内存一致的缓存行的O状态
公开(公告)号：US06397303B1
公开(公告)日：2002-05-28
申请号：US09339408
申请日：1999-06-24
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai
IPC分类号： G06F1200
CPC分类号： G06F12/0811
摘要： A multiprocessor data processing system includes an interconnect, a plurality of processing units coupled to the interconnect, and at least one system memory and a plurality of caches coupled to the plurality of processing units. A cache suitable for use in such a data processing system includes data storage containing multiple granules of data and a number of state fields associated with the granules of data. Each state field has a plurality of possible states including an O state indicating that an associated granule is consistent with corresponding data in the memory and has unknown coherency with respect to peer caches in the data processing system. Thus, a cache is permitted to store memory-consistent, but possibly non-coherent data in order to offer processing units in the data processing system lower latency to an image of system memory.
摘要翻译：多处理器数据处理系统包括互连，耦合到互连的多个处理单元以及耦合到多个处理单元的至少一个系统存储器和多个高速缓存。适用于这种数据处理系统的高速缓存包括包含多个数据颗粒和与数据颗粒相关联的多个状态字段的数据存储。每个状态字段具有多个可能状态，包括指示相关联的粒子与存储器中的对应数据一致的O状态，并且与数据处理系统中的对等高速缓存具有未知的一致性。因此，缓存被允许存储内存一致但可能非相干的数据，以便为数据处理系统中的处理单元提供对系统存储器的图像的较低延迟。

8. 发明授权

US06356982B1 Dynamic mechanism to upgrade o state memory-consistent cache lines 有权
标题翻译：动态机制升级o状态内存一致的缓存行
公开(公告)号：US06356982B1
公开(公告)日：2002-03-12
申请号：US09339405
申请日：1999-06-24
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F12/0862
摘要： A multiprocessor data processing system includes an interconnect, a plurality of processing units coupled to the interconnect, and at least one system memory and a plurality of caches coupled to the plurality of processing units. A cache suitable for use in such a data processing system includes data storage containing a data granule, a state field associated with the data granule, and a cache controller. The state field has a plurality of possible states including a first state that indicates that the data granule is consistent with corresponding data in the memory and has unknown coherency with respect to other peer caches among the plurality of caches. To update the state of the data granule from the first state, the cache controller issues on the interconnect a transaction specifying an address associated with the data granule. In response to receipt of a combined response of the plurality of caches, the cache controller updates the state field to a second state among the plurality of possible states.
摘要翻译：多处理器数据处理系统包括互连，耦合到互连的多个处理单元以及耦合到多个处理单元的至少一个系统存储器和多个高速缓存。适用于这种数据处理系统的缓存包括包含数据粒子的数据存储器，与数据粒子相关联的状态字段以及高速缓存控制器。状态字段具有多个可能状态，包括指示数据粒子与存储器中的相应数据一致的第一状态，并且在多个高速缓存中相对于其他对等体高速缓存具有未知的一致性。为了从第一状态更新数据粒子的状态，高速缓存控制器在互连器上发出指定与数据粒子相关联的地址的事务。响应于接收到多个高速缓存的组合响应，高速缓存控制器将状态字段更新为多个可能状态中的第二状态。

9. 发明授权

US06349368B1 High performance mechanism to support O state horizontal cache-to-cache transfers 有权
标题翻译：高性能机制支持O状态的缓存到缓存的传输
公开(公告)号：US06349368B1
公开(公告)日：2002-02-19
申请号：US09339406
申请日：1999-06-24
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F12/0862
摘要： A multiprocessor data processing system includes an interconnect, a plurality of processing units coupled to the interconnect, and at least one system memory and a plurality of caches coupled to the plurality of processing units. A cache suitable for use in such a data processing system includes data storage containing multiple data granules and a number of state fields associated with the data granules. Each state field has a plurality of possible states including an OR state that indicates that an associated granule is consistent with corresponding data in the memory, that the associated data granule has unknown coherency with respect to other peer caches in the data processing system, and that the cache is responsible, among all of its peer caches that may store the associated data granule in a memory-consistent state with unknown coherency, for sourcing the data granule in response to a request.
摘要翻译：多处理器数据处理系统包括互连，耦合到互连的多个处理单元以及耦合到多个处理单元的至少一个系统存储器和多个高速缓存。适用于这种数据处理系统的高速缓存包括包含多个数据颗粒的数据存储和与数据颗粒相关联的多个状态字段。每个状态字段具有多个可能状态，包括指示相关联的粒子与存储器中的对应数据一致的OR状态，相关联的数据粒子相对于数据处理系统中的其他对等体高速缓存具有未知的一致性，并且高速缓存在其可以将关联的数据粒子存储在具有未知一致性的存储器一致状态中的所有对等高速缓存中负责，以响应于请求来采集数据粒子。

10. 发明授权

US06282615B1 Multiprocessor system bus with a data-less castout mechanism 失效
标题翻译：具有无数据丢弃机制的多处理器系统总线
公开(公告)号：US06282615B1
公开(公告)日：2001-08-28
申请号：US09437044
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai
IPC分类号： G06F1202
CPC分类号： G06F12/0811 , G06F12/0804
摘要： A method and apparatus for casting out data within a cache memory hierarchy for a data processing system is disclosed. The data processing system has multiple processing units, each of the processing units having a multi-level cache memory hierarchy. In response to a castout write request from a cache memory to a non-inclusive lower-level cache memory within a cache memory hierarchy, the data transfer is aborted if the lower-level cache memory already has a copy of the data of the castout write. The coherency state of the lower-level cache memory is then updated, if necessary.
摘要翻译：公开了一种用于在数据处理系统的高速缓存存储器层级内投出数据的方法和装置。数据处理系统具有多个处理单元，每个处理单元具有多级高速缓冲存储器层级。响应于从缓存存储器到高速缓存存储器层次结构内的非包容性低级高速缓冲存储器的丢弃写入请求，如果低级高速缓冲存储器已经具有写入数据的数据的副本，则中止数据传输。如果需要，则更新低级缓存的相关性状态。

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