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1. 发明授权

US6154498A Computer system with a semi-differential bus signaling scheme 失效
标题翻译：具有半差分总线信令方案的计算机系统
公开(公告)号：US6154498A
公开(公告)日：2000-11-28
申请号：US938359
申请日：1997-09-26
申请人： Sanjay Dabral , Dilip K. Sampath , Alper Ilkbahar
发明人： Sanjay Dabral , Dilip K. Sampath , Alper Ilkbahar
IPC分类号： G06F13/40 , H04L25/06 , H04L25/08 , H04B3/00 , H03K3/00 , H04L23/00 , H04L27/00
CPC分类号： G06F13/4072 , H04L25/06 , H04L25/085
摘要： A computer system with a semi-differential bus-signaling scheme is described. The computer system includes a transmitter coupled to a common bus. The transmitter sends clock signals and a data signal to logic-comparing devices within a receiver. The logic-comparing devices compare the data signal to a reference voltage while comparing the clock signals to each other. After the comparison, the clock signals can be used to capture the data into a retiming circuit.
摘要翻译：描述了具有半差分总线信令方案的计算机系统。计算机系统包括耦合到公共总线的发射器。发射机将时钟信号和数据信号发送到接收机内的逻辑比较装置。逻辑比较器件将数据信号与参考电压进行比较，同时将时钟信号彼此进行比较。比较后，可以使用时钟信号将数据捕获到重新定时电路中。

2. 发明授权

US6043682A Predriver logic circuit 失效
标题翻译：前驱逻辑电路
公开(公告)号：US6043682A
公开(公告)日：2000-03-28
申请号：US997223
申请日：1997-12-23
申请人： Sanjay Dabral , Dilip K. Sampath , Alper Ilkbahar
发明人： Sanjay Dabral , Dilip K. Sampath , Alper Ilkbahar
IPC分类号： H03K19/003 , H03K19/0175 , H03K19/094
CPC分类号： H03K19/00361
摘要： A buffer for enabling a signal to be applied to a bus. The buffer includes a first transistor coupled to a bus and a voltage supply. The logic buffer includes a first logic circuit which has an input coupled to receive a data signal and adapted to charge a terminal of the transistor at a first rate in response to a transition in the data signal. A second logic circuit charges the terminal at a faster rate during an initial transition period, until a first preselected condition is met. The buffer also includes a third logic circuit to charge the terminal at a second faster rate during a final transition period, after a second preselected condition is met. A method for controlling a voltage level of a signal applied to a terminal of a transistor includes charging the terminal at a fast rate until a first preselected condition is met. The terminal is then charged at a slower rate, until a second preselected condition is met, at which time the terminal is charged at a second fast rate, which is also greater than the slower rate.
摘要翻译：用于使信号施加到总线的缓冲器。缓冲器包括耦合到总线的第一晶体管和电压源。逻辑缓冲器包括第一逻辑电路，其具有耦合以接收数据信号的输入，并且适于响应于数据信号中的转变以第一速率对晶体管的端子充电。第二逻辑电路在初始过渡期间以更快的速率对终端充电，直到满足第一预选条件。缓冲器还包括第三逻辑电路，以在满足第二预选条件之后，在最后的过渡期期间以更快的速率对终端充电。用于控制施加到晶体管的端子的信号的电压电平的方法包括以快速的速率对端子充电直到满足第一预选条件。然后以较慢的速率对终端进行充电，直到满足第二预选条件，此时终端以第二快速率充电，其也大于较慢速率。

3. 发明授权

US06622256B1 System for protecting strobe glitches by separating a strobe signal into pointer path and timing path, filtering glitches from signals on pointer path thereof 失效
标题翻译：用于通过将选通信号分离为指针路径和定时路径来保护频闪毛刺的系统，从其指针路径上的信号滤除毛刺
公开(公告)号：US06622256B1
公开(公告)日：2003-09-16
申请号：US09539666
申请日：2000-03-30
申请人： Sanjay Dabral , Alper Ilkbahar
发明人： Sanjay Dabral , Alper Ilkbahar
IPC分类号： G06F104
CPC分类号： H03K5/1252 , H03K5/133 , H03L7/0805 , H03L7/0995 , H04L7/0008 , H04L7/0025 , H04L7/005
摘要： A method and apparatus for a strobe glitch protection mechanism for a source synchronous I/O link. One method of the present invention comprises separating a transfer clock having a plurality of transfer clock edges into a pointer path and a timing path. Glitches are filtered from signals on said pointer path. The pointer path and the timing path are coupled to generate latch enable signals to latch data bits.
摘要翻译：一种用于源同步I / O链路的选通脉冲干扰保护机制的方法和装置。本发明的一种方法包括将具有多个传送时钟边缘的传送时钟分离成指针路径和定时路径。毛刺从所述指针路径上的信号中滤除。指针路径和定时路径被耦合以产生锁存使能信号以锁存数据位。

4. 发明授权

US08143911B2 Input/output driver swing control and supply noise rejection 有权
标题翻译：输入/输出驱动器摆幅控制和电源噪声抑制
公开(公告)号：US08143911B2
公开(公告)日：2012-03-27
申请号：US12060251
申请日：2008-03-31
申请人： Zuoguo Wu , Feng Chen , Sanjay Dabral
发明人： Zuoguo Wu , Feng Chen , Sanjay Dabral
IPC分类号： H03K17/16 , H03K19/003 , H03K19/0175
CPC分类号： H04L25/0276
摘要： In general, in one aspect, the disclosure describes an apparatus having an averager to receive differential output voltages of a transmitter and generate an average transmitter output voltage. A comparator is to compare the average transmitter output voltage to a reference voltage and generate a difference therebetween. An integrator is to integrate the difference between the average transmitter output voltage and the reference voltage over time. The integrated difference is fed back to the transmitter to bias the transmitter.
摘要翻译：通常，在一个方面，本公开描述了一种具有平均器以接收发射机的差分输出电压并产生平均发射机输出电压的装置。比较器将平均发射机输出电压与参考电压进行比较，并产生它们之间的差值。积分器将整合平均发射机输出电压和参考电压随时间的差异。积分差值被反馈给发射机以偏置发射机。

5. 发明申请

US20120011276A1 Dynamically Modulating Link Width 有权
标题翻译：动态调节链路宽度
公开(公告)号：US20120011276A1
公开(公告)日：2012-01-12
申请号：US13240546
申请日：2011-09-22
申请人： Naveen Cherukuri , Aaron T. Spink , Phanindra Mannaya , Tim Frodsham , Jeffrey R. Wilcox , Sanjay Dabral , David Dunning , Theodore Z. Schoenborn
发明人： Naveen Cherukuri , Aaron T. Spink , Phanindra Mannaya , Tim Frodsham , Jeffrey R. Wilcox , Sanjay Dabral , David Dunning , Theodore Z. Schoenborn
IPC分类号： G06F15/173
CPC分类号： H04L67/141 , G06F13/4265 , H04L65/60 , Y02D10/14 , Y02D10/151
摘要： Systems and methods of managing a link provide for receiving a remote width capability during a link initialization, the remote width capability corresponding to a remote port. A link between a local port and the remote port is operated at a plurality of link widths in accordance with the remote width capability.
摘要翻译：管理链路的系统和方法提供了在链路初始化期间接收远程宽度能力，即对应于远程端口的远程宽度能力。根据远程宽度能力，本地端口和远程端口之间的链路以多个链路宽度进行操作。

6. 发明授权

US07907418B2 Circuit board including stubless signal paths and method of making same 有权
标题翻译：电路板包括无铅信号路径及其制作方法
公开(公告)号：US07907418B2
公开(公告)日：2011-03-15
申请号：US12628778
申请日：2009-12-01
申请人： Pascal Meier , Sanjay Dabral
发明人： Pascal Meier , Sanjay Dabral
IPC分类号： H05K7/00
CPC分类号： H05K3/4611 , H01L2224/16225 , H01L2924/15311 , H05K1/024 , H05K1/112 , H05K1/147 , H05K3/0064 , H05K3/4084 , H05K2201/091 , H05K2201/09318 , H05K2201/10734 , Y10T29/49126
摘要： A circuit board may include first and second sides, a plurality of circuit board layers between the sides, and a plurality of signal traces located in respective circuit board layers. The circuit board layers and the signal traces may extend from a first component connection region at the first side of the circuit board to a second component connection region at the first side of the circuit board. The signal traces may thus form stubless signal paths through the circuit board between the component connection regions. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
摘要翻译：电路板可以包括第一和第二侧，在侧面之间的多个电路板层和位于相应的电路板层中的多个信号迹线。电路板层和信号迹线可以从电路板的第一侧的第一部件连接区域延伸到电路板的第一侧的第二部件连接区域。因此，信号迹线可以在组件连接区域之间形成通过电路板的不连续的信号路径。当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。

7. 发明申请

US20080238588A1 Programmable passive equalizer 失效
标题翻译：可编程无源均衡器
公开(公告)号：US20080238588A1
公开(公告)日：2008-10-02
申请号：US12156532
申请日：2008-06-02
申请人： Evelina F. Yeung , Sanjay Dabral , Pascal Meier , Santanu Chaudhuri
发明人： Evelina F. Yeung , Sanjay Dabral , Pascal Meier , Santanu Chaudhuri
IPC分类号： H04B3/14
CPC分类号： H04B3/145
摘要： Embodiments of a programmable passive equalizer are described herein.
摘要翻译：本文描述了可编程无源均衡器的实施例。

8. 发明授权

US07394331B2 Programmable passive equalizer 有权
公开(公告)号：US07394331B2
公开(公告)日：2008-07-01
申请号：US11198111
申请日：2005-08-05
申请人： Evelina F Yeung , Sanjay Dabral , Pascal Meier , Santanu Chaudhuri
发明人： Evelina F Yeung , Sanjay Dabral , Pascal Meier , Santanu Chaudhuri
IPC分类号： H04B3/14
CPC分类号： H04B3/145
摘要： Embodiments of a programmable passive equalizer are described herein.

9. 发明授权

US07328359B2 Technique to create link determinism 有权
标题翻译：技术创造链接决定论
公开(公告)号：US07328359B2
公开(公告)日：2008-02-05
申请号：US10897225
申请日：2004-07-21
申请人： Tim Frodsham , Michael J. Tripp , David J. O'Brien , Muraleedhara Navada , Naveen Cherukuri , Sanjay Dabral , David S. Dunning , Theodore Z. Schoenborn
发明人： Tim Frodsham , Michael J. Tripp , David J. O'Brien , Muraleedhara Navada , Naveen Cherukuri , Sanjay Dabral , David S. Dunning , Theodore Z. Schoenborn
IPC分类号： G06F1/04 , G06F1/12 , G06F5/00 , G06F13/42 , H04L7/00
CPC分类号： G06F13/4273 , G06F5/06
摘要： A technique for promoting determinism among bus agents within a point-to-point (PtP) network. More particularly, embodiments of the invention relate to techniques to compensate for link latency, data skew, and clock shift within a PtP network of common system interface (CSI) bus agents.
摘要翻译：一种促进点对点（PtP）网络中总线代理之间确定性的技术。更具体地，本发明的实施例涉及补偿公共系统接口（CSI）总线代理的PtP网络内的链路延迟，数据偏移和时钟偏移的技术。

10. 发明授权

US07250333B2 Method of fabricating a linearized output driver and terminator 有权
标题翻译：制造线性化输出驱动器和终端器的方法
公开(公告)号：US07250333B2
公开(公告)日：2007-07-31
申请号：US10394977
申请日：2003-03-20
申请人： Sanjay Dabral , Krishna Seshan
发明人： Sanjay Dabral , Krishna Seshan
IPC分类号： H01L21/8234 , H01L21/8244
CPC分类号： H01L29/66659 , H01L29/7835 , Y02P80/30
摘要： A method and apparatus for a linearized output driver and terminator is described. In one embodiment the method includes forming a gate electrode on a substrate, the portion of the substrate covered by the gate electrode defining a channel. The method further includes forming a first source/drain doped region on laterally opposed sides of the gate electrode in the substrate. The method also includes forming a spacer on laterally opposed sides of the gate electrode on the substrate. The method also includes forming a linearized drain contact region at a location within the first source/drain doped region sufficiently distant from the gate electrode to define a series resistor in the first source/drain doped region disposed between the gate electrode and the linearized drain contact area based on an expected resistivity of the source/drain doped region, the series resistor coupled electrically to the channel.
摘要翻译：描述了用于线性化输出驱动器和终止器的方法和装置。在一个实施例中，该方法包括在衬底上形成栅电极，衬底的由栅电极覆盖的部分限定沟道。该方法还包括在衬底的栅电极的横向相对侧上形成第一源极/漏极掺杂区域。该方法还包括在基板上的栅电极的横向相对侧上形成间隔物。该方法还包括在与栅电极充分远的第一源极/漏极掺杂区域内的位置处形成线性化的漏极接触区域，以在布置在栅极电极和线性化漏极接触之间的第一源极/漏极掺杂区域中限定串联电阻器基于源极/漏极掺杂区域的预期电阻率的区域，串联电阻器电连接到沟道。

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