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1. 发明授权

US6154498A Computer system with a semi-differential bus signaling scheme 失效
标题翻译：具有半差分总线信令方案的计算机系统
公开(公告)号：US6154498A
公开(公告)日：2000-11-28
申请号：US938359
申请日：1997-09-26
申请人： Sanjay Dabral , Dilip K. Sampath , Alper Ilkbahar
发明人： Sanjay Dabral , Dilip K. Sampath , Alper Ilkbahar
IPC分类号： G06F13/40 , H04L25/06 , H04L25/08 , H04B3/00 , H03K3/00 , H04L23/00 , H04L27/00
CPC分类号： G06F13/4072 , H04L25/06 , H04L25/085
摘要： A computer system with a semi-differential bus-signaling scheme is described. The computer system includes a transmitter coupled to a common bus. The transmitter sends clock signals and a data signal to logic-comparing devices within a receiver. The logic-comparing devices compare the data signal to a reference voltage while comparing the clock signals to each other. After the comparison, the clock signals can be used to capture the data into a retiming circuit.
摘要翻译：描述了具有半差分总线信令方案的计算机系统。计算机系统包括耦合到公共总线的发射器。发射机将时钟信号和数据信号发送到接收机内的逻辑比较装置。逻辑比较器件将数据信号与参考电压进行比较，同时将时钟信号彼此进行比较。比较后，可以使用时钟信号将数据捕获到重新定时电路中。

2. 发明授权

US6043682A Predriver logic circuit 失效
标题翻译：前驱逻辑电路
公开(公告)号：US6043682A
公开(公告)日：2000-03-28
申请号：US997223
申请日：1997-12-23
申请人： Sanjay Dabral , Dilip K. Sampath , Alper Ilkbahar
发明人： Sanjay Dabral , Dilip K. Sampath , Alper Ilkbahar
IPC分类号： H03K19/003 , H03K19/0175 , H03K19/094
CPC分类号： H03K19/00361
摘要： A buffer for enabling a signal to be applied to a bus. The buffer includes a first transistor coupled to a bus and a voltage supply. The logic buffer includes a first logic circuit which has an input coupled to receive a data signal and adapted to charge a terminal of the transistor at a first rate in response to a transition in the data signal. A second logic circuit charges the terminal at a faster rate during an initial transition period, until a first preselected condition is met. The buffer also includes a third logic circuit to charge the terminal at a second faster rate during a final transition period, after a second preselected condition is met. A method for controlling a voltage level of a signal applied to a terminal of a transistor includes charging the terminal at a fast rate until a first preselected condition is met. The terminal is then charged at a slower rate, until a second preselected condition is met, at which time the terminal is charged at a second fast rate, which is also greater than the slower rate.
摘要翻译：用于使信号施加到总线的缓冲器。缓冲器包括耦合到总线的第一晶体管和电压源。逻辑缓冲器包括第一逻辑电路，其具有耦合以接收数据信号的输入，并且适于响应于数据信号中的转变以第一速率对晶体管的端子充电。第二逻辑电路在初始过渡期间以更快的速率对终端充电，直到满足第一预选条件。缓冲器还包括第三逻辑电路，以在满足第二预选条件之后，在最后的过渡期期间以更快的速率对终端充电。用于控制施加到晶体管的端子的信号的电压电平的方法包括以快速的速率对端子充电直到满足第一预选条件。然后以较慢的速率对终端进行充电，直到满足第二预选条件，此时终端以第二快速率充电，其也大于较慢速率。

3. 发明授权

US06192431B1 Method and apparatus for configuring the pinout of an integrated circuit 失效
标题翻译：用于配置集成电路的引脚分布的方法和装置
公开(公告)号：US06192431B1
公开(公告)日：2001-02-20
申请号：US09001550
申请日：1997-12-31
申请人： Sanjay Dabral , Dilip K. Sampath , Christopher Cheng
发明人： Sanjay Dabral , Dilip K. Sampath , Christopher Cheng
IPC分类号： G06F1000
CPC分类号： H05K1/181 , H01L23/50 , H01L2224/16 , H05K1/0298 , H05K2201/09309 , H05K2201/10545 , H05K2201/10689 , Y02P70/611
摘要： A method and apparatus for configuring the pinout of an integrated circuit. An integrated circuit includes an input/output structure including an input/output port. The input/output structure communicates a first signal in a first configuration and a second signal in a second configuration. The first and second signals are parallel signals of a bus.
摘要翻译：一种用于配置集成电路的引脚分布的方法和装置。集成电路包括包括输入/输出端口的输入/输出结构。输入/输出结构以第一配置传送第一信号和在第二配置中传送第二信号。第一和第二信号是总线的并行信号。

4. 发明授权

US5953521A Data-pattern induced skew reducer 失效
标题翻译：数据模式诱导偏斜减少器
公开(公告)号：US5953521A
公开(公告)日：1999-09-14
申请号：US962812
申请日：1997-11-03
申请人： Sanjay Dabral , Dilip K. Sampath
发明人： Sanjay Dabral , Dilip K. Sampath
IPC分类号： G06F5/06 , H04L7/02 , G06F13/38
CPC分类号： G06F5/06 , H04L7/02
摘要： The amount of skew present in a signal delivered over a transmission line is reduced by identifying of the type of data pattern from which a bit of data is being sent and generating a corresponding delay in response to identification of the data pattern is described. The generated delay results in reducing the amount of skew present in the system. In a first configuration, the invention includes first-storage and second-storage mechanisms, a logic gate, first and second delay paths, and a mechanisms for generating an output terminal. The first-storage mechanism stores a first digital signal. The second-storage mechanism stores a second digital signal that occurs in a selected number of clock transitions after the first data signal. The two storage mechanisms are connected to a logic gate. The first storage mechanism is also connected to the first and second delay paths which delay signals sent to them. A generating mechanism is connected to the delay paths and the logic gate and generates an output terminal signal in response to the selection of a digital signal from either the first or second delay path. A second configuration includes bypass circuitry coupled to the generating mechanism and the logic device.
摘要翻译：描述了通过传输线传送的信号中存在的偏斜量，通过识别从其发送数据位的数据模式的类型，并响应于数据模式的识别而产生相应的延迟来减少。产生的延迟导致减少系统中存在的偏斜量。在第一种配置中，本发明包括第一存储和第二存储机制，逻辑门，第一和第二延迟路径以及用于产生输出终端的机制。第一存储机构存储第一数字信号。第二存储机构存储在第一数据信号之后的选定数量的时钟转换中出现的第二数字信号。两个存储机制连接到逻辑门。第一存储机构还连接到延迟发送给它们的信号的第一和第二延迟路径。生成机构连接到延迟路径和逻辑门，并响应于来自第一或第二延迟路径的数字信号的选择而产生输出端信号。第二配置包括耦合到生成机构和逻辑设备的旁路电路。

5. 发明授权

US06336159B1 Method and apparatus for transferring data in source-synchronous protocol and transferring signals in common clock protocol in multiple agent processing system 失效
标题翻译：用于在多个代理处理系统中传送源同步协议中的数据并传输公共时钟协议中的信号的方法和装置
公开(公告)号：US06336159B1
公开(公告)日：2002-01-01
申请号：US09006322
申请日：1998-01-13
申请人： Peter D. MacWilliams , William S. Wu , Dilip K. Sampath , Bindi A. Prasad
发明人： Peter D. MacWilliams , William S. Wu , Dilip K. Sampath , Bindi A. Prasad
IPC分类号： G06F1342
CPC分类号： G06F13/385 , G06F13/4018 , G06F13/405
摘要： A method and apparatus for transferring data between bus agents in a computer system. The present invention includes transmitting a control signal, from a first agent to a second agent, via a first transfer protocol; and, transmitting data corresponding to the control signal, from the first agent to the second agent, via a second transfer protocol. In one embodiment, the control signals are transmitted from the first agent to the second agent via a synchronous transmission with respect to a bus clock; and, the data is transmitted via an asynchronous transmission with respect to the bus clock, which has a data width greater than the synchronous transmission. In addition, in one embodiment of the present invention, the synchronous transmission is a common clock data transfer protocol, and the asynchronous transmission is a source clock data transfer protocol.
摘要翻译：一种用于在计算机系统中的总线代理之间传送数据的方法和装置。本发明包括经由第一传输协议从第一代理向第二代理发送控制信号; 并且经由第二传送协议从第一代理向第二代理发送与控制信号相对应的数据。在一个实施例中，控制信号通过相对于总线时钟的同步传输从第一代理发送到第二代理; 并且相对于具有大于同步传输的数据宽度的总线时钟的异步传输来传送数据。此外，在本发明的一个实施例中，同步传输是公共时钟数据传输协议，异步传输是源时钟数据传输协议。

6. 发明授权

US06598103B2 Transmission of signals synchronous to a common clock and transmission of data synchronous to strobes in a multiple agent processing system 有权
公开(公告)号：US06598103B2
公开(公告)日：2003-07-22
申请号：US09991626
申请日：2001-11-06
申请人： Peter D. MacWilliams , William S. Wu , Dilip K. Sampath , Bindi A. Prasad
发明人： Peter D. MacWilliams , William S. Wu , Dilip K. Sampath , Bindi A. Prasad
IPC分类号： G06F1342
CPC分类号： G06F13/385 , G06F13/4018 , G06F13/405
摘要： A method and apparatus for transferring data between bus agents in a computer system. The present invention includes transmitting a control signal, from a first agent to a second agent, via a first transfer protocol; and, transmitting data corresponding to the control signal, from the first agent to the second agent, via a second transfer protocol. In one embodiment, the control signals are transmitted from the first agent to the second agent via a synchronous transmission with respect to a bus clock; and, the data is transmitted via an asynchronous transmission with respect to the bus clock, which has a data width greater than the synchronous transmission. In addition, in one embodiment of the present invention, the synchronous transmission is a common clock data transfer protocol, and the asynchronous transmission is a source clock data transfer protocol.

7. 发明授权

US5964856A Mechanism for data strobe pre-driving during master changeover on a parallel bus 失效
标题翻译：并行总线主转换期间数据选通预驱动的机制
公开(公告)号：US5964856A
公开(公告)日：1999-10-12
申请号：US940050
申请日：1997-09-30
申请人： William S. Wu , Leonard Schultz , Dilip K. Sampath , Muthurajan Jayakumar , Bindi A. Prasad
发明人： William S. Wu , Leonard Schultz , Dilip K. Sampath , Muthurajan Jayakumar , Bindi A. Prasad
IPC分类号： G06F13/42 , G06F13/14 , G06F1/04 , G06F13/00
CPC分类号： G06F13/4217
摘要： In a microprocessor system having a bus clock running at a bus clock rate, a method for reducing an idle interval between a first data transfer and a second data transfer, the method comprising the steps of:providing a first strobe signal and a second strobe signal for synchronizing said first and second data transfers with the bus clock;a pre-driving the first strobe signal before the first data transfer, the first strobe signal running at the bus clock rate during the first data transfer; andpre-driving one of the first and second strobe signals before the second data transfer, said one of the first and second strobe signals running at the bus clock rate during the second data transfer.
摘要翻译：在具有以总线时钟速率运行的总线时钟的微处理器系统中，一种用于减少第一数据传送和第二数据传送之间的空闲间隔的方法，所述方法包括以下步骤：提供第一选通信号和第二选通信号用于使所述第一和第二数据传输与所述总线时钟同步; 在所述第一数据传送之前预驱动所述第一选通信号，所述第一选通信号在所述第一数据传送期间以总线时钟速率运行; 以及在所述第二数据传送之前预驱动所述第一和第二选通信号之一，所述第一和第二选通信号之一在所述第二数据传送期间以总线时钟速率运行。

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