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1. 发明授权

US07677751B2 Hands free magnification eyewear 失效
标题翻译：手自由放大眼镜
公开(公告)号：US07677751B2
公开(公告)日：2010-03-16
申请号：US11598518
申请日：2006-11-13
申请人： William E. Kinsman , Robert E. O'Brien , David J. O'Brien
发明人： William E. Kinsman , Robert E. O'Brien , David J. O'Brien
IPC分类号： F21V21/084
CPC分类号： G02C7/08 , F21V21/0885 , F21V33/0048 , G02B25/02 , G02C11/04
摘要： A hands free magnification device is provided that is capable of illuminating an area adjacent the user. A method of use of the device is also provided.
摘要翻译：提供了能够照亮与用户相邻的区域的免提倍率装置。还提供了该装置的使用方法。

2. 发明授权

US06704892B1 Automated clock alignment for testing processors in a bypass mode 失效
标题翻译：以旁路模式测试处理器的自动时钟对齐
公开(公告)号：US06704892B1
公开(公告)日：2004-03-09
申请号：US09583268
申请日：2000-05-31
申请人： Nasser A. Kurd , Javed S. Barkatullah , Tim Frodsham , David J. O'Brien
发明人： Nasser A. Kurd , Javed S. Barkatullah , Tim Frodsham , David J. O'Brien
IPC分类号： G01R3128
CPC分类号： G06F11/27 , G01R31/31725 , G01R31/318594
摘要： In a bypass mode, a tester may bypass the core and input/output phase locked loops (PLLs) utilized by a processor to develop internal clock signals. External, tester-generated, phase shifted clock signals may be used to generate aligned high frequency signals to replace those generated by the phase locked loops. A plurality of phase shifted, tester generated clock signals may be subjected to an exclusive OR operation for generating input/output and core clock replacement signals. The clock signals received from the tester may also be aligned. Thus, a variety of skews may be compensated before entering the bypass mode. In some embodiments of the present invention, the core and I/O PLL clocks are used to establish alignment in a set-up phase and in other embodiments, the core and I/O PLL need not be utilized at all to generate appropriate internal clock signals from an external tester.
摘要翻译：在旁路模式下，测试人员可以绕过核心和处理器利用的输入/输出锁相环（PLL）来开发内部时钟信号。外部测试仪生成的相移时钟信号可用于产生对准的高频信号以代替由锁相环生成的信号。多个相移的测试仪产生的时钟信号可以经受用于产生输入/输出和核心时钟替换信号的异或运算。从测试仪接收的时钟信号也可以对齐。因此，在进入旁路模式之前可以补偿各种偏差。在本发明的一些实施例中，核心和I / O PLL时钟用于在建立阶段建立对准，在其它实施例中，核心和I / O PLL根本不需要被利用以产生适当的内部时钟来自外部测试仪的信号。

3. 发明授权

US06262585B1 Apparatus for I/O leakage self-test in an integrated circuit 有权
标题翻译：集成电路中用于I / O泄漏自检的装置
公开(公告)号：US06262585B1
公开(公告)日：2001-07-17
申请号：US09332758
申请日：1999-06-14
申请人： R. Tim Frodsham , David J. O'Brien
发明人： R. Tim Frodsham , David J. O'Brien
IPC分类号： G01R3102
CPC分类号： G01R31/3004 , G01R31/31715
摘要： According to one embodiment, an integrated circuit is disclosed that includes a first input/output (I/O) circuit and a leakage detection circuit coupled to the first I/O circuit. In a test mode of operation, the leakage detection circuit tests the first I/O circuit for excessive leakage current. According to another embodiment, the integrated circuit also includes a first resistor coupled between a line voltage and the first I/O circuit and a second resistor coupled between the first I/O circuit and ground. Further, the integrated circuit includes a second I/O circuit coupled to the leakage detection circuit and the first and second resistors. The leakage circuit also tests the second I/O circuit for excessive leakage current in the test mode of operation.
摘要翻译：根据一个实施例，公开了一种集成电路，其包括耦合到第一I / O电路的第一输入/输出（I / O）电路和泄漏检测电路。在测试操作模式下，漏电检测电路对第一个I / O电路进行了测试，以获得过大的漏电流。根据另一实施例，集成电路还包括耦合在线路电压和第一I / O电路之间的第一电阻器以及耦合在第一I / O电路和地之间的第二电阻器。此外，集成电路包括耦合到泄漏检测电路和第一和第二电阻器的第二I / O电路。泄漏电路还在测试操作模式下对第二个I / O电路进行过大的漏电流测试。

4. 发明授权

US07328359B2 Technique to create link determinism 有权
标题翻译：技术创造链接决定论
公开(公告)号：US07328359B2
公开(公告)日：2008-02-05
申请号：US10897225
申请日：2004-07-21
申请人： Tim Frodsham , Michael J. Tripp , David J. O'Brien , Muraleedhara Navada , Naveen Cherukuri , Sanjay Dabral , David S. Dunning , Theodore Z. Schoenborn
发明人： Tim Frodsham , Michael J. Tripp , David J. O'Brien , Muraleedhara Navada , Naveen Cherukuri , Sanjay Dabral , David S. Dunning , Theodore Z. Schoenborn
IPC分类号： G06F1/04 , G06F1/12 , G06F5/00 , G06F13/42 , H04L7/00
CPC分类号： G06F13/4273 , G06F5/06
摘要： A technique for promoting determinism among bus agents within a point-to-point (PtP) network. More particularly, embodiments of the invention relate to techniques to compensate for link latency, data skew, and clock shift within a PtP network of common system interface (CSI) bus agents.
摘要翻译：一种促进点对点（PtP）网络中总线代理之间确定性的技术。更具体地，本发明的实施例涉及补偿公共系统接口（CSI）总线代理的PtP网络内的链路延迟，数据偏移和时钟偏移的技术。

5. 发明授权

US07747888B2 Technique to create link determinism 有权
标题翻译：技术创造链接决定论
公开(公告)号：US07747888B2
公开(公告)日：2010-06-29
申请号：US11978849
申请日：2007-10-30
申请人： Tim Frodsham , Michael J. Tripp , David J. O'Brien , Muraleedhara Navada , Naveen Cherukuri , Sanjay Dabral , David S. Dunning , Theodore Z. Schoenborn
发明人： Tim Frodsham , Michael J. Tripp , David J. O'Brien , Muraleedhara Navada , Naveen Cherukuri , Sanjay Dabral , David S. Dunning , Theodore Z. Schoenborn
IPC分类号： G06F1/12 , G06F1/14
CPC分类号： G06F13/4273 , G06F5/06
摘要： A technique for promoting determinism among bus agents within a point-to-point (PtP) network. More particularly, embodiments of the invention relate to techniques to compensate for link latency, data skew, and clock shift within a PtP network of common system interface (CSI) bus agents.
摘要翻译：一种促进点对点（PtP）网络中总线代理之间确定性的技术。更具体地，本发明的实施例涉及补偿公共系统接口（CSI）总线代理的PtP网络内的链路延迟，数据偏移和时钟偏移的技术。

6. 发明申请

US20140156892A1 METHOD, SYSTEM, AND APPARATUS FOR LINK LATENCY MANAGEMENT 审中-公开
标题翻译：方法，系统和设备的链接延期管理
公开(公告)号：US20140156892A1
公开(公告)日：2014-06-05
申请号：US13913774
申请日：2013-06-10
申请人： Tim Frodsham , Michael J. Tripp , David J. O'Brien , Navada Herur Muraleedhara , Naveen Cherukuri , Sanjay Dabral , David S. Dunning , Theodore Z. Schoenborn
发明人： Tim Frodsham , Michael J. Tripp , David J. O'Brien , Navada Herur Muraleedhara , Naveen Cherukuri , Sanjay Dabral , David S. Dunning , Theodore Z. Schoenborn
IPC分类号： G06F1/06 , G06F13/362
CPC分类号： G06F1/06 , G06F13/362 , H04L43/50
摘要： A link latency management for a high-speed point-to-point network (pTp) is described The link latency management facilitates calculating latency of a serial interface by tracking a round trip delay of a header that contains latency information. Therefore, the link latency management facilitates testers, logic analyzers, or test devices to accurately measure link latency for a point-to-point architecture utilizing a serial interface.
摘要翻译：描述了用于高速点对点网络（pTp）的链路延迟管理。链路延迟管理有助于通过跟踪包含延迟信息的报头的往返延迟来计算串行接口的延迟。因此，链路延迟管理便于测试人员，逻辑分析仪或测试设备使用串行接口准确测量点对点架构的链路延迟。

7. 发明授权

US06477674B1 Method and apparatus for conducting input/output loop back tests using a local pattern generator and delay elements 有权
标题翻译：使用本地模式发生器和延迟元件进行输入/输出回路测试的方法和装置
公开(公告)号：US06477674B1
公开(公告)日：2002-11-05
申请号：US09474874
申请日：1999-12-29
申请人： Sarah E. Bates , R. Tim Frodsham , Nasser A. Kurd , Anne Meixner , David J. O'Brien , Rajay R. Pai , Mike Tripp , Jeff Wight
发明人： Sarah E. Bates , R. Tim Frodsham , Nasser A. Kurd , Anne Meixner , David J. O'Brien , Rajay R. Pai , Mike Tripp , Jeff Wight
IPC分类号： G06F1100
CPC分类号： G01R31/3187 , G01R31/31716
摘要： In one embodiment, an integrated circuit including a plurality of input/output (I/O) buffers is disclosed. The integrated circuit contains a plurality of I/O buffers. Each of the I/O buffers include an I/O test circuit that generates test pattern signals whenever the integrated circuit is operating in a loopback test mode. According to a further embodiment, the integrated circuit includes one or more programmable delay circuits coupled to the I/O buffers that permit switching state (AC) loopback timing tests to be conducted.
摘要翻译：在一个实施例中，公开了包括多个输入/输出（I / O）缓冲器的集成电路。集成电路包含多个I / O缓冲器。每个I / O缓冲器包括一个I / O测试电路，每当集成电路工作在环回测试模式时，它产生测试模式信号。根据另一实施例，集成电路包括耦合到I / O缓冲器的一个或多个可编程延迟电路，其允许进行开关状态（AC）环回定时测试。

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