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1. 发明申请

US20110316042A1 THYRISTOR RANDOM ACCESS MEMORY DEVICE AND METHOD 有权
公开(公告)号：US20110316042A1
公开(公告)日：2011-12-29
申请号：US12826323
申请日：2010-06-29
申请人： Sanh D. Tang , John K. Zahurak , Michael P. Violette
发明人： Sanh D. Tang , John K. Zahurak , Michael P. Violette
IPC分类号： H01L29/74 , H01L21/332
CPC分类号： H01L29/66363 , H01L27/1027 , H01L29/42308 , H01L29/74 , H01L2924/1301
摘要： Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.
摘要翻译：显示存储器件和制造存储器件的方法。所示的方法和配置提供用于增加存储器密度的折叠和垂直存储器件。提供的方法减少了对诸如深掺杂剂植入物的制造方法的需要。

2. 发明授权

US08535992B2 Thyristor random access memory device and method 有权
标题翻译：晶闸管随机存取存储器件及方法
公开(公告)号：US08535992B2
公开(公告)日：2013-09-17
申请号：US12826323
申请日：2010-06-29
申请人： Sanh D. Tang , John K. Zahurak , Michael P. Violette
发明人： Sanh D. Tang , John K. Zahurak , Michael P. Violette
IPC分类号： H01L21/322
CPC分类号： H01L29/66363 , H01L27/1027 , H01L29/42308 , H01L29/74 , H01L2924/1301
摘要： Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.
摘要翻译：显示存储器件和制造存储器件的方法。所示的方法和配置提供用于增加存储器密度的折叠和垂直存储器件。提供的方法减少了对诸如深掺杂剂植入物的制造方法的需要。

3. 发明申请

US20110316063A1 THREE DIMENSIONAL MEMORY AND METHODS OF FORMING THE SAME 有权
标题翻译：三维存储器及其形成方法
公开(公告)号：US20110316063A1
公开(公告)日：2011-12-29
申请号：US12825211
申请日：2010-06-28
申请人： Sanh D. Tang , John K. Zahurak
发明人： Sanh D. Tang , John K. Zahurak
IPC分类号： H01L29/78 , H01L21/82
CPC分类号： H01L27/11582 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C16/10 , G11C16/14 , G11C16/26 , G11C2213/71 , H01L21/28273 , H01L21/76838 , H01L23/528 , H01L27/0688 , H01L27/11519 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/11575 , H01L27/11578 , H01L27/2454 , H01L27/249 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926 , H01L45/06
摘要： Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.
摘要翻译：一些实施例包括存储器件和形成存储器件的方法。一个这样的存储器件包括第一组存储器单元，第一组的每个存储器单元形成在位于存储器件的一个器件级中的第一控制栅极的空腔中。存储器件还包括第二组存储器单元，第二组的每个存储器单元形成在位于存储器件的另一个器件级中的第二控制栅极的腔中。描述附加的装置和方法。

4. 发明授权

US08067286B2 Methods of forming recessed access devices associated with semiconductor constructions 有权
标题翻译：形成与半导体结构相关联的凹陷接入设备的方法
公开(公告)号：US08067286B2
公开(公告)日：2011-11-29
申请号：US13012675
申请日：2011-01-24
申请人： Kunal R. Parekh , Suraj J. Mathew , Jigish D. Trivedi , John K. Zahurak , Sanh D. Tang
发明人： Kunal R. Parekh , Suraj J. Mathew , Jigish D. Trivedi , John K. Zahurak , Sanh D. Tang
IPC分类号： H01L21/336
CPC分类号： H01L27/10876 , H01L27/10823
摘要： The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access device trenches, and source/drain regions are formed proximate the electrically conductive material. The electrically conductive material and source/drain regions together are incorporated into a pair of adjacent recessed access devices. After the recessed access device trenches are formed within the substrate, an isolation region trench is formed between the adjacent recessed access devices and filled with electrically insulative material to form a trenched isolation region.
摘要翻译：本发明包括形成凹入进入装置的方法。提供基板以在其中具有凹入的接入装置沟槽。一对凹进的接入设备沟槽彼此相邻。导电材料形成在凹进的存取装置沟槽内，源极/漏极区域靠近导电材料形成。导电材料和源极/漏极区域一起被并入一对相邻的凹进入器件中。在凹陷的访问设备沟槽形成在衬底内之后，在相邻的凹进的访问设备之间形成隔离区沟槽，并且填充有电绝缘材料以形成沟槽隔离区域。

5. 发明申请

US20080166856A1 Methods of Forming Recessed Access Devices Associated With Semiconductor Constructions 有权
标题翻译：形成与半导体结构相关的嵌入式接入设备的方法
公开(公告)号：US20080166856A1
公开(公告)日：2008-07-10
申请号：US12051620
申请日：2008-03-19
申请人： Kunal R. Parekh , Suraj Mathew , Jigish D. Trivedi , John K. Zahurak , Sanh D. Tang
发明人： Kunal R. Parekh , Suraj Mathew , Jigish D. Trivedi , John K. Zahurak , Sanh D. Tang
IPC分类号： H01L21/76
CPC分类号： H01L27/10876 , H01L27/10823
摘要： The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access device trenches, and source/drain regions are formed proximate the electrically conductive material. The electrically conductive material and source/drain regions together are incorporated into a pair of adjacent recessed access devices. After the recessed access device trenches are formed within the substrate, an isolation region trench is formed between the adjacent recessed access devices and filled with electrically insulative material to form a trenched isolation region.
摘要翻译：本发明包括形成凹入进入装置的方法。提供基板以在其中具有凹入的接入装置沟槽。一对凹进的接入设备沟槽彼此相邻。导电材料形成在凹进的存取装置沟槽内，源极/漏极区域靠近导电材料形成。导电材料和源极/漏极区域一起被并入一对相邻的凹进入器件中。在凹陷的访问设备沟槽形成在衬底内之后，在相邻的凹进的访问设备之间形成隔离区沟槽，并且填充有电绝缘材料以形成沟槽隔离区域。

6. 发明授权

US09252188B2 Methods of forming memory cells 有权
标题翻译：形成记忆细胞的方法
公开(公告)号：US09252188B2
公开(公告)日：2016-02-02
申请号：US13298840
申请日：2011-11-17
申请人： Sanh D. Tang , Scott E. Sills , John K. Zahurak
发明人： Sanh D. Tang , Scott E. Sills , John K. Zahurak
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/085 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/1233 , H01L45/14 , H01L45/148 , H01L45/16 , H01L45/1675
摘要： Some embodiments include methods of forming memory cells. A series of rails is formed to include bottom electrode contact material. Sacrificial material is patterned into a series of lines that cross the series of rails. A pattern of the series of lines is transferred into the bottom electrode contact material. At least a portion of the sacrificial material is subsequently replaced with top electrode material. Some embodiments include memory arrays that contain a second series of electrically conductive lines crossing a first series of electrically conductive lines. Memory cells are at locations where the electrically conductive lines of the second series overlap the electrically conductive lines of the first series. First and second memory cell materials are within the memory cell locations. The first memory cell material is configured as planar sheets and the second memory cell material is configured as upwardly-opening containers.
摘要翻译：一些实施例包括形成存储器单元的方法。形成一系列轨道以包括底部电极接触材料。牺牲材料被图案化成跨越一系列轨道的一系列线。一系列线的图案被转移到底部电极接触材料中。牺牲材料的至少一部分随后被顶部电极材料代替。一些实施例包括包含与第一系列导电线交叉的第二系列导电线的存储器阵列。存储单元位于第二系列的导电线与第一系列的导电线重叠的位置处。第一和第二存储单元材料位于存储单元位置内。第一存储单元材料被配置为平面片，并且第二存储单元材料被配置为向上开口的容器。

7. 发明授权

US08772848B2 Circuit structures, memory circuitry, and methods 有权
标题翻译：电路结构，存储器电路和方法
公开(公告)号：US08772848B2
公开(公告)日：2014-07-08
申请号：US13191293
申请日：2011-07-26
申请人： John K. Zahurak , Sanh D. Tang , Lars P. Heineck , Martin C. Roberts , Wolfgang Mueller , Haitao Liu
发明人： John K. Zahurak , Sanh D. Tang , Lars P. Heineck , Martin C. Roberts , Wolfgang Mueller , Haitao Liu
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/1203 , H01L21/84 , H01L23/528 , H01L27/092 , H01L27/10802 , H01L27/10823 , H01L27/10876 , H01L27/10894 , H01L27/10897 , H01L27/2454 , H01L29/36 , H01L29/66969 , H01L29/78 , H01L29/7827 , H01L29/7841 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/14 , H01L45/145 , H01L45/146 , H01L45/16 , H01L2924/0002 , H01L2924/00
摘要： A circuit structure includes a substrate having an array region and a peripheral region. The substrate in the array and peripheral regions includes insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor material over the conductive material. The array region includes vertical circuit devices which include the second semiconductor material. The peripheral region includes horizontal circuit devices which include the second semiconductor material. The horizontal circuit devices in the peripheral region individually have a floating body which includes the second semiconductor material. The conductive material in the peripheral region is under and electrically coupled to the second semiconductor material of the floating bodies. Conductive straps in the array region are under the vertical circuit devices. The conductive straps include the conductive material and individually are electrically coupled to a plurality of the vertical circuit devices in the array region. Other implementations are disclosed.
摘要翻译：电路结构包括具有阵列区域和周边区域的基板。阵列和外围区域中的衬底包括在第一半导体材料上的绝缘体材料，绝缘体材料上方的导电材料和导电材料上的第二半导体材料。阵列区域包括包括第二半导体材料的垂直电路器件。外围区域包括包括第二半导体材料的水平电路器件。外围区域中的水平电路器件分别具有包括第二半导体材料的浮体。外围区域中的导电材料在浮体的第二半导体材料的下面并电耦合。阵列区域中的导电带在垂直电路装置下方。导电带包括导电材料，并且单独地电耦合到阵列区域中的多个垂直电路器件。公开了其他实现。

8. 发明授权

US08546864B2 Three dimensional memory and methods of forming the same 有权
公开(公告)号：US08546864B2
公开(公告)日：2013-10-01
申请号：US12825211
申请日：2010-06-28
申请人： Sanh D. Tang , John K. Zahurak
发明人： Sanh D. Tang , John K. Zahurak
IPC分类号： H01L29/76 , G11C11/34 , G11C16/04
摘要： Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.

9. 发明申请

US20130011977A1 Floating Body Cell Structures, Devices Including Same, and Methods for Forming Same 有权
公开(公告)号：US20130011977A1
公开(公告)日：2013-01-10
申请号：US13609997
申请日：2012-09-11
申请人： Sanh D. Tang , John K. Zahurak , Werner Juengling
发明人： Sanh D. Tang , John K. Zahurak , Werner Juengling
IPC分类号： H01L21/336
CPC分类号： H01L27/10802 , H01L21/845 , H01L27/10826 , H01L27/10879 , H01L27/1211 , H01L29/4236 , H01L29/7841
摘要： Floating body cell structures including an array of floating body cells disposed on a back gate and source regions and drain regions of the floating body cells spaced apart from the back gate. The floating body cells may each include a volume of semiconductive material having a channel region extending between pillars, which may be separated by a void, such as a U-shaped trench. The floating body cells of the array may be electrically coupled to another gate, which may be disposed on sidewalls of the volume of semiconductive material or within the void therein. Methods of forming the floating body cell devices are also disclosed.

10. 发明申请

US20110215396A1 SEMICONDUCTOR CELLS, ARRAYS, DEVICES AND SYSTEMS HAVING A BURIED CONDUCTIVE LINE AND METHODS FOR FORMING THE SAME 有权
标题翻译：具有导电线的半导体电池，阵列，器件和系统及其形成方法
公开(公告)号：US20110215396A1
公开(公告)日：2011-09-08
申请号：US12715922
申请日：2010-03-02
申请人： Sanh D. Tang , John K. Zahurak
发明人： Sanh D. Tang , John K. Zahurak
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/762 , H01L21/32 , H01L27/0814 , H01L27/108 , H01L27/10808 , H01L27/2454 , H01L27/2472 , H01L29/66666 , H01L29/7827 , H01L29/861 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： Semiconductor arrays including a plurality of access devices disposed on a buried conductive line and methods for forming the same are provided. The access devices each include a transistor having a source region and drain region spaced apart by a channel region of opposite dopant type and an access line associated with the transistor. The access line may be electrically coupled with one or more of the transistors and may be operably coupled to a voltage source. The access devices may be formed in an array on one or more conductive lines. A system may be formed by integrating the semiconductor devices with one or more memory semiconductor arrays or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device.
摘要翻译：提供了包括设置在埋地导线上的多个访问装置的半导体阵列及其形成方法。接入装置各自包括具有由相反掺杂剂类型的沟道区域隔开的源极区域和漏极区域以及与该晶体管相关联的存取管线的晶体管。接入线路可以与一个或多个晶体管电耦合，并且可以可操作地耦合到电压源。访问设备可以以一个或多个导线上的阵列形成。可以通过将半导体器件与诸如互补金属氧化物半导体（CMOS）器件的一个或多个存储器半导体阵列或常规逻辑器件集成来形成系统。

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