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1. 发明申请

US20060084220A1 Differentially nitrided gate dielectrics in CMOS fabrication process 审中-公开
标题翻译： CMOS制造工艺中的差分氮化栅极电介质
公开(公告)号：US20060084220A1
公开(公告)日：2006-04-20
申请号：US10965963
申请日：2004-10-15
申请人： Sangwoo Lim , Paul Grudowski , Dejan Jovanovic , Choh-Fei Yeap
发明人： Sangwoo Lim , Paul Grudowski , Dejan Jovanovic , Choh-Fei Yeap
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/336
CPC分类号： H01L21/823857 , H01L21/823807
摘要： A semiconductor fabrication process includes forming a first plasma nitrided oxide (PNO) gate dielectric overlying a first region of a semiconductor substrate. A second PNO gate dielectric is formed overlying a second region of the substrate. The nitrogen concentration of the second PNO differs from the nitrogen concentration of the first PNO. A PMOS transistor is formed overlying the first substrate region and an NMOS transistor overlying the second substrate region. Prior to forming the first PNO gate dielectric, a mobility enhancing channel region may be formed overlying the first substrate region. Forming the mobility enhancing channel region may include forming a compressively stressed silicon germanium film overlying the first substrate region.
摘要翻译：半导体制造工艺包括形成覆盖在半导体衬底的第一区域上的第一等离子体氮化氧化物（PNO）栅极电介质。在衬底的第二区域上形成第二PNO栅极电介质。第二PNO的氮浓度与第一PNO的氮浓度不同。形成在第一衬底区域上方的PMOS晶体管和覆盖第二衬底区域的NMOS晶体管。在形成第一PNO栅极电介质之前，可以形成覆盖在第一衬底区域上的迁移率增强沟道区。形成迁移率增强沟道区域可以包括形成覆盖在第一衬底区域上的压缩应力的硅锗膜。

2. 发明申请

US20060223266A1 Method of forming an electronic device 有权
标题翻译：电子设备的形成方法
公开(公告)号：US20060223266A1
公开(公告)日：2006-10-05
申请号：US11098874
申请日：2005-04-05
申请人： Sangwoo Lim , Paul Grudowski , Mohamad Jahanbani , Hsing Tseng , Choh-Fei Yeap
发明人： Sangwoo Lim , Paul Grudowski , Mohamad Jahanbani , Hsing Tseng , Choh-Fei Yeap
IPC分类号： H01L21/8234
CPC分类号： H01L21/823462
摘要： A method of forming an electronic device includes etching a portion of a first gate dielectric layer to reduce a thickness of the gate dielectric layer within that portion. In one embodiment, portions not being etched may be covered by mask. In another embodiment, different portions may be etched during different times to give different thicknesses for the first gate dielectric layer. In a particular embodiment, a second gate dielectric layer may be formed over the first gate dielectric layer after etching the portion. The second gate dielectric layer can have a dielectric constant greater than the dielectric constant of the first gate dielectric layer. Subsequent gate electrode and source/drain region formation can be performed to form a transistor structure.
摘要翻译：一种形成电子器件的方法包括蚀刻第一栅极电介质层的一部分以减小该部分内的栅极电介质层的厚度。在一个实施例中，未被蚀刻的部分可以被掩模覆盖。在另一个实施例中，不同部分可以在不同时间被蚀刻，以给予第一栅极介电层不同的厚度。在特定实施例中，可以在蚀刻该部分之后在第一栅极电介质层上形成第二栅极电介质层。第二栅极介电层可以具有大于第一栅极介电层的介电常数的介电常数。可以进行随后的栅电极和源/漏区形成以形成晶体管结构。

3. 发明申请

US20070090455A1 Electronic device including transistor structures with sidewall spacers and a process for forming the electronic device 失效
标题翻译：电子器件包括具有侧壁间隔物的晶体管结构和用于形成电子器件的工艺
公开(公告)号：US20070090455A1
公开(公告)日：2007-04-26
申请号：US11258781
申请日：2005-10-26
申请人： Sangwoo Lim , Stanley Filipiak , Paul Grudowski , Venkat Kolagunta
发明人： Sangwoo Lim , Stanley Filipiak , Paul Grudowski , Venkat Kolagunta
IPC分类号： H01L29/76 , H01L21/8238 , H01L21/336 , H01L27/12 , H01L29/94 , H01L27/01 , H01L31/00 , H01L31/0392
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823864 , H01L21/823878 , H01L21/84 , H01L29/7843
摘要： An electronic device can include a first transistor structure including a first gate electrode surrounded by a first sidewall spacer having a first stress and a second transistor structure including a second gate electrode surrounding a second sidewall spacer having second stress. The first sidewall spacer is an only sidewall spacer surrounding the first gate electrode or a closer sidewall spacer as compared to any other sidewall spacer that surrounds the first gate electrode and the second sidewall spacer is an only sidewall spacer surrounding the second gate electrode or a closer sidewall spacer as compared to any other sidewall spacer that surrounds the second gate electrode, wherein the first stress has a lower value as compared to the second stress. More than one process can be used to form the electronic device.
摘要翻译：电子器件可以包括第一晶体管结构，其包括由具有第一应力的第一侧壁间隔物围绕的第一栅电极和包括围绕具有第二应力的第二侧壁间隔物的第二栅电极的第二晶体管结构。与围绕第一栅电极的任何其它侧壁间隔物相比，第一侧壁间隔物是围绕第一栅电极或更靠近的侧壁间隔物的唯一侧壁间隔物，并且第二侧壁间隔物是仅围绕第二栅电极的侧壁间隔物与围绕第二栅电极的任何其它侧壁间隔物相比，其中第一应力具有与第二应力相比较低的值。可以使用多个过程来形成电子设备。

4. 发明申请

US20060194423A1 Method of making a nitrided gate dielectric 失效
标题翻译：制造氮化栅极电介质的方法
公开(公告)号：US20060194423A1
公开(公告)日：2006-08-31
申请号：US11067257
申请日：2005-02-25
申请人： Sangwoo Lim , Paul Grudowski , Tien Luo , Olubunmi Adetutu , Hsing Tseng
发明人： Sangwoo Lim , Paul Grudowski , Tien Luo , Olubunmi Adetutu , Hsing Tseng
IPC分类号： H01L21/3205 , H01L21/31 , H01L21/336
CPC分类号： H01L21/02329 , H01L21/02181 , H01L21/0234 , H01L21/28185 , H01L21/28202 , H01L21/3141 , H01L21/3144 , H01L21/3185 , H01L29/4908 , H01L29/511 , H01L29/6659 , H01L29/7833
摘要： A gate dielectric is treated with a nitridation step and an anneal. After this, an additional nitridation step and anneal is performed. The second nitridation and anneal results in an improvement in the relationship between gate leakage current density and current drive of the transistors that are ultimately formed.
摘要翻译：用氮化步骤和退火处理栅极电介质。之后，进行另外的氮化步骤和退火。第二次氮化和退火导致栅极漏电流密度与最终形成的晶体管的电流驱动之间的关系得到改善。

5. 发明申请

US20070197011A1 Method for improving self-aligned silicide extendibility with spacer recess using a stand-alone recess etch integration 审中-公开
标题翻译：使用独立凹陷蚀刻集成来改善具有间隔凹槽的自对准硅化物扩展性的方法
公开(公告)号：US20070197011A1
公开(公告)日：2007-08-23
申请号：US11360318
申请日：2006-02-22
申请人： Anadi Srivastava , Paul Grudowski , Dharmesh Jawarani , Rode Mora
发明人： Anadi Srivastava , Paul Grudowski , Dharmesh Jawarani , Rode Mora
IPC分类号： H01L21/4763 , H01L21/3205
CPC分类号： H01L21/76895 , H01L21/28052 , H01L29/665 , H01L29/6653
摘要： A method is provided for making a silicided gate (209). In accordance with the method, a semiconductor substrate (202) is provided which has a gate (209) disposed thereon and which has a spacer (219) disposed adjacent to the gate. The spacer is subjected to a recess etch which exposes a lateral portion of the gate. An implant region (215) is then created adjacent to the spacer, and a layer of silicide (225) is formed which extends over the exposed lateral portion of the gate.
摘要翻译：提供了一种制造硅化栅（209）的方法。根据该方法，提供一种半导体衬底（202），其具有设置在其上的栅极（209），并且具有邻近栅极设置的间隔物（219）。间隔件进行凹口蚀刻，露出栅极的侧面部分。然后在间隔物附近产生注入区域（215），并且形成一层硅化物（225），其在栅极的暴露侧面部分上延伸。

6. 发明申请

US20050156237A1 Transistor sidewall spacer stress modulation 有权
标题翻译：晶体管侧壁间隔应力调制
公开(公告)号：US20050156237A1
公开(公告)日：2005-07-21
申请号：US11036859
申请日：2005-01-13
申请人： Paul Grudowski
发明人： Paul Grudowski
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/26586 , H01L21/823468 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7835 , H01L29/7842 , Y10S257/90
摘要： A semiconductor fabrication process and the resulting integrated circuit include forming a gate electrode (116) over a gate dielectric (104) over a semiconductor substrate (102). A spacer film (124) exhibiting a tensile stress characteristic is deposited over the gate electrode (116). The stress characteristics of at least a portion of the spacer film is then modulated (132, 192) and the spacer film (124) is etched to form sidewall spacers (160, 162) on the gate electrode sidewalls. The spacer film (124) is an LPCVD silicon nitride in one embodiment. Modulating (132) the spacer film (124) includes implanting Xenon or Germanium into the spacers (160) at an implant energy sufficient to break at least some of the silicon nitride bonds. The modulation implant (132) may be performed selectively or non-selectively either before or after etching the spacer film (124).
摘要翻译：半导体制造工艺和所得到的集成电路包括在半导体衬底（102）上方的栅电介质（104）上形成栅电极（116）。表现出拉伸应力特性的间隔膜（124）沉积在栅电极（116）上。然后对间隔膜的至少一部分的应力特性进行调制（132,192），并且蚀刻间隔膜（124）以在栅极电极侧壁上形成侧壁间隔物（160,162）。在一个实施例中，间隔膜（124）是LPCVD氮化硅。调节（132）间隔膜（124）包括以足以破坏至少一些氮化硅键的注入能量将氙或锗注入到间隔物（160）中。调制植入物（132）可以在蚀刻间隔膜（124）之前或之后选择性地或非选择地进行。

7. 发明申请

US20050156229A1 Integrated circuit device and method therefor 审中-公开
公开(公告)号：US20050156229A1
公开(公告)日：2005-07-21
申请号：US11014661
申请日：2004-12-16
申请人： Geoffrey Yeap , Srinivas Jallepalli , Yongjoo Jeon , James Burnett , Rana Singh , Paul Grudowski
发明人： Geoffrey Yeap , Srinivas Jallepalli , Yongjoo Jeon , James Burnett , Rana Singh , Paul Grudowski
IPC分类号： H01L21/336 , H01L21/8239 , H01L21/8247 , H01L27/105 , H01L29/76 , H01L29/78
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/1052 , H01L27/11541 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/7833
摘要： A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.

8. 发明申请

US20070218661A1 Undoped gate poly integration for improved gate patterning and cobalt silicide extendibility 失效
标题翻译：未掺杂的栅极聚合，用于改进栅极图案化和硅化钴可扩展性
公开(公告)号：US20070218661A1
公开(公告)日：2007-09-20
申请号：US11375768
申请日：2006-03-15
申请人： Mehul Shroff , Paul Grudowski , Mark Hall , Tab Stephens
发明人： Mehul Shroff , Paul Grudowski , Mark Hall , Tab Stephens
IPC分类号： H01L21/04
CPC分类号： H01L21/82345 , H01L21/823418 , H01L21/823456 , H01L21/823462
摘要： A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch an intrinsic polysilicon layer (26) formed over a substrate (11), thereby forming etched gates (62, 64) having vertical sidewall profiles (61, 63). While a blanket nitrogen implant (46) of the intrinsic polysilicon layer (26) may occur prior to gate etch, more idealized vertical gate sidewall profiles (61, 63) are obtained by fully doping the gates (80, 100) during the source/drain implantation steps (71, 77, 91, 97) and after the gate etch.
摘要翻译：半导体工艺和设备使用预定的图案化和蚀刻步骤序列来蚀刻在衬底（11）上形成的本征多晶硅层（26），从而形成具有垂直侧壁轮廓（61,63）的蚀刻栅极（62,64）。虽然本征多晶硅层（26）的覆盖氮氮注入（46）可以在栅极蚀刻之前发生，但是在源极/漏极中通过完全掺杂栅极（80,100）来获得更理想化的垂直栅极侧壁轮廓（61,63）漏极注入步骤（71,77,91,97）和栅极蚀刻之后。

9. 发明申请

US20070132031A1 Semiconductor device having stressors and method for forming 有权
标题翻译：具有应力源的半导体器件及其形成方法
公开(公告)号：US20070132031A1
公开(公告)日：2007-06-14
申请号：US11300091
申请日：2005-12-14
申请人： Mehul Shroff , Paul Grudowski
发明人： Mehul Shroff , Paul Grudowski
IPC分类号： H01L29/94
CPC分类号： H01L29/7843 , H01L21/3185 , H01L21/76802 , H01L21/76829 , H01L21/823807 , H01L21/823864 , H01L21/823871 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： N channel and P channel transistors are enhanced by applying stressor layers of tensile and compressive, respectively, over them. A previously unknown problem was discovered concerning the two stressor layers, which both may conveniently be nitride but made somewhat differently. The two stressors have different etch rates which results in deleterious effects when etching a contact hole at the interface between the two stressors. A contact to a gate is often preferably half way between N and P channel transistors which is also the seemingly best location for the border between the two stressor layers. The contact etch at the border can result in pitting of the underlying gate structure or in residual nitride in the contact hole. Therefore, it has been found beneficial to ensure that each contact is at least some predetermined distance from the stressor of the opposite type from the one the contact is passing through.
摘要翻译：通过在其上分别施加拉伸和压缩的应力层来增强N沟道和P沟道晶体管。发现关于两个应力层的以前未知的问题，这两个应力层都可以方便地是氮化的，但是略有不同。两个应力源具有不同的蚀刻速率，这在蚀刻两个应力源之间的界面处的接触孔时会产生有害影响。与栅极的接触通常优选在N沟道晶体管和P沟道晶体管之间，这也是两个应力层之间边界的看似最佳位置。在边界处的接触蚀刻可导致底层栅极结构或接触孔中的残余氮化物的点蚀。因此，已经发现有益的是确保每个接触件与来自接触件通过的相反类型的应力器至少一定的距离。

10. 发明申请

US20070202651A1 Semiconductor process integrating source/drain stressors and interlevel dielectric layer stressors 失效
标题翻译：集成源极/漏极应力和半导体介电层应力的半导体工艺
公开(公告)号：US20070202651A1
公开(公告)日：2007-08-30
申请号：US11361171
申请日：2006-02-24
申请人： Da Zhang , Vance Adams , Bich-Yen Nguyen , Paul Grudowski
发明人： Da Zhang , Vance Adams , Bich-Yen Nguyen , Paul Grudowski
IPC分类号： H01L21/336
CPC分类号： H01L29/7846 , H01L29/165 , H01L29/66636 , H01L29/66772 , H01L29/7843 , H01L29/7848 , H01L29/78654
摘要： A semiconductor fabrication process includes forming isolation structures on either side of a transistor region, forming a gate structure overlying the transistor region, removing source/drain regions to form source/drain recesses, removing portions of the isolation structures to form recessed isolation structures, and filling the source/drain recesses with a source/drain stressor such as an epitaxially formed semiconductor. A lower surface of the source/drain recess is preferably deeper than an upper surface of the recessed isolation structure by approximately 10 to 30 nm. Filling the source/drain recesses may precede or follow forming the recessed isolation structures. An ILD stressor is then deposited over the transistor region such that the ILD stressor is adjacent to sidewalls of the source/drain structure thereby coupling the ILD stressor to the source/drain stressor. The ILD stressor is preferably compressive or tensile silicon nitride and the source/drain structure is preferably silicon germanium or silicon carbon.
摘要翻译：半导体制造工艺包括在晶体管区域的任一侧上形成隔离结构，形成覆盖晶体管区域的栅极结构，去除源极/漏极区域以形成源极/漏极凹部，去除隔离结构的部分以形成凹入的隔离结构;以及用诸如外延形成的半导体的源极/漏极应力源填充源/漏极凹部。源极/漏极凹部的下表面优选比凹入的隔离结构的上表面深大约10至30nm。填充源极/漏极凹部可以在形成凹入的隔离结构之前或之后。然后将ILD应激源沉积在晶体管区域上，使得ILD应力源与源极/漏极结构的侧壁相邻，从而将ILD应激源耦合到源极/漏极应力源。 ILD应力器优选为压缩或拉伸氮化硅，并且源极/漏极结构优选为硅锗或硅碳。

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