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1. 发明申请

US20050156229A1 Integrated circuit device and method therefor 审中-公开
公开(公告)号：US20050156229A1
公开(公告)日：2005-07-21
申请号：US11014661
申请日：2004-12-16
申请人： Geoffrey Yeap , Srinivas Jallepalli , Yongjoo Jeon , James Burnett , Rana Singh , Paul Grudowski
发明人： Geoffrey Yeap , Srinivas Jallepalli , Yongjoo Jeon , James Burnett , Rana Singh , Paul Grudowski
IPC分类号： H01L21/336 , H01L21/8239 , H01L21/8247 , H01L27/105 , H01L29/76 , H01L29/78
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/1052 , H01L27/11541 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/7833
摘要： A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.

2. 发明申请

US20060079047A1 Integration of multiple gate dielectrics by surface protection 有权
标题翻译：通过表面保护集成多个栅极电介质
公开(公告)号：US20060079047A1
公开(公告)日：2006-04-13
申请号：US10962944
申请日：2004-10-12
申请人： Sangwoo Lim , Laegu Kang , Geoffrey Yeap
发明人： Sangwoo Lim , Laegu Kang , Geoffrey Yeap
IPC分类号： H01L21/8238 , H01L21/31
CPC分类号： H01L21/823462
摘要： A multiple gate oxidation process is provided. The process comprises the steps of (a) providing a silicon substrate (203) having a sacrificial oxide layer (207) thereon; (b) depositing and patterning a first layer of photoresist (209) on the sacrificial oxide layer, thereby forming a first region in which the sacrificial oxide layer is exposed; (c) etching the exposed sacrificial oxide layer within the first region, thereby forming a first etched region; (d) growing a first oxide layer (211) within the first etched region; (e) depositing and patterning a second layer of photoresist (213) on the sacrificial oxide layer and first oxide layer, thereby forming a second region in which the sacrificial oxide layer is exposed; (f) etching the exposed sacrificial oxide layer within the second region, thereby forming a second etched region; and (g) growing a second oxide layer (215) within the second etched region.
摘要翻译：提供多栅极氧化工艺。该方法包括以下步骤：（a）提供其上具有牺牲氧化物层（207）的硅衬底（203）; （b）在所述牺牲氧化物层上沉积和图案化第一层光致抗蚀剂（209），从而形成其中暴露所述牺牲氧化物层的第一区域; （c）蚀刻第一区域内的暴露的牺牲氧化物层，由此形成第一蚀刻区域; （d）在第一蚀刻区域内生长第一氧化物层（211）; （e）在所述牺牲氧化物层和所述第一氧化物层上沉积和图案化第二层光致抗蚀剂（213），从而形成其中暴露所述牺牲氧化物层的第二区域; （f）蚀刻第二区域内的暴露的牺牲氧化物层，从而形成第二蚀刻区域; 和（g）在第二蚀刻区域内生长第二氧化物层（215）。

3. 发明授权

US5960322A Suppression of boron segregation for shallow source and drain junctions in semiconductors 失效
标题翻译：抑制半导体中浅源极和漏极结的硼偏析
公开(公告)号：US5960322A
公开(公告)日：1999-09-28
申请号：US994308
申请日：1997-12-19
申请人： Qi Xiang , Geoffrey Yeap , Srinath Krishnan , Ming-Ren Lin
发明人： Qi Xiang , Geoffrey Yeap , Srinath Krishnan , Ming-Ren Lin
IPC分类号： H01L21/265 , H01L21/336 , H01L21/31 , H01L21/469
CPC分类号： H01L29/6659 , H01L21/2652 , H01L29/6656 , Y10S438/917
摘要： A method in the manufacture of ultra-large scale integrated circuit semiconductor devices suppresses boron loss due to segregation into the screen oxide during the boron activation rapid thermal anneal. A nitridation of the screen oxide is used to incorporate nitrogen into the screen oxide layer prior to boron implantation for ultra-shallow, source and drain extension junctions. A second nitridation of a second screen oxide is used prior to boron implantation for deeper, source and drain junctions. This method significantly suppresses boron diffusion and segregation away from the silicon substrate which reduces series resistance of the complete source and drain junctions.
摘要翻译：制造超大规模集成电路半导体器件的方法抑制了硼激活快速热退火期间由于偏析到屏幕氧化物中的硼损失。在用于超浅，源极和漏极延伸结的硼注入之前，使用屏幕氧化物的氮化将氮掺入屏幕氧化物层中。在硼注入之前，使用第二屏蔽氧化物的第二次氮化用于更深，源极和漏极结。该方法显着抑制了硼扩散和离开硅衬底的偏析，从而降低了整个源极和漏极结的串联电阻。

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