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1. 发明授权

US07855926B2 Semiconductor memory device having local sense amplifier with on/off control 有权
标题翻译：具有开/关控制的本地读出放大器的半导体存储器件
公开(公告)号：US07855926B2
公开(公告)日：2010-12-21
申请号：US11188184
申请日：2005-07-20
申请人： Sang-Woong Shin , Chul-Soo Kim , Young-Hyun Jun , Sang-Bo Lee
发明人： Sang-Woong Shin , Chul-Soo Kim , Young-Hyun Jun , Sang-Bo Lee
IPC分类号： G11C7/00 , G11C7/02
CPC分类号： G11C7/06 , G11C11/4091 , G11C2207/005 , G11C2207/065
摘要： A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current. The operating speed of the semiconductor memory device can be improved by combining the local sense amplifier with a current type data sense amplifier that does not require precharging and equalization during a read operation.
摘要翻译：半导体存储器件包括多个存储单元阵列块，位线读出放大器，可被控制为导通或截止的本地读出放大器，数据读出放大器和控制器。控制器响应于第一和第二信号激活预定持续时间的局部感测控制信号。第一信号是激活位线读出放大器的位线检测使能信号，并且在位线检测使能信号被激活之后局部读出放大器被激活预定的持续时间。第二信号与连接一对位线和一对本地输入/输出线的列选择线信号同相激活或去激活。因此，可以根据操作条件接通或关闭本地读出放大器，由此增加tRCD参数并减少电流消耗。可以通过组合本地读出放大器与在读取操作期间不需要预充电和均衡的电流型数据读出放大器来提高半导体存储器件的工作速度。

2. 发明申请

US20060028888A1 Semiconductor memory device having local sense amplifier with on/off control 有权
标题翻译：具有开/关控制的本地读出放大器的半导体存储器件
公开(公告)号：US20060028888A1
公开(公告)日：2006-02-09
申请号：US11188184
申请日：2005-07-20
申请人： Sang-Woong Shin , Chul-Soo Kim , Young-Hyun Jun , Sang-Bo Lee
发明人： Sang-Woong Shin , Chul-Soo Kim , Young-Hyun Jun , Sang-Bo Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/06 , G11C11/4091 , G11C2207/005 , G11C2207/065
摘要： A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current. The operating speed of the semiconductor memory device can be improved by combining the local sense amplifier with a current type data sense amplifier that does not require precharging and equalization during a read operation.
摘要翻译：半导体存储器件包括多个存储单元阵列块，位线读出放大器，可被控制为导通或截止的本地读出放大器，数据读出放大器和控制器。控制器响应于第一和第二信号激活预定持续时间的局部感测控制信号。第一信号是激活位线读出放大器的位线检测使能信号，并且在位线检测使能信号被激活之后局部读出放大器被激活预定的持续时间。第二信号与连接一对位线和一对本地输入/输出线的列选择线信号同相激活或去激活。因此，可以根据操作条件接通或关闭本地读出放大器，由此增加tRCD参数并减少电流消耗。可以通过组合本地读出放大器与在读取操作期间不需要预充电和均衡的电流型数据读出放大器来提高半导体存储器件的工作速度。

3. 发明申请

US20110069568A1 SEMICONDUCTOR MEMORY DEVICE HAVING LOCAL SENSE AMPLIFIER WITH ON/OFF CONTROL 审中-公开
标题翻译：具有开/关控制的本地信号放大器的半导体存储器件
公开(公告)号：US20110069568A1
公开(公告)日：2011-03-24
申请号：US12952328
申请日：2010-11-23
申请人： Sang-Woong Shin , Chul-Soo Kim , Young-Hyun Jun , Sang-Bo Lee
发明人： Sang-Woong Shin , Chul-Soo Kim , Young-Hyun Jun , Sang-Bo Lee
IPC分类号： G11C7/08 , G11C7/12 , G11C7/22
CPC分类号： G11C7/06 , G11C11/4091 , G11C2207/005 , G11C2207/065
摘要： A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current. The operating speed of the semiconductor memory device can be improved by combining the local sense amplifier with a current type data sense amplifier that does not require precharging and equalization during a read operation.
摘要翻译：半导体存储器件包括多个存储单元阵列块，位线读出放大器，可被控制为导通或截止的本地读出放大器，数据读出放大器和控制器。控制器响应于第一和第二信号激活预定持续时间的局部感测控制信号。第一信号是激活位线读出放大器的位线检测使能信号，并且在位线检测使能信号被激活之后局部读出放大器被激活预定的持续时间。第二信号与连接一对位线和一对本地输入/输出线的列选择线信号同相激活或去激活。因此，可以根据操作条件接通或关闭本地读出放大器，由此增加tRCD参数并减少电流消耗。可以通过组合本地读出放大器与在读取操作期间不需要预充电和均衡的电流型数据读出放大器来提高半导体存储器件的工作速度。

4. 发明授权

US07366822B2 Semiconductor memory device capable of reading and writing data at the same time 有权
标题翻译：能够同时读取和写入数据的半导体存储器件
公开(公告)号：US07366822B2
公开(公告)日：2008-04-29
申请号：US10840268
申请日：2004-05-07
申请人： Jin-Seok Kwak , Young-Hyun Jun , Seong-Jin Jang , Sang-Bo Lee , Min-Sang Park , Chul-Soo Kim
发明人： Jin-Seok Kwak , Young-Hyun Jun , Seong-Jin Jang , Sang-Bo Lee , Min-Sang Park , Chul-Soo Kim
IPC分类号： G06F12/00 , G11C8/00
CPC分类号： G11C7/1066 , G11C7/1072 , G11C11/4082 , G11C11/4087
摘要： A semiconductor memory device includes a plurality of banks. A data path may be divided into a read data path and a write data path, therefore, parallel processing of write and read commands are possible. The semiconductor memory device may include an address bank buffer, address buffer, column predecoder and/or a decoder. The semiconductor memory device may begin execution of a write command in a bank in one clock cycle and begin execution of a read command in the following clock cycle, therefore, bus efficiency is increased and/or write-to-read turn around time is reduced.
摘要翻译：半导体存储器件包括多个存储体。数据路径可以被划分为读取数据路径和写入数据路径，因此并行处理写入和读取命令是可能的。半导体存储器件可以包括地址库缓冲器，地址缓冲器，列预解码器和/或解码器。半导体存储器件可以在一个时钟周期内开始执行存储体中的写入命令，并且在随后的时钟周期开始执行读取命令，因此总线效率增加和/或写入读取时间减少。

5. 发明授权

US06603687B2 Semiconductor devices, circuits and methods for synchronizing the inputting and outputting data by internal clock signals derived from single feedback loop 失效
标题翻译：用于通过从单反馈环路导出的内部时钟信号来同步输入和输出数据的半导体器件，电路和方法
公开(公告)号：US06603687B2
公开(公告)日：2003-08-05
申请号：US10074592
申请日：2002-02-11
申请人： Young-Hyun Jun , Chul-Soo Kim , Ho-Young Song
发明人： Young-Hyun Jun , Chul-Soo Kim , Ho-Young Song
IPC分类号： G11C700
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/222
摘要： Devices, circuits and methods synchronize the inputting and outputting of groups of data into a memory cell array and out of a device. Synchronizing is performed by internal clock signals, both of which are derived from a single delay feedback loop.
摘要翻译：设备，电路和方法将数据组的输入和输出同步到存储单元阵列中并从设备中输出。通过内部时钟信号执行同步，两者都是从单个延迟反馈回路得出的。

6. 发明申请

US20110246857A1 MEMORY SYSTEM AND METHOD 审中-公开
标题翻译：记忆系统和方法
公开(公告)号：US20110246857A1
公开(公告)日：2011-10-06
申请号：US13078364
申请日：2011-04-01
申请人： Seung-Jun Bae , Kwang-Il Park , Young-Soo Sohn , Young-Hyun Jun , Joo-Sun Choi , Tae-Young Oh
发明人： Seung-Jun Bae , Kwang-Il Park , Young-Soo Sohn , Young-Hyun Jun , Joo-Sun Choi , Tae-Young Oh
IPC分类号： H03M13/09 , H03M13/05 , G06F11/10
CPC分类号： G06F11/1004 , H03M13/09
摘要： A memory system includes a memory controller and a memory device. The memory device exchanges data through a first channel with the memory controller, exchanges a first cyclic redundancy check (CRC) code associated with the data through a second channel with the memory controller, and receives a command/address packet including a second CRC code associated with a command/address from the memory controller through a third channel.
摘要翻译：存储器系统包括存储器控制器和存储器件。存储器件通过第一通道与存储器控制器交换数据，通过与存储器控制器的第二通道交换与数据相关联的第一循环冗余校验（CRC）代码，并且接收包括相关联的第二CRC码的命令/地址分组具有来自存储器控制器的命令/地址通过第三通道。

7. 发明授权

US07724073B2 Charge pump circuit 有权
标题翻译：电荷泵电路
公开(公告)号：US07724073B2
公开(公告)日：2010-05-25
申请号：US12287620
申请日：2008-10-10
申请人： Joung-Yeal Kim , Young-Hyun Jun , Bai-Sun Kong
发明人： Joung-Yeal Kim , Young-Hyun Jun , Bai-Sun Kong
IPC分类号： G05F3/02
CPC分类号： G11C5/145
摘要： A charge pump circuit includes initialization units, each of which initializes a boost node to an initialization voltage. Boosting units each boost the boost node to a higher voltage than the initialization voltage in response to an input voltage. First and second pump circuits each include a transfer unit for transferring a voltage of the boost node to an output node and sharing the output node. The transfer unit of the first pump circuit includes two transfer transistors that are switched in response to a voltage of a control node of the first pump circuit and the voltage of the boost node of the second pump circuit. The transfer unit of the second pump circuit includes two transfer transistors that are switched in response to a voltage of a control node of the second pump circuit and the voltage of the boost node of the first pump circuit.
摘要翻译：电荷泵电路包括初始化单元，每个初始化单元将升压节点初始化为初始化电压。升压单元各自将升压节点升压到比初始化电压高的电压以响应于输入电压。第一和第二泵电路各自包括用于将升压节点的电压传送到输出节点并共享输出节点的传送单元。第一泵电路的传送单元包括响应于第一泵电路的控制节点的电压和第二泵电路的升压节点的电压而被切换的两个传输晶体管。第二泵电路的传送单元包括响应于第二泵电路的控制节点的电压和第一泵电路的升压节点的电压而被切换的两个传输晶体管。

8. 发明申请

US20080122523A1 VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
标题翻译：电压发生电路和包括其的半导体存储器件
公开(公告)号：US20080122523A1
公开(公告)日：2008-05-29
申请号：US12025442
申请日：2008-02-04
申请人： Hyoung-Ryol Hwang , Young-Hyun Jun
发明人： Hyoung-Ryol Hwang , Young-Hyun Jun
IPC分类号： G05F3/02 , G05F3/16
CPC分类号： G11C5/14
摘要： A voltage generation circuit and semiconductor memory device including the same are provided. The voltage generation circuit includes: a voltage level detector, which detects a level of a first high voltage to generate a first high voltage level detection signal and detects a level of a second high voltage to generate a second high voltage level detection signal; a control signal generator, which generates at least four pumping control signals in sequence when the first high voltage level detection signal is active, generates a control signal when the first high voltage level detection signal is inactive, and generates a first one of the at least four pumping control signals in response to a level of a power supply voltage; and a voltage generator, which pumps a boost node in response to the at least four pumping control signals to generate the first high voltage and transmits charge from the boost node to a second high voltage generation terminal in response to the control signal to generate the second high voltage.
摘要翻译：提供了包括该电压产生电路和半导体存储器件的电压产生电路。电压产生电路包括：电压电平检测器，其检测第一高电平的电平以产生第一高电压电平检测信号，并检测第二高电平的电平以产生第二高电压电平检测信号; 控制信号发生器，当所述第一高电压电平检测信号有效时，依次产生至少四个泵送控制信号，当所述第一高电压电平检测信号无效时产生控制信号，并且产生至少四个泵送控制信号响应于电源电压的电平; 以及电压发生器，其响应于所述至少四个泵送控制信号泵送升压节点以产生所述第一高电压，并且响应于所述控制信号将电压从所述升压节点传输到第二高电压发生端子，以产生所述第二高电压高压。

9. 发明申请

US20050105315A1 Content addressable memory (CAM) capable of finding errors in a CAM cell array and a method thereof 失效
标题翻译：能够在CAM单元阵列中发现错误的内容可寻址存储器（CAM）及其方法
公开(公告)号：US20050105315A1
公开(公告)日：2005-05-19
申请号：US10973806
申请日：2004-10-26
申请人： Ho-Geun Shin , Young-Hyun Jun
发明人： Ho-Geun Shin , Young-Hyun Jun
IPC分类号： G11C15/00 , G11C29/08
CPC分类号： G11C29/08 , G11C15/00
摘要： A method of finding errors in a content addressable memory (CAM) and a CAM cell array, the CAM being capable of finding errors in the CAM cell array, is disclosed. The CAM includes the CAM cell array having a plurality of CAM cells and a match line state storing unit. The match line state storing unit is connected to a word line and a match line of the plurality of CAM cells and has a plurality of state cells in which a logic level of stored data is changed according to a logic level of the match line. Errors in the CAM cell array are found by reading data stored in the plurality of state cells. The data stored in the plurality of state cells are matched when there are no errors in the CAM cell array.
摘要翻译：公开了一种在内容可寻址存储器（CAM）和CAM单元阵列中发现错误的方法，CAM能够在CAM单元阵列中发现错误。 CAM包括具有多个CAM单元的CAM单元阵列和匹配线状态存储单元。匹配线状态存储单元连接到多个CAM单元的字线和匹配线，并且具有根据匹配线的逻辑电平改变存储数据的逻辑电平的多个状态单元。通过读取存储在多个状态单元中的数据来发现CAM单元阵列中的错误。当CAM单元阵列中没有错误时，存储在多个状态单元中的数据是匹配的。

10. 发明申请

US20050094448A1 Integrated circuit device with on-chip setup/hold measuring circuit 失效
标题翻译：具有片上建立/保持测量电路的集成电路器件
公开(公告)号：US20050094448A1
公开(公告)日：2005-05-05
申请号：US10972119
申请日：2004-10-21
申请人： Jong-Eon Lee , Young-Hyun Jun
发明人： Jong-Eon Lee , Young-Hyun Jun
IPC分类号： G11C7/00 , G11C29/50
CPC分类号： G11C29/50012 , G11C29/50
摘要： An integrated circuit device disclosed herein includes a test device and a setup and hold measuring circuit. The setup and hold measuring circuit generates a reference signal and a data signal in response to an external clock signal in a test mode of operation. The test device receives the data signal in response to a reference signal, and outputs the inputted data signal as a setup and hold determining circuit. One of the reference signal and the data signal is a multiphase signal synchronized with the external clock signal. The setup and hold measuring circuit detects whether the output of the test device indicates a valid value of the data signal, and generates the detected result to the external as a setup/hold timing margin through at least one pad.
摘要翻译：本文公开的集成电路装置包括测试装置和建立和保持测量电路。建立和保持测量电路在测试操作模式下响应外部时钟信号产生参考信号和数据信号。测试装置响应于参考信号接收数据信号，并输出输入的数据信号作为建立和保持确定电路。参考信号和数据信号之一是与外部时钟信号同步的多相信号。建立和保持测量电路检测测试装置的输出是否指示数据信号的有效值，并通过至少一个焊盘将检测结果作为建立/保持定时裕度产生到外部。

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