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    • 1. 发明授权
    • Method of fabricating a semiconductor device having a shallow source/drain region
    • 制造具有浅源/漏区的半导体器件的方法
    • US07217625B2
    • 2007-05-15
    • US10753447
    • 2004-01-09
    • Sang-Jin LeeKyung-Soo KimChang-Bong OhHee-Sung Kang
    • Sang-Jin LeeKyung-Soo KimChang-Bong OhHee-Sung Kang
    • H01L21/336
    • H01L29/6653H01L21/2652H01L21/26586H01L29/6656H01L29/6659H01L29/7833
    • A method of fabricating a semiconductor device forms a shallow source/drain region after a deep source/drain region. First, a gate insulating layer including a gate pattern and a gate electrode are formed on a semiconductor substrate. A buffer insulating layer, a first insulating layer, and a second insulating layer are then sequentially formed on the entire surface of the gate pattern and the semiconductor substrate. A first spacer is formed on the first insulating layer at both sidewalls of the gate pattern by etching the second insulating layer. A deep source/drain region is then formed on the semiconductor substrate as aligned by the first spacer. The first spacer is removed. Next, an offset spacer is formed at both sidewalls of the gate pattern by etching the first insulating layer. Finally, a shallow source/drain region is formed on the semiconductor substrate adjacent to the deep source/drain region as aligned by the offset spacer.
    • 半导体器件的制造方法在深源极/漏极区域之后形成浅的源极/漏极区域。 首先,在半导体基板上形成包括栅极图案和栅电极的栅极绝缘层。 然后在栅极图案和半导体衬底的整个表面上依次形成缓冲绝缘层,第一绝缘层和第二绝缘层。 通过蚀刻第二绝缘层,在栅极图案的两个侧壁的第一绝缘层上形成第一间隔物。 然后在第一间隔物对准的半导体衬底上形成深源/漏区。 第一个垫片被去除。 接下来,通过蚀刻第一绝缘层在栅极图案的两个侧壁处形成偏移间隔物。 最后,在与偏移间隔物对齐的深源/漏区附近的半导体衬底上形成浅源极/漏极区。
    • 3. 发明授权
    • Test device and semiconductor integrated circuit device
    • 测试器件和半导体集成电路器件
    • US08508017B2
    • 2013-08-13
    • US13067833
    • 2011-06-29
    • Sang-Jin LeeGin-Kyu Lee
    • Sang-Jin LeeGin-Kyu Lee
    • H01L21/70H01L23/58
    • G01R31/2884G01R31/025G11C11/41G11C29/02G11C29/24G11C29/50008H01L22/34
    • Test devices and integrated circuits with improved productivity are provided. In accordance with example embodiments, a test device may include a first test region with a first test element and a second test region with a second test element defined on a semiconductor substrate. The first test element may include a pair of first secondary test regions in the semiconductor substrate and a pair of first test gate lines. One of the first test gate lines may overlap one of the first secondary test regions and the other first test gate line may overlap the other first secondary test region. The second test element may include structures corresponding to the first test element except the second test element does not include structures corresponding to the pair of first secondary test regions and the pair of first test gate lines.
    • 提供了提高生产率的测试设备和集成电路。 根据示例实施例,测试设备可以包括具有第一测试元件的第一测试区域和具有限定在半导体衬底上的第二测试元件的第二测试区域。 第一测试元件可以包括半导体衬底中的一对第一次级测试区域和一对第一测试栅极线。 第一测试栅极线之一可以与第一次级测试区域中的一个重叠,而另一个第一测试栅极线可能与另一个第一次级测试区域重叠。 第二测试元件可以包括对应于第一测试元件的结构,除了第二测试元件不包括对应于该对第一次级测试区域对和该对第一测试栅极线对的结构。
    • 5. 发明授权
    • Test device and semiconductor integrated circuit device
    • 测试器件和半导体集成电路器件
    • US08258805B2
    • 2012-09-04
    • US12458535
    • 2009-07-15
    • Sang-Jin LeeGin-Kyu Lee
    • Sang-Jin LeeGin-Kyu Lee
    • G01R31/26H01L23/58
    • H01L22/34G11C11/41G11C29/50
    • A test device and a semiconductor integrated circuit are provided. The test device may include a first test region and a second test region defined on a semiconductor substrate. The first test region may include a first test element and the second region may include a second test element. The first test element may include a pair of first secondary test regions in the semiconductor substrate extending in a first direction. The second test element may include structures corresponding to the first test element except the second test element does not include structures corresponding to the pair of first secondary test regions.
    • 提供了一种测试装置和半导体集成电路。 测试装置可以包括限定在半导体衬底上的第一测试区域和第二测试区域。 第一测试区域可以包括第一测试元件,并且第二区域可以包括第二测试元件。 第一测试元件可以包括在第一方向上延伸的半导体衬底中的一对第一次级测试区域。 第二测试元件可以包括对应于第一测试元件的结构,除了第二测试元件不包括与该对第一次测试区对应的结构。
    • 7. 发明授权
    • Test device and semiconductor integrated circuit device
    • 测试器件和半导体集成电路器件
    • US07994811B2
    • 2011-08-09
    • US12385117
    • 2009-03-31
    • Sang-Jin LeeGin-Kyu Lee
    • Sang-Jin LeeGin-Kyu Lee
    • G01R31/02
    • G01R31/2884G01R31/025G11C11/41G11C29/02G11C29/24G11C29/50008H01L22/34
    • Test devices and integrated circuits with improved productivity are provided. In accordance with example embodiments, a test device may include a first test region with a first test element and a second test region with a second test element defined on a semiconductor substrate. The first test element may include a pair of first secondary test regions in the semiconductor substrate and a pair of first test gate lines. One of the first test gate lines may overlap one of the first secondary test regions and the other first test gate line may overlap the other first secondary test region. The second test element may include structures corresponding to the first test element except the second test element does not include structures corresponding to the pair of first secondary test regions and the pair of first test gate lines.
    • 提供了提高生产率的测试设备和集成电路。 根据示例实施例,测试设备可以包括具有第一测试元件的第一测试区域和具有限定在半导体衬底上的第二测试元件的第二测试区域。 第一测试元件可以包括半导体衬底中的一对第一次级测试区域和一对第一测试栅极线。 第一测试栅极线之一可以与第一次级测试区域中的一个重叠,而另一个第一测试栅极线可能与另一个第一次级测试区域重叠。 第二测试元件可以包括对应于第一测试元件的结构,除了第二测试元件不包括对应于该对第一次级测试区域对和该对第一测试栅极线对的结构。
    • 8. 发明申请
    • TOUCH PANEL DEVICE AND METHOD OF DETECTING CONTACT POSITION THEREOF
    • 触控面板装置及其接触位置检测方法
    • US20100277433A1
    • 2010-11-04
    • US12740470
    • 2008-04-30
    • Sang-Jin LeeChul-Yong JoungBang-Won Lee
    • Sang-Jin LeeChul-Yong JoungBang-Won Lee
    • G06F3/045
    • G06F3/044
    • Provided are a touch pad device and a method of detecting a contact position thereof. The touch panel device includes: a touch panel having a surface on which at least one pair of touch patterns formed of a conductive material are formed; and a touch sensor for generating a contact signal corresponding to a contact position of a contact object using impedances of a pair of touch patterns when the pair of touch patterns are contacted by the contact object. The touch panel device includes a plurality of pairs of touch patterns formed of a conductive material. A first axis position of a contact object is determined depending on whether or not the touch patterns are contacted by the contact object, and a second axis position of the contact object is determined by detecting variations in capacitance of the touch patterns or delay times by which a reference signal applied to the touch patterns is delayed. Thus, a contact position of the contact object can be detected using the first and second axis positions. Since the touch panel uses a one-layer ITO film, manufacturing the touch panel device with improved transparency can be easy and economical.
    • 提供了触摸板装置和检测其接触位置的方法。 触摸面板装置包括:触摸面板,其具有形成由导电材料形成的至少一对触摸图案的表面; 以及触摸传感器,用于当所述一对触摸图案被所述接触对象接触时,使用所述一对触摸图案的阻抗来产生与所述接触物体的接触位置相对应的接触信号。 触摸面板装置包括由导电材料形成的多对触摸图案。 接触物体的第一轴位置取决于接触物体是否接触触摸图案,并且通过检测触摸图案的电容的变化或延迟时间来确定接触物体的第二轴位置 施加到触摸图案的参考信号被延迟。 因此,可以使用第一和第二轴位置来检测接触物体的接触位置。 由于触摸面板使用单层ITO膜,所以制造具有提高的透明度的触摸面板装置可以容易且经济。
    • 9. 发明申请
    • Test device and semiconductor integrated circuit device
    • 测试器件和半导体集成电路器件
    • US20100013513A1
    • 2010-01-21
    • US12385117
    • 2009-03-31
    • Sang-Jin LeeGin-Kyu Lee
    • Sang-Jin LeeGin-Kyu Lee
    • G01R31/26H01L23/58
    • G01R31/2884G01R31/025G11C11/41G11C29/02G11C29/24G11C29/50008H01L22/34
    • Test devices and integrated circuits with improved productivity are provided. In accordance with example embodiments, a test device may include a first test region with a first test element and a second test region with a second test element defined on a semiconductor substrate. The first test element may include a pair of first secondary test regions in the semiconductor substrate and a pair of first test gate lines. One of the first test gate lines may overlap one of the first secondary test regions and the other first test gate line may overlap the other first secondary test region. The second test element may include structures corresponding to the first test element except the second test element does not include structures corresponding to the pair of first secondary test regions and the pair of first test gate lines.
    • 提供了提高生产率的测试设备和集成电路。 根据示例实施例,测试设备可以包括具有第一测试元件的第一测试区域和具有限定在半导体衬底上的第二测试元件的第二测试区域。 第一测试元件可以包括半导体衬底中的一对第一次级测试区域和一对第一测试栅极线。 第一测试栅极线之一可以与第一次级测试区域中的一个重叠,而另一个第一测试栅极线可能与另一个第一次级测试区域重叠。 第二测试元件可以包括对应于第一测试元件的结构,除了第二测试元件不包括对应于该对第一次级测试区域对和该对第一测试栅极线对的结构。