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1. 发明授权

US08691693B2 Methods of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08691693B2
公开(公告)日：2014-04-08
申请号：US13290285
申请日：2011-11-07
申请人： Sang-Jin Kim , Jong-Chan Shin , Yong-Kug Bae , Do-Hyoung Kim , Dong-Woon Park
发明人： Sang-Jin Kim , Jong-Chan Shin , Yong-Kug Bae , Do-Hyoung Kim , Dong-Woon Park
IPC分类号： H01L21/44 , H01L29/40
CPC分类号： H01L21/76895 , H01L21/28518 , H01L21/31144 , H01L21/76897 , H01L21/823418 , H01L21/823475 , H01L21/823481 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： In a method of manufacturing a semiconductor device, a first etching mask and a second etching mask are formed sequentially on a metal gate structure on a substrate and a first insulating interlayer covering a sidewall of the metal gate structure respectively. An opening is formed to expose a top surface of the substrate by removing a portion of the first insulating interlayer not overlapped with the first etching mask or the second etching mask. A metal silicide pattern is formed on the exposed top surface of the substrate. A plug on the metal silicide pattern is formed to fill a remaining portion of the opening. Further, a planarization layer may be used as the second etching mask.
摘要翻译：在制造半导体器件的方法中，依次在基板上的金属栅极结构和覆盖金属栅极结构的侧壁的第一绝缘夹层上形成第一蚀刻掩模和第二蚀刻掩模。通过除去与第一蚀刻掩模或第二蚀刻掩模不重叠的第一绝缘夹层的一部分，形成开口以暴露基板的顶表面。在衬底的暴露的顶表面上形成金属硅化物图案。形成金属硅化物图案上的塞子以填充开口的剩余部分。此外，可以使用平坦化层作为第二蚀刻掩模。

2. 发明申请

US20120122286A1 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120122286A1
公开(公告)日：2012-05-17
申请号：US13290285
申请日：2011-11-07
申请人： Sang-Jin Kim , Jong-Chan Shin , Yong-Kug Bae , Do-Hyoung Kim , Dong-Woon Park
发明人： Sang-Jin Kim , Jong-Chan Shin , Yong-Kug Bae , Do-Hyoung Kim , Dong-Woon Park
IPC分类号： H01L21/336 , H01L21/768
CPC分类号： H01L21/76895 , H01L21/28518 , H01L21/31144 , H01L21/76897 , H01L21/823418 , H01L21/823475 , H01L21/823481 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： In a method of manufacturing a semiconductor device, a first etching mask and a second etching mask are formed sequentially on a metal gate structure on a substrate and a first insulating interlayer covering a sidewall of the metal gate structure respectively. An opening is formed to expose a top surface of the substrate by removing a portion of the first insulating interlayer not overlapped with the first etching mask or the second etching mask. A metal silicide pattern is formed on the exposed top surface of the substrate. A plug on the metal silicide pattern is formed to fill a remaining portion of the opening. Further, a planarization layer may be used as the second etching mask.
摘要翻译：在制造半导体器件的方法中，依次在基板上的金属栅极结构和覆盖金属栅极结构的侧壁的第一绝缘夹层上形成第一蚀刻掩模和第二蚀刻掩模。通过除去与第一蚀刻掩模或第二蚀刻掩模不重叠的第一绝缘夹层的一部分，形成开口以暴露基板的顶表面。在衬底的暴露的顶表面上形成金属硅化物图案。形成金属硅化物图案上的塞子以填充开口的剩余部分。此外，可以使用平坦化层作为第二蚀刻掩模。

3. 发明授权

US08563383B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08563383B2
公开(公告)日：2013-10-22
申请号：US13252621
申请日：2011-10-04
申请人： Sang-Jin Kim , Jong-Chan Shin , Yong-Kug Bae , Myeong-Cheol Kim , Do-Hyoung Kim
发明人： Sang-Jin Kim , Jong-Chan Shin , Yong-Kug Bae , Myeong-Cheol Kim , Do-Hyoung Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/823425 , H01L21/823437 , H01L29/66545 , H01L29/66628 , H01L29/7834
摘要： A method of manufacturing a semiconductor device includes forming a plurality of gate structures including a metal on a substrate having an isolation layer, forming first insulating interlayer patterns covering sidewalls of the gate structures, forming first capping layer patterns and a second capping layer pattern on the gate structures and the first insulating interlayer patterns, the first capping layer patterns covering upper faces of the gate structures, and the second capping layer pattern overlapping the isolation layer, partially removing the first insulating interlayer patterns using the first and the second capping layer patterns as etching masks to form first openings that expose portions of the substrate, forming metal silicide patterns on the portions of the substrate exposed in the forming of the first openings, and forming conductive structures on the metal silicide patterns.
摘要翻译：制造半导体器件的方法包括在具有隔离层的衬底上形成包括金属的多个栅极结构，形成覆盖栅极结构的侧壁的第一绝缘层间图案，形成第一覆盖层图案和第二覆盖层图案栅极结构和第一绝缘层间图案，第一覆盖层图案覆盖栅极结构的上表面，第二覆盖层图案与隔离层重叠，使用第一和第二覆盖层图案部分地去除第一绝缘层间图案，如蚀刻掩模以形成暴露基板部分的第一开口，在形成第一开口的裸露部分上形成金属硅化物图案，并在金属硅化物图案上形成导电结构。

4. 发明申请

US20120122284A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120122284A1
公开(公告)日：2012-05-17
申请号：US13252621
申请日：2011-10-04
申请人： Sang-Jin KIM , Jong-Chan Shin , Yong-Kug Bae , Myeong-Cheol Kim , Do-Hyoung Kim
发明人： Sang-Jin KIM , Jong-Chan Shin , Yong-Kug Bae , Myeong-Cheol Kim , Do-Hyoung Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/823425 , H01L21/823437 , H01L29/66545 , H01L29/66628 , H01L29/7834
摘要： A method of manufacturing a semiconductor device includes forming a plurality of gate structures including a metal on a substrate having an isolation layer, forming first insulating interlayer patterns covering sidewalls of the gate structures, forming first capping layer patterns and a second capping layer pattern on the gate structures and the first insulating interlayer patterns, the first capping layer patterns covering upper faces of the gate structures, and the second capping layer pattern overlapping the isolation layer, partially removing the first insulating interlayer patterns using the first and the second capping layer patterns as etching masks to form first openings that expose portions of the substrate, forming metal silicide patterns on the portions of the substrate exposed in the forming of the first openings, and forming conductive structures on the metal silicide patterns.
摘要翻译：制造半导体器件的方法包括在具有隔离层的衬底上形成包括金属的多个栅极结构，形成覆盖栅极结构的侧壁的第一绝缘层间图案，形成第一覆盖层图案和第二覆盖层图案栅极结构和第一绝缘层间图案，第一覆盖层图案覆盖栅极结构的上表面，第二覆盖层图案与隔离层重叠，使用第一和第二覆盖层图案部分地去除第一绝缘层间图案，如蚀刻掩模以形成暴露基板部分的第一开口，在形成第一开口的裸露部分上形成金属硅化物图案，并在金属硅化物图案上形成导电结构。

5. 发明授权

US09711395B2 Overlay marks, methods of forming the same, and methods of fabricating semiconductor devices using the same 有权
公开(公告)号：US09711395B2
公开(公告)日：2017-07-18
申请号：US14810621
申请日：2015-07-28
申请人： Jong-Su Kim , Dong-Woon Park , Tae-Hoi Park , Yong-Kug Bae , Tae-Hwan Oh , Chang-Hoon Lee , Boo-Hyun Ham
发明人： Jong-Su Kim , Dong-Woon Park , Tae-Hoi Park , Yong-Kug Bae , Tae-Hwan Oh , Chang-Hoon Lee , Boo-Hyun Ham
IPC分类号： H01L21/768 , H01L21/8234 , H01L21/311 , H01L27/02 , G03F7/20 , H01L21/285
CPC分类号： H01L21/76816 , G03F7/70633 , G03F7/70683 , H01L21/28518 , H01L21/31144 , H01L21/76811 , H01L21/76897 , H01L21/823437 , H01L21/823475 , H01L27/0207
摘要： In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.

6. 发明申请

US20160035617A1 OVERLAY MARKS, METHODS OF FORMING THE SAME, AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES USING THE SAME 有权
标题翻译：叠加标记，其形成方法以及使用其制造半导体器件的方法
公开(公告)号：US20160035617A1
公开(公告)日：2016-02-04
申请号：US14810621
申请日：2015-07-28
申请人： Jong-Su Kim , Dong-Woon Park , Tae-Hoi Park , Yong-Kug Bae , Tae-Hwan Oh , Chang-Hoon Lee , Boo-Hyun Ham
发明人： Jong-Su Kim , Dong-Woon Park , Tae-Hoi Park , Yong-Kug Bae , Tae-Hwan Oh , Chang-Hoon Lee , Boo-Hyun Ham
IPC分类号： H01L21/768 , H01L21/285 , H01L21/311 , H01L21/8234 , H01L21/3213
CPC分类号： H01L21/76816 , G03F7/70633 , G03F7/70683 , H01L21/28518 , H01L21/31144 , H01L21/76811 , H01L21/76897 , H01L21/823437 , H01L21/823475 , H01L27/0207
摘要： In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.
摘要翻译：在制造半导体器件的方法中，提供了包括电路区域和覆盖标记区域的衬底。在电路区域中的基板上形成导电栅极图案，使得覆盖标记区域没有栅极图案，并且在基板上在电路区域中的栅极图案之间形成导电接触图案。在覆盖标记区域中的基板上形成反射镜图案，其中反射镜图案和接触图案包括相同的反射材料。还讨论了相关半导体器件，覆盖标记和制造方法。

7. 发明授权

US09349651B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09349651B2
公开(公告)日：2016-05-24
申请号：US14802643
申请日：2015-07-17
申请人： Jong-Su Kim , Hee-Young Go , Sang-Jin Kim , Yong-Kug Bae , Il-Young Yoon
发明人： Jong-Su Kim , Hee-Young Go , Sang-Jin Kim , Yong-Kug Bae , Il-Young Yoon
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/82 , H01L29/66 , H01L21/66 , H01L23/544 , H01L21/762
CPC分类号： H01L21/76224 , H01L22/30 , H01L23/544 , H01L2223/54426 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate including a circuit region and a scribe lane region, an active fin protruding from the substrate in the circuit region, a first gate structure extending over the active fin in the circuit region, and a second gate structure formed in the scribe lane region.
摘要翻译：提供一种半导体器件及其制造方法。该半导体器件包括：基板，包括电路区域和刻划通道区域;从电路区域中的基板突出的有源鳍片;在该电路区域中的有源鳍片上延伸的第一栅极结构;以及第二栅极结构，划线车道区域。

8. 发明申请

US20070026685A1 Mask structure, method of forming the mask structure, method of forming a pattern using the mask structure and method of forming contacts in a semiconductor device using the mask structure 审中-公开
标题翻译：掩模结构，形成掩模结构的方法，使用掩模结构形成图案的方法以及使用掩模结构在半导体器件中形成接触的方法
公开(公告)号：US20070026685A1
公开(公告)日：2007-02-01
申请号：US11481177
申请日：2006-07-06
申请人： Yong-Kug Bae , Ji-Yong You , Yong-Sun Ko , Seung-Won Seong
发明人： Yong-Kug Bae , Ji-Yong You , Yong-Sun Ko , Seung-Won Seong
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L21/76816
摘要： A mask structure may include a first mask pattern and a second mask pattern formed on an object. When the object includes a first material, the first and the second mask patterns may include a second material and a third material, respectively. The second mask pattern may have at least two openings that expose portions of the object adjacent to sides of the first mask pattern. Because the mask structure has the first and the second mask patterns, desired structures, for example, recesses, trenches, contact holes or patterns may be more precisely formed on or through the object. For example, the first mask pattern may protect the object in an etching process for forming contact holes so that the contact holes may not be connected to each other, for example, when the contact holes have bar shapes or line shapes.
摘要翻译：掩模结构可以包括形成在物体上的第一掩模图案和第二掩模图案。当物体包括第一材料时，第一和第二掩模图案可以分别包括第二材料和第三材料。第二掩模图案可以具有暴露邻近第一掩模图案的侧面的物体的部分的至少两个开口。由于掩模结构具有第一和第二掩模图案，所以可以更精确地形成所需的结构，例如凹槽，沟槽，接触孔或图案。例如，第一掩模图案可以在用于形成接触孔的蚀刻工艺中保护物体，使得接触孔可以不彼此连接，例如当接触孔具有条形或线形时。

9. 发明申请

US20060073670A1 Method of manufacturing a semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20060073670A1
公开(公告)日：2006-04-06
申请号：US11243397
申请日：2005-10-03
申请人： Yong-Kug Bae , Kwang-Sub Yoon , Young-Wook Park , Jung-Hyeon Lee
发明人： Yong-Kug Bae , Kwang-Sub Yoon , Young-Wook Park , Jung-Hyeon Lee
IPC分类号： H01L21/20 , H01L21/4763 , H01L21/8242
CPC分类号： H01L28/91 , H01L21/7682 , H01L27/10852 , H01L27/10894
摘要： In one embodiment, first and second multi-layer pattern structures are formed over first and second regions of a substrate, respectively. The first and second multi-layer pattern structures include first and second support layer patterns, respectively. The first and second multi-layer pattern structures define first and second openings, respectively. The first and second openings partially expose a portion of the first region and a portion of the second region, respectively. First and second liner patterns are formed on an inner face of the first opening and an inner face of the second opening, respectively. A first etching process is performed on the first multi-layer pattern structure until the first support layer pattern is removed. A second etching process is performed to remove the second multi-layer pattern structure except for the second support layer pattern.
摘要翻译：在一个实施例中，分别在衬底的第一和第二区域上形成第一和第二多层图案结构。第一和第二多层图案结构分别包括第一和第二支撑层图案。第一和第二多层图案结构分别限定第一和第二开口。第一和第二开口分别部分地暴露第一区域的一部分和第二区域的一部分。第一和第二衬里图案分别形成在第一开口的内表面和第二开口的内表面上。对第一多层图案结构进行第一蚀刻处理，直到第一支撑层图案被去除。执行第二蚀刻处理以除去除了第二支撑层图案之外的第二多层图案结构。

10. 发明申请

US20100096681A1 Cell structure for a semiconductor memory device and method of fabricating the same 失效
标题翻译：半导体存储器件的单元结构及其制造方法
公开(公告)号：US20100096681A1
公开(公告)日：2010-04-22
申请号：US12654255
申请日：2009-12-15
申请人： Kyoung-Yun Baek , Yong-Sun Ko , Hak Kim , Yong-Kug Bae
发明人： Kyoung-Yun Baek , Yong-Sun Ko , Hak Kim , Yong-Kug Bae
IPC分类号： H01L27/108
CPC分类号： H01L27/0207 , H01L27/10888
摘要： In a 6F2 cell structure of a memory device and a method of fabricating the same, the plurality of active regions may have a first area at both end portions and a second area at a central portion. A portion of a bit-line contact pad may be positioned on the second area and the other portion may be positioned on a third area of the substrate that may not overlap with the plurality of active regions. The bit line may be connected with the bit-line contact pad at the third area. The cell structure may be more easily formed despite a 6F2-structured unit cell. The plurality of active regions may have an elliptical shape including major and minor axes. The plurality of active regions may be positioned in a major axis direction to thereby form an active row, and may be positioned in a minor axis direction in such a structure that a center of the plurality of active regions is shifted from that of an adjacent active region in a neighboring active row.
摘要翻译：在存储器件的6F2单元结构及其制造方法中，多个有源区可以在两端部具有第一区域，在中心部分可以具有第二区域。位线接触焊盘的一部分可以位于第二区域上，另一部分可以位于基板的不与多个有源区域重叠的第三区域上。位线可以与第三区域的位线接触焊盘连接。尽管6F2结构的单元电池，电池结构也可以更容易地形成。多个有源区域可以具有包括主轴和短轴的椭圆形状。多个有源区域可以被定位在长轴方向上，从而形成有源行，并且可以以这样的结构定位在短轴方向上，使得多个有源区域的中心与相邻的活动区域的中心相邻活动行中的区域。

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