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    • 1. 发明授权
    • Method of fabricating thin film transistors
    • 制造薄膜晶体管的方法
    • US6077730A
    • 2000-06-20
    • US22415
    • 1998-02-12
    • Sang-Gul LeeJu-Cheon YeoYong-Min Ha
    • Sang-Gul LeeJu-Cheon YeoYong-Min Ha
    • H01L29/786H01L21/336H01L21/84
    • H01L27/127H01L29/78621
    • A method is provided for fabricating a thin film transistor on a substrate. The method includes the steps of forming an active layer having a channel region on the substrate, forming an impurity-blocking mask covering the channel region and portions of the active layer outside the channel region adjacent the channel region, and doping impurities of a first conductivity type at a high density into portions of the active layer uncovered by the impurity-blocking mask to form impurity-doped regions in the active layer. The method further includes the steps of removing the impurity-blocking mask and thereafter performing a plasma treatment on the resultant structure using a plasma gas containing impurities of the first conductivity type to form LDD regions in the active layer between the channel region and the impurity-doped regions.
    • 提供了一种在衬底上制造薄膜晶体管的方法。 该方法包括以下步骤:在衬底上形成具有沟道区的有源层,形成覆盖沟道区的杂质阻挡掩模和与沟道区相邻的沟道区之外的有源层的部分,以及掺杂第一导电性的杂质 以高密度键入由杂质阻挡掩模未覆盖的有源层的部分,以在有源层中形成杂质掺杂区域。 该方法还包括以下步骤:去除杂质阻挡掩模,然后使用含有第一导电类型的杂质的等离子气体对所得结构进行等离子体处理,以在沟道区和杂质阻挡掩模之间的有源层中形成LDD区, 掺杂区域。
    • 2. 发明授权
    • Thin film transistor having dual gate structure and a fabricating method thereof
    • 具有双栅极结构的薄膜晶体管及其制造方法
    • US06534788B1
    • 2003-03-18
    • US09364823
    • 1999-07-30
    • Ju-Cheon YeoHong-Seok ChoiYong-Min HaSang-Gul Lee
    • Ju-Cheon YeoHong-Seok ChoiYong-Min HaSang-Gul Lee
    • H01L2912
    • H01L29/6675H01L29/41733H01L29/78621H01L29/78645H01L29/78648
    • The present invention relates to a thin film transistor and a fabricating method thereof, wherein the source and drain wires are located on a substrate and a double gate structure is provided, whereby the driving capacity of on-current is improved and the degradation of a device is reduced. The TFT includes a substrate, a source electrode, a drain electrode and a lower gate electrode on the substrate, a buffer layer covering an exposed surface of the substrate as well as the source, drain and lower gate electrodes. An active layer is formed on the buffer layer, wherein a source region, a drain region, lightly-doped (LD) regions and a channel region are formed in the active layer. A gate insulating layer is formed on the channel and LD regions. An upper gate electrode is then formed on the gate insulating layer over the channel region. A passivation layer then covers the upper gate electrode. A plurality of contact holes are formed in the buffer and passivation layers, wherein the contact holes expose the source and drain electrodes and the source and drain regions. A first interconnection wire connects the source electrode to the source region. A second interconnection wire connects the drain electrode to the drain region.
    • 薄膜晶体管及其制造方法技术领域本发明涉及一种薄膜晶体管及其制造方法,其中源极和漏极布线位于基板上,并且提供双栅极结构,由此提高了导通电流的驱动能力和器件的劣化 降低了。 TFT包括衬底,源电极,漏电极和下栅电极,覆盖衬底的暴露表面的缓冲层以及源极,漏极和下栅电极。 在缓冲层上形成有源层,其中在有源层中形成源极区,漏极区,轻掺杂(LD)区和沟道区。 在沟道和LD区域上形成栅极绝缘层。 然后在沟道区上的栅绝缘层上形成上栅电极。 然后钝化层覆盖上栅电极。 在缓冲层和钝化层中形成多个接触孔,其中接触孔暴露出源极和漏极以及源极和漏极区。 第一互连线将源电极连接到源极区域。 第二互连线将漏极连接到漏极区。
    • 4. 发明授权
    • Liquid crystal display panel having a static electricity prevention
circuit and a method of operating the same
    • 具有静电防止电路的液晶显示面板及其操作方法
    • US5973658A
    • 1999-10-26
    • US873927
    • 1997-06-12
    • Seong-Gyun KimJu-Cheon Yeo
    • Seong-Gyun KimJu-Cheon Yeo
    • G02F1/1362G09G3/36
    • G02F1/136204G09G3/3648G09G2310/0248G09G2310/0251G09G2330/04Y10S345/904
    • A method and apparatus for controlling at least one transmission line in a liquid crystal display includes at least one transmission gate. The liquid crystal display includes a plurality of pixels, and each pixel includes a thin film transistor. At least one thin film transistor is connected to the transmission line. The transmission gate has first and second gates, an input and an output. The input is connected to the transmission line. The transmission gate transmits when one of a first voltage of said first gate is greater than a voltage of said input and a second voltage of said second gate is less than said voltage of said input. A first external terminal is connected to the first gate, a second external terminal is connected to the second gate, and a common external terminal is connected to the output of the transmission gate. When the first and second external terminals apply a floating potential, static electricity generated in the transmission line discharges through the transmission gate to the third external terminal. When a low and high voltage are respectively applied to the first and second external terminals, the transmission gate effectively isolates the transmission line. Alternatively, by applying a high and low voltage, respectively, to the first and second external terminals, the transmission line can be pre-charged via the transmission gate with a voltage applied to the common external terminal.
    • 用于控制液晶显示器中的至少一条传输线的方法和装置包括至少一个传输门。 液晶显示器包括多个像素,并且每个像素包括薄膜晶体管。 至少一个薄膜晶体管连接到传输线。 传输门具有第一和第二门,输入和输出。 输入端连接到传输线。 当所述第一门的第一电压之一大于所述输入的电压且所述第二门的第二电压小于所述输入的所述电压时,所述传输门传输。 第一外部端子连接到第一栅极,第二外部端子连接到第二栅极,并且公共外部端子连接到传输门的输出端。 当第一和第二外部端子施加浮动电位时,传输线中产生的静电通过传输门排放到第三外部端子。 当低电压和高电压分别施加到第一和第二外部端子时,传输门有效隔离传输线。 或者,通过分别向第一和第二外部端子施加高电压和低电压,可以通过传输门对施加到公共外部端子的电压进行预充电。
    • 7. 发明授权
    • Liquid crystal display device and method of manufacturing the same
    • 液晶显示装置及其制造方法
    • US06356319B1
    • 2002-03-12
    • US09629952
    • 2000-08-01
    • Jae-Deok ParkJu-Cheon Yeo
    • Jae-Deok ParkJu-Cheon Yeo
    • G02F1136
    • H01L29/78603G02F1/136286G02F1/1368G02F2001/13629
    • The present invention discloses a liquid crystal display device including a first insulating substrate having: a) a buffer layer formed on the first substrate; b) an inter-layer insulating film formed on the buffer layer, the inter-layer insulating film having an etching portion, the etching portion is etched; c) a semiconductor island formed on a portion of the buffer layer corresponding to the etching portion; d) data lines formed on the semiconductor island; e) gate lines arranged in a direction perpendicular to the data lines; f) switching elements arranged near cross points of the gate and data lines, each of the switching element having a gate electrode, a source electrode and a drain electrode, the gate electrode extending from the gate line, the source electrode extending from the data line; and g) pixel electrodes formed on a region defined by the gate and data lines, the pixel electrode connecting with the drain electrode, the pixel electrode overlapping an end portion of the data line, the adjacent two pixel electrodes spaced apart from each other; a second insulating substrate having a color filter; and a liquid crystal layer interposed between the first and second insulating substrates.
    • 本发明公开了一种液晶显示装置,包括:第一绝缘基板,具有:a)形成在第一基板上的缓冲层; b)形成在所述缓冲层上的层间绝缘膜,所述层间绝缘膜具有蚀刻部分,蚀刻所述蚀刻部分; c)形成在对应于蚀刻部分的缓冲层的一部分上的半导体岛; d)形成在半导体岛上的数据线; e)沿垂直于数据线的方向布置的栅极线; f)布置在栅极和数据线的交叉点附近的开关元件,每个开关元件具有栅电极,源电极和漏电极,栅电极从栅极线延伸,源电极从数据线延伸 ; 以及g)形成在由栅极和数据线限定的区域上的像素电极,与漏电极连接的像素电极,与数据线的端部重叠的像素电极,彼此间​​隔开的相邻的两个像素电极; 具有滤色器的第二绝缘基板; 以及插入在第一和第二绝缘基板之间的液晶层。
    • 8. 发明授权
    • Liquid crystal display with a protection layer formed by the layer used
to form the pixel electrode
    • 具有由用于形成像素电极的层形成的保护层的液晶显示器
    • US5990999A
    • 1999-11-23
    • US212992
    • 1998-12-16
    • Ju-Cheon Yeo
    • Ju-Cheon Yeo
    • G02F1/136G02F1/1333G02F1/1343G02F1/1362
    • G02F1/136227G02F1/133345G02F1/134309
    • A liquid crystal display includes a substrate, an active layer on the substrate, the active layer having a source region, a channel region and a drain region, a gate line including a gate electrode, the gate electrode overlapping the channel region of the active layer and the gate line having a gate insulating layer disposed underneath, an insulating interlayer covering the exposed surface of the substrate including the gate line, a first contact hole and a second contact hole exposing portions of the source region and the drain region in the insulating interlayer, respectively, a data line including a source electrode on the insulating interlayer, the source electrode connected to the source region and the data line crossing over the gate line, a drain electrode on the insulating interlayer, the drain electrode connected to the drain region, a passivation layer covering the exposed surface of the substrate including the data line and the drain electrode, a third contact hole exposing a portion of the drain electrode on the passivation layer, a pixel electrode connected to the drain electrode on the passivation layer, and a first etching preventing layer covering the crossing portion of the gate lines and the data lines.
    • 液晶显示器包括衬底,衬底上的有源层,有源层具有源极区,沟道区和漏极区,栅极线包括栅电极,栅电极与有源层的沟道区重叠 并且所述栅极线具有设置在其下方的栅极绝缘层,覆盖包括所述栅极线的所述基板的暴露表面的绝缘夹层,暴露在所述绝缘中间层中的所述源极区域和所述漏极区域的部分的第一接触孔和第二接触孔 分别包括绝缘中间层上的源极电极,与源极区域连接的源电极和与栅极线交叉的数据线的数据线,绝缘中间层上的漏极电极,与漏极区域连接的漏电极, 覆盖包括数据线和漏极的衬底的暴露表面的钝化层,暴露第三接触孔 钝化层上的漏电极的一部分,连接到钝化层上的漏电极的像素电极以及覆盖栅极线和数据线交叉部分的第一蚀刻防止层。
    • 10. 发明授权
    • Data driver for use in liquid crystal display
    • 用于液晶显示器的数据驱动器
    • US06489943B1
    • 2002-12-03
    • US09487663
    • 2000-01-19
    • Ju-Cheon Yeo
    • Ju-Cheon Yeo
    • G09G506
    • G09G3/2011G09G3/3688G09G2310/0259
    • A ramp signal application type of data driver in a liquid crystal display. The data driver includes a plurality of shift registers and sample and hold circuits that sample data lines. A plurality of timing control parts receive the sampled data from the sample and hold circuits and n timing signals having different periods from each other to thereby perform a logical operation. A plurality of transistors receive a ramp signal and are switched in accordance with the signals output by the timing control parts to output the ramp signal based on when the transistor is on and off.
    • 液晶显示器中的斜坡信号应用类型的数据驱动器。 数据驱动器包括对数据线进行采样的多个移位寄存器和采样保持电路。 多个定时控制部分从采样和保持电路接收采样数据,并且具有彼此不同周期的n个定时信号,从而执行逻辑运算。 多个晶体管接收斜坡信号,并且根据由定时控制部分输出的信号进行切换以基于晶体管何时导通和截止来输出斜坡信号。