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1. 发明授权

US07994851B2 PSK demodulator using time-to-digital converter 失效
标题翻译： PSK解调器采用时间 - 数字转换器
公开(公告)号：US07994851B2
公开(公告)日：2011-08-09
申请号：US12511323
申请日：2009-07-29
申请人： Sang Jin Byun , Jae Hoon Shim , Hyun Kyu Yu
发明人： Sang Jin Byun , Jae Hoon Shim , Hyun Kyu Yu
IPC分类号： H04L27/06 , H03D3/18
CPC分类号： H04L27/233 , H04L27/2338
摘要： A PSK demodulator using a time-to-digital converter includes: a filter unit that performs band pass filtering on a PSK signal; an amplitude limiting unit that limits the amplitude of an output signal of the filter unit; a clock signal generating unit that generates a clock signal; and a time-to-digital converter that samples the phase of an output signal of the amplitude limiting unit according to the clock signal and outputs a digital signal having a value corresponding to the phase of the PSK signal. Power consumption can be reduced and a circuit implementation can be simplified.
摘要翻译：使用时间 - 数字转换器的PSK解调器包括：对PSK信号执行带通滤波的滤波器单元; 幅度限制单元，限制滤波器单元的输出信号的幅度; 时钟信号生成单元，生成时钟信号; 以及时间 - 数字转换器，其根据时钟信号对幅度限制单元的输出信号的相位进行采样，并输出具有与PSK信号的相位对应的值的数字信号。可以降低功耗并简化电路实现。

2. 发明申请

US20070134852A1 Layout method of power line for semiconductor integrated circuit and semiconductor integrated circuit manufactured by the layout method 有权
标题翻译：半导体集成电路电源线布局方法和半导体集成电路布局方法
公开(公告)号：US20070134852A1
公开(公告)日：2007-06-14
申请号：US11523212
申请日：2006-09-19
申请人： Sang Jin Byun , Hyun Kyu Yu
发明人： Sang Jin Byun , Hyun Kyu Yu
IPC分类号： H01L21/82
CPC分类号： H01L27/0207
摘要： Provided are a layout method of a power line for a semiconductor integrated circuit and a semiconductor integrated circuit manufactured by the layout method. The layout method includes the steps of: forming a decoupling capacitor on a substrate; laying out a first metal layer, connected to the decoupling capacitor through a contact, above a region where the decoupling capacitor is formed so as to cover the decoupling capacitor; and laying out a second metal layer above a region where the first metal layer is formed. Therefore, the metal layers and the decoupling capacitor are laid out in the same region so that a chip area can be prevented from being additionally consumed at the time of laying out the decoupling capacitor, and degradation which may occur due to connection line resistance from the power lines to the decoupling capacitors can be prevented.
摘要翻译：提供了一种用于半导体集成电路的电力线的布局方法和通过布局方法制造的半导体集成电路。布局方法包括以下步骤：在衬底上形成去耦电容器; 在形成去耦电容器的区域上方布置第一金属层，其通过接触件连接到去耦电容器，以覆盖去耦电容器; 并在其上形成第一金属层的区域上方布置第二金属层。因此，金属层和去耦电容器布置在相同的区域中，使得在布置去耦电容器时可以防止芯片面积额外消耗，并且可能由于连接线电阻而导致的劣化可以防止到去耦电容器的电源线。

3. 发明授权

US07456063B2 Layout method of power line for semiconductor integrated circuit and semiconductor integrated circuit manufactured by the layout method 有权
标题翻译：半导体集成电路电源线布局方法和半导体集成电路布局方法
公开(公告)号：US07456063B2
公开(公告)日：2008-11-25
申请号：US11523212
申请日：2006-09-19
申请人： Sang Jin Byun , Hyun Kyu Yu
发明人： Sang Jin Byun , Hyun Kyu Yu
IPC分类号： H01L21/8242
CPC分类号： H01L27/0207
摘要： Provided are a layout method of a power line for a semiconductor integrated circuit and a semiconductor integrated circuit manufactured by the layout method. The layout method includes the steps of: forming a decoupling capacitor on a substrate; laying out a first metal layer, connected to the decoupling capacitor through a contact, above a region where the decoupling capacitor is formed so as to cover the decoupling capacitor; and laying out a second metal layer above a region where the first metal layer is formed. Therefore, the metal layers and the decoupling capacitor are laid out in the same region so that a chip area can be prevented from being additionally consumed at the time of laying out the decoupling capacitor, and degradation which may occur due to connection line resistance from the power lines to the decoupling capacitors can be prevented.
摘要翻译：提供了一种用于半导体集成电路的电力线的布局方法和通过布局方法制造的半导体集成电路。布局方法包括以下步骤：在衬底上形成去耦电容器; 在形成去耦电容器的区域上方布置第一金属层，其通过接触件连接到去耦电容器，以覆盖去耦电容器; 并在其上形成第一金属层的区域上方布置第二金属层。因此，金属层和去耦电容器布置在相同的区域中，使得在布置去耦电容器时可以防止芯片面积额外消耗，并且可能由于连接线电阻而导致的劣化可以防止到去耦电容器的电源线。

4. 发明申请

US20100090761A1 PSK DEMODULATOR USING TIME-TO-DIGITAL CONVERTER 失效
标题翻译：使用时间到数字转换器的PSK DEMODULATOR
公开(公告)号：US20100090761A1
公开(公告)日：2010-04-15
申请号：US12511323
申请日：2009-07-29
申请人： Sang Jin Byun , Jae Hoon Shim , Hyun Kyu Yu
发明人： Sang Jin Byun , Jae Hoon Shim , Hyun Kyu Yu
IPC分类号： H03D3/00
CPC分类号： H04L27/233 , H04L27/2338
摘要： A PSK demodulator using a time-to-digital converter includes: a filter unit that performs band pass filtering on a PSK signal; an amplitude limiting unit that limits the amplitude of an output signal of the filter unit; a clock signal generating unit that generates a clock signal; and a time-to-digital converter that samples the phase of an output signal of the amplitude limiting unit according to the clock signal and outputs a digital signal having a value corresponding to the phase of the PSK signal. Power consumption can be reduced and a circuit implementation can be simplified.
摘要翻译：使用时间 - 数字转换器的PSK解调器包括：对PSK信号执行带通滤波的滤波器单元; 幅度限制单元，限制滤波器单元的输出信号的幅度; 时钟信号生成单元，生成时钟信号; 以及时间 - 数字转换器，其根据时钟信号对幅度限制单元的输出信号的相位进行采样，并输出具有与PSK信号的相位对应的值的数字信号。可以降低功耗并简化电路实现。

5. 发明授权

US07429874B2 Replica bias circuit 有权
标题翻译：复制偏置电路
公开(公告)号：US07429874B2
公开(公告)日：2008-09-30
申请号：US11451962
申请日：2006-06-13
申请人： Sang Jin Byun , Hyun Kyu Yu
发明人： Sang Jin Byun , Hyun Kyu Yu
IPC分类号： H03K19/094
CPC分类号： H03F1/301 , H03F3/45183 , H03F2200/453 , H03F2200/456 , H03F2200/513
摘要： Provided is a replica bias circuit which is suitable for multi-layer stacked CMOS current mode logic (CML) and is stably used in application fields using a low power supply voltage. The replica bias circuit applies a reference voltage to gates of target transistors constituting an electronic circuit. The replica bias circuit includes a sub threshold voltage generator for maintaining a voltage difference lower than a threshold voltage of the transistor; and a replica path including devices designed by referring to dimensions of constituent devices forming a current flow path, the current flow path including the target transistors in the electronic circuit. With the replica bias circuit, multi-layer stacked CMOS current mode logic (CML) circuits can stably operate even at a low power supply voltage.
摘要翻译：提供了一种适用于多层堆叠CMOS电流模式逻辑（CML）的复制偏置电路，并且在使用低电源电压的应用领域中稳定地使用。复制偏置电路对构成电子电路的目标晶体管的栅极施加参考电压。复制偏置电路包括用于保持低于晶体管的阈值电压的电压差的副阈值电压发生器; 以及包括通过参考形成电流流路的构成装置的尺寸而设计的装置的复制路径，所述电流流路包括电子电路中的目标晶体管。利用复制偏置电路，即使在低电源电压下，多层堆叠CMOS电流模式逻辑（CML）电路也能稳定地工作。

6. 发明授权

US09013347B2 Radar apparatus 有权
标题翻译：雷达装置
公开(公告)号：US09013347B2
公开(公告)日：2015-04-21
申请号：US13445102
申请日：2012-04-12
申请人： Pil Jae Park , Cheon Soo Kim , Hyun Kyu Yu , Min Park , Ik Soo Eo
发明人： Pil Jae Park , Cheon Soo Kim , Hyun Kyu Yu , Min Park , Ik Soo Eo
IPC分类号： G01S13/74 , G01S13/08 , G01S13/58 , G01S13/32 , G01S7/00
CPC分类号： G01S13/325 , G01S7/003 , G01S13/584
摘要： An embodiment of the present invention relates to a radar apparatus, wherein a distance to a target and a velocity of the target are measured by transmitting a digitally modulated transmitting signal using a digital code and receiving and demodulating an echo signal returned due to reflection of the transmitting signal from the target.
摘要翻译：本发明的实施例涉及一种雷达装置，其中通过使用数字码发送数字调制的发射信号来测量与目标的距离和目标的速度，并且接收和解调由于反射而返回的回波信号从目标传输信号。

7. 发明授权

US08509353B2 Digital receiver 有权
标题翻译：数字接收机
公开(公告)号：US08509353B2
公开(公告)日：2013-08-13
申请号：US12818510
申请日：2010-06-18
申请人： Seon-Ho Han , Hyun Kyu Yu
发明人： Seon-Ho Han , Hyun Kyu Yu
IPC分类号： H03K9/00
CPC分类号： H04B1/0025 , H04B1/001
摘要： In a digital receiver, a noise attenuation and signal magnitude mapping variable amplifying unit includes a filter and an amplifier, amplifies and band-bass filters an analog signal and attenuating white noise and an interference signal other than a band signal. An ADC performs subsampling on a carrier frequency of a desired signal and performs oversampling on the band of the desired signal by using a sampling frequency to convert the analog signal which has passed through the noise attenuation and signal magnitude mapping variable amplifying unit into a digital signal of a direct conversion frequency band or an intermediate frequency band. The ADC has a dynamic range for processing both the desired signal and an undesired signal adjacent to the desired signal. A digital signal processing unit converts a signal frequency of the digital signal or digital-filters an undesired signal within the digital signal and processes the digital signal by digitally adjusting a gain.
摘要翻译：在数字接收机中，噪声衰减和信号幅度映射可变放大单元包括滤波器和放大器，对模拟信号进行放大和频带滤波，并衰减白噪声和除频带信号之外的干扰信号。 ADC在期望信号的载波频率上执行子采样，并通过使用采样频率对已经通过噪声衰减和信号幅度映射可变放大单元的模拟信号进行数字信号的期望信号的频带上的过采样，的直接转换频带或中频带。 ADC具有用于处理期望信号和与期望信号相邻的不期望信号的动态范围。数字信号处理单元转换数字信号的信号频率或数字滤波数字信号内的不需要的信号，并通过数字调节增益来处理数字信号。

8. 发明申请

US20130064148A1 SINGLE FREQUENCY SYNTHESIZER BASED FDD TRANSCEIVER 有权
标题翻译：单频合成器FDD收发器
公开(公告)号：US20130064148A1
公开(公告)日：2013-03-14
申请号：US13608677
申请日：2012-09-10
申请人： Hyun Ho BOO , Seon-Ho Han , Jang Hong Choi , Ik Soo Eo , Hyun Kyu Yu
发明人： Hyun Ho BOO , Seon-Ho Han , Jang Hong Choi , Ik Soo Eo , Hyun Kyu Yu
IPC分类号： H04J1/02
CPC分类号： H04L27/3836 , H04B1/0007 , H04L27/206 , H04L27/2092 , H04L27/2332 , H04L27/362 , H04L27/3854
摘要： The present invention relates to a single frequency synthesizer based FDD transceiver. A single frequency synthesizer generates and provides a carrier frequency so that frequency up-conversion and frequency down-conversion can be performed at the time of transmission and reception. Accordingly, the area, power consumption, and design complexity of the entire system can be reduced, and the performance of the system can be improved.
摘要翻译：本发明涉及一种基于单频合成器的FDD收发器。单个频率合成器产生并提供载波频率，使得可以在发送和接收时执行上变频和下变频。因此，可以降低整个系统的面积，功耗和设计复杂性，并且可以提高系统的性能。

9. 发明申请

US20130063199A1 PROGRAMMABLE COMPLEX MIXER 审中-公开
标题翻译：可编程复合混合器
公开(公告)号：US20130063199A1
公开(公告)日：2013-03-14
申请号：US13615423
申请日：2012-09-13
申请人： Seon-Ho HAN , Hyun Ho Boo , Mun Yang Park , Jang Hong Choi , Hyun Kyu Yu
发明人： Seon-Ho HAN , Hyun Ho Boo , Mun Yang Park , Jang Hong Choi , Hyun Kyu Yu
IPC分类号： G06G7/14
CPC分类号： H03D7/165
摘要： Disclosed is a programmable complex mixer. In accordance with the embodiments of the present invention, it is possible to control an output by programming paths and signs of internal signals in a complex mixer to reduce a processing bandwidth, power consumption, and a chip area in a transceiver, thereby improving performance of a transceiver.
摘要翻译：公开了一种可编程复合混合器。根据本发明的实施例，可以通过在复合混频器中编程内部信号的路径和符号来控制输出，以减少收发器中的处理带宽，功耗和芯片面积，从而提高收发器

10. 发明授权

US08217818B2 Digital RF converter and RF converting method thereof 有权
标题翻译：数字RF转换器及其RF转换方法
公开(公告)号：US08217818B2
公开(公告)日：2012-07-10
申请号：US12902125
申请日：2010-10-11
申请人： Jang Hong Choi , Hyun Ho Boo , Hyun Kyu Yu
发明人： Jang Hong Choi , Hyun Ho Boo , Hyun Kyu Yu
IPC分类号： H03M1/66
CPC分类号： H03M3/504 , H03M3/32
摘要： Provided are a digital radio frequency (RF) converter and an RF converting method thereof. The RF frequency converter includes first and second RF output terminals of a differential form outputting an RF signal; a differential switch selectively connecting first and second nodes into the first and second RF output terminals in response to an oscillating waveform; at least one digital delay device column outputting a plurality of unit bits by sequentially delaying an input bit corresponding to the digital input signal; a front-end processor summing an output of the at least one digital delay device column; a plurality of current sources; and a plurality of first switches corresponding to the plurality of current sources, respectively, and delivering currents of current sources whose number corresponds to the sum value of the front-end processor among the plurality of current sources, to one of the first and second nodes.
摘要翻译：提供一种数字射频（RF）转换器及其RF转换方法。 RF频率转换器包括输出RF信号的差分形式的第一和第二RF输出端; 差分开关响应于振荡波形选择性地将第一和第二节点连接到第一和第二RF输出端子中; 至少一个数字延迟装置列通过顺序地延迟对应于数字输入信号的输入位而输出多个单位位; 前端处理器对所述至少一个数字延迟装置列的输出求和; 多个电流源; 以及分别对应于多个电流源的多个第一开关，并将数量对应于多个电流源中的前端处理器的和值的电流源的电流传送到第一和第二节点之一。

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